22 : motherboard(motherboard_)
24 motherboard.getCommandController(),
"cputrace",
25 "CPU tracing on/off", false,
Setting::DONT_SAVE)
27 motherboard.getCommandController(),
"di_halt_callback",
28 "Tcl proc called when the CPU executed a DI/HALT sequence")
30 motherboard,
"z80", traceSetting,
31 diHaltCallback, EmuTime::zero()))
32 , r800(motherboard.isTurboR()
34 motherboard,
"r800", traceSetting,
35 diHaltCallback, EmuTime::zero())
37 , timeInfo(motherboard.getMachineInfoCommand())
38 , z80FreqInfo(motherboard.getMachineInfoCommand(),
"z80_freq", *z80)
40 ? std::make_unique<CPUFreqInfoTopic>(
41 motherboard.getMachineInfoCommand(),
"r800_freq", *r800)
43 , debuggable(motherboard_)
44 , reference(EmuTime::zero())
47 newZ80Active = z80Active;
51 traceSetting.
attach(*
this);
53 z80->freqLocked.attach(*
this);
54 z80->freqValue.attach(*
this);
56 r800->freqLocked.attach(*
this);
57 r800->freqValue.attach(*
this);
59 invalidateMemCacheSlot();
64 traceSetting.
detach(*
this);
65 z80->freqLocked.detach(*
this);
66 z80->freqValue.detach(*
this);
68 r800->freqLocked.detach(*
this);
69 r800->freqValue.detach(*
this);
77 interface = interface_;
78 z80 ->setInterface(interface);
79 if (r800) r800->setInterface(interface);
85 if (r800) r800->doReset(time);
97 if (tmp != z80Active) {
106 r800->setDRAMmode(dram);
109 void MSXCPU::execute(
bool fastForward)
111 if (z80Active != newZ80Active) {
112 EmuTime time = getCurrentTime();
113 z80Active = newZ80Active;
114 z80Active ? z80 ->warp(time)
117 auto zCache = z80 ->getCacheLines();
118 auto rCache = r800->getCacheLines();
119 auto from = z80Active ? rCache : zCache;
120 auto to = z80Active ? zCache : rCache;
124 z80Active ? z80 ->execute(fastForward)
125 : r800->execute(fastForward);
130 z80Active ? z80 ->exitCPULoopSync()
131 : r800->exitCPULoopSync();
135 z80Active ? z80 ->exitCPULoopAsync()
136 : r800->exitCPULoopAsync();
139 EmuTime::param MSXCPU::getCurrentTime()
const
141 return z80Active ? z80 ->getCurrentTime()
142 : r800->getCurrentTime();
147 z80Active ? z80 ->setNextSyncPoint(time)
148 : r800->setNextSyncPoint(time);
151 void MSXCPU::invalidateMemCacheSlot()
156 for (
auto i :
xrange(16)) {
164 byte from = slots[page];
165 byte to = 4 * primarySlot + secondarySlot;
168 auto [cpuReadLines, cpuWriteLines] = z80Active ? z80->getCacheLines() : r800->getCacheLines();
172 std::copy_n(&cpuReadLines [first], num, &slotReadLines [from][first]);
173 std::copy_n(&slotReadLines [to][first], num, &cpuReadLines [first]);
174 std::copy_n(&cpuWriteLines [first], num, &slotWriteLines[from][first]);
175 std::copy_n(&slotWriteLines[to][first], num, &cpuWriteLines [first]);
177 if (r800) r800->updateVisiblePage(page, primarySlot, secondarySlot);
183 auto [cpuReadLines, cpuWriteLines] = z80Active ? z80->getCacheLines() : r800->getCacheLines();
187 std::fill_n(cpuReadLines + first, num,
nullptr);
188 std::fill_n(cpuWriteLines + first, num,
nullptr);
190 for (
auto i :
xrange(16)) {
191 std::fill_n(slotReadLines [i] + first, num,
nullptr);
192 std::fill_n(slotWriteLines[i] + first, num,
nullptr);
196 template<
bool READ,
bool WRITE,
bool SUB_START>
197 void MSXCPU::setRWCache(
unsigned start,
unsigned size,
const byte* rData,
byte* wData,
int ps,
int ss,
198 const byte* disallowRead,
const byte* disallowWrite)
200 if constexpr (!SUB_START) {
201 assert(rData ==
nullptr);
202 assert(wData ==
nullptr);
209 int slot = 4 * ps + ss;
210 unsigned page = start >> 14;
211 assert(((start +
size - 1) >> 14) == page);
212 if constexpr (SUB_START && READ) rData -= start;
213 if constexpr (SUB_START && WRITE) wData -= start;
216 auto [readLines, writeLines] = [&] {
217 if (slot == slots[page]) {
218 return z80Active ? z80->getCacheLines() : r800->getCacheLines();
220 return CacheLines{slotReadLines [slot],
221 slotWriteLines[slot]};
228 disallowRead += first;
229 disallowWrite += first;
232 static auto*
const NON_CACHEABLE =
reinterpret_cast<byte*
>(1);
233 for (
auto i :
xrange(num)) {
234 if constexpr (READ) readLines [i] = disallowRead [i] ? NON_CACHEABLE : rData;
235 if constexpr (WRITE) writeLines[i] = disallowWrite[i] ? NON_CACHEABLE : wData;
239 static constexpr
void extendForAlignment(
unsigned& start,
unsigned&
size)
250 const byte* disallowRead,
const byte* disallowWrite)
253 extendForAlignment(start,
size);
254 setRWCache<true, true, false>(start,
size,
nullptr,
nullptr, ps, ss, disallowRead, disallowWrite);
257 const byte* disallowRead)
259 extendForAlignment(start,
size);
260 setRWCache<true, false, false>(start,
size,
nullptr,
nullptr, ps, ss, disallowRead,
nullptr);
263 const byte* disallowWrite)
265 extendForAlignment(start,
size);
266 setRWCache<false, true, false>(start,
size,
nullptr,
nullptr, ps, ss,
nullptr, disallowWrite);
270 const byte* disallowRead,
const byte* disallowWrite)
272 setRWCache<true, true, true>(start,
size, rData, wData, ps, ss, disallowRead, disallowWrite);
275 const byte* disallowRead)
277 setRWCache<true, false, true>(start,
size, rData,
nullptr, ps, ss, disallowRead,
nullptr);
280 const byte* disallowWrite)
282 setRWCache<false, true, true>(start,
size,
nullptr, wData, ps, ss,
nullptr, disallowWrite);
288 if (r800) r800->raiseIRQ();
293 if (r800) r800->lowerIRQ();
298 if (r800) r800->raiseNMI();
303 if (r800) r800->lowerNMI();
308 return z80Active ? z80 ->isM1Cycle(address)
309 : r800->isM1Cycle(address);
319 z80Active ? z80 ->wait(time)
325 return z80Active ? z80 ->waitCycles(time, cycles)
331 return z80Active ? time
332 : r800->waitCycles(time, cycles);
347 if (r800) r800->update(
setting);
354 Interpreter& interp, std::span<const TclObject> tokens,
357 z80Active ? z80 ->disasmCommand(interp, tokens, result)
358 : r800->disasmCommand(interp, tokens, result);
364 z80 ->setExtHALT(paused);
365 z80 ->exitCPULoopSync();
367 r800->setExtHALT(paused);
368 r800->exitCPULoopSync();
375 MSXCPU::TimeInfoTopic::TimeInfoTopic(
InfoCommand& machineInfoCommand)
380 void MSXCPU::TimeInfoTopic::execute(
381 std::span<const TclObject> , TclObject& result)
const
384 EmuDuration dur = cpu.getCurrentTime() - cpu.reference;
385 result = dur.toDouble();
388 std::string MSXCPU::TimeInfoTopic::help(std::span<const TclObject> )
const
390 return "Prints the time in seconds that the MSX is powered on\n";
396 MSXCPU::CPUFreqInfoTopic::CPUFreqInfoTopic(
397 InfoCommand& machineInfoCommand,
398 const std::string& name_,
CPUClock& clock_)
399 : InfoTopic(machineInfoCommand, name_)
404 void MSXCPU::CPUFreqInfoTopic::execute(
405 std::span<const TclObject> , TclObject& result)
const
407 result = clock.getFreq();
410 std::string MSXCPU::CPUFreqInfoTopic::help(std::span<const TclObject> )
const
412 return "Returns the actual frequency of this CPU.\n"
413 "This frequency can vary because:\n"
414 " - the user has overridden the freq via the '{z80,r800}_freq' setting\n"
415 " - (only on some MSX machines) the MSX software can switch the Z80 between 2 frequencies\n"
416 "See also the '{z80,r800}_freq_locked' setting.\n";
423 "Registers of the active CPU (Z80 or R800).\n"
424 "Each byte in this debuggable represents one 8 bit register:\n"
425 " 0 -> A 1 -> F 2 -> B 3 -> C\n"
426 " 4 -> D 5 -> E 6 -> H 7 -> L\n"
427 " 8 -> A' 9 -> F' 10 -> B' 11 -> C'\n"
428 " 12 -> D' 13 -> E' 14 -> H' 15 -> L'\n"
429 " 16 -> IXH 17 -> IXL 18 -> IYH 19 -> IYL\n"
430 " 20 -> PCH 21 -> PCL 22 -> SPH 23 -> SPL\n"
431 " 24 -> I 25 -> R 26 -> IM 27 -> IFF1/2\n"
432 "The last position (27) contains the IFF1 and IFF2 flags in respectively\n"
433 "bit 0 and 1. Bit 2 contains 'IFF1 AND last-instruction-was-not-EI', so\n"
434 "this effectively indicates that the CPU could accept an interrupt at\n"
435 "the start of the current instruction.\n";
442 byte MSXCPU::Debuggable::read(
unsigned address)
445 const CPURegs& regs = cpu.getRegisters();
447 case 0:
return regs.getA();
448 case 1:
return regs.getF();
449 case 2:
return regs.getB();
450 case 3:
return regs.getC();
451 case 4:
return regs.getD();
452 case 5:
return regs.getE();
453 case 6:
return regs.getH();
454 case 7:
return regs.getL();
455 case 8:
return regs.getA2();
456 case 9:
return regs.getF2();
457 case 10:
return regs.getB2();
458 case 11:
return regs.getC2();
459 case 12:
return regs.getD2();
460 case 13:
return regs.getE2();
461 case 14:
return regs.getH2();
462 case 15:
return regs.getL2();
463 case 16:
return regs.getIXh();
464 case 17:
return regs.getIXl();
465 case 18:
return regs.getIYh();
466 case 19:
return regs.getIYl();
467 case 20:
return regs.getPCh();
468 case 21:
return regs.getPCl();
469 case 22:
return regs.getSPh();
470 case 23:
return regs.getSPl();
471 case 24:
return regs.getI();
472 case 25:
return regs.getR();
473 case 26:
return regs.getIM();
474 case 27:
return 1 * regs.getIFF1() +
476 4 * (regs.getIFF1() && !regs.prevWasEI());
481 void MSXCPU::Debuggable::write(
unsigned address,
byte value)
484 CPURegs& regs = cpu.getRegisters();
486 case 0: regs.setA(value);
break;
487 case 1: regs.setF(value);
break;
488 case 2: regs.setB(value);
break;
489 case 3: regs.setC(value);
break;
490 case 4: regs.setD(value);
break;
491 case 5: regs.setE(value);
break;
492 case 6: regs.setH(value);
break;
493 case 7: regs.setL(value);
break;
494 case 8: regs.setA2(value);
break;
495 case 9: regs.setF2(value);
break;
496 case 10: regs.setB2(value);
break;
497 case 11: regs.setC2(value);
break;
498 case 12: regs.setD2(value);
break;
499 case 13: regs.setE2(value);
break;
500 case 14: regs.setH2(value);
break;
501 case 15: regs.setL2(value);
break;
502 case 16: regs.setIXh(value);
break;
503 case 17: regs.setIXl(value);
break;
504 case 18: regs.setIYh(value);
break;
505 case 19: regs.setIYl(value);
break;
506 case 20: regs.setPCh(value);
break;
507 case 21: regs.setPCl(value);
break;
508 case 22: regs.setSPh(value);
break;
509 case 23: regs.setSPl(value);
break;
510 case 24: regs.setI(value);
break;
511 case 25: regs.setR(value);
break;
513 if (value < 3) regs.setIM(value);
516 regs.setIFF1((value & 0x01) != 0);
517 regs.setIFF2((value & 0x02) != 0);
527 template<
typename Archive>
530 if (ar.versionAtLeast(version, 2)) {
531 ar.serialize(
"z80", *z80);
532 if (r800) ar.serialize(
"r800", *r800);
533 ar.serialize(
"z80Active", z80Active,
534 "newZ80Active", newZ80Active);
537 assert(Archive::IS_LOADER);
539 ar.serializeWithID(
"z80", *z80);
540 if (r800) ar.serializeWithID(
"r800", *r800);
543 ar.serializePointerID(
"activeCPU", activeCPU);
544 ar.serializePointerID(
"newCPU", newCPU);
545 z80Active = activeCPU == z80.get();
547 newZ80Active = newCPU == z80.get();
549 newZ80Active = z80Active;
552 ar.serialize(
"resetTime", reference);
554 if constexpr (Archive::IS_LOADER) {
555 invalidateMemCacheSlot();
556 invalidateAllSlotsRWCache(0x0000, 0x10000);
void setCPU(MSXCPU *cpu_)
void setZ80Freq(unsigned freq)
Switch the Z80 clock freq.
void fillWCache(unsigned start, unsigned size, byte *wData, int ps, int ss, const byte *disallowWrite)
bool isM1Cycle(unsigned address) const
Should only be used from within a MSXDevice::readMem() method.
void lowerNMI()
This methods lowers the non-maskable interrupt again.
void fillRWCache(unsigned start, unsigned size, const byte *rData, byte *wData, int ps, int ss, const byte *disallowRead, const byte *disallowWrite)
Fill the read and write cache lines for a specific slot with the specified value.
void setActiveCPU(CPUType cpu)
Switch between Z80/R800.
void invalidateAllSlotsRWCache(word start, unsigned size)
Invalidate the CPU its cache for the interval [start, start + size) For example MSXMemoryMapper and M...
void fillRCache(unsigned start, unsigned size, const byte *rData, int ps, int ss, const byte *disallowRead)
void updateVisiblePage(byte page, byte primarySlot, byte secondarySlot)
Inform CPU of bank switch.
void invalidateRWCache(unsigned start, unsigned size, int ps, int ss, const byte *disallowRead, const byte *disallowWrite)
Similar to the method above, but only invalidates one specific slot.
EmuTime waitCyclesR800(EmuTime::param time, unsigned cycles)
void exitCPULoopSync()
See CPUCore::exitCPULoopsync()
void disasmCommand(Interpreter &interp, std::span< const TclObject > tokens, TclObject &result) const
void setNextSyncPoint(EmuTime::param time)
EmuTime waitCyclesZ80(EmuTime::param time, unsigned cycles)
void raiseIRQ()
This method raises a maskable interrupt.
void raiseNMI()
This method raises a non-maskable interrupt.
void wait(EmuTime::param time)
void invalidateRCache(unsigned start, unsigned size, int ps, int ss, const byte *disallowRead)
void doReset(EmuTime::param time)
Reset CPU.
void setInterface(MSXCPUInterface *interf)
void setPaused(bool paused)
(un)pause CPU.
void exitCPULoopAsync()
See CPUCore::exitCPULoopAsync()
void setDRAMmode(bool dram)
Sets DRAM or ROM mode (influences memory access speed for R800).
void lowerIRQ()
This methods lowers the maskable interrupt again.
MSXCPU(MSXMotherBoard &motherboard)
void invalidateWCache(unsigned start, unsigned size, int ps, int ss, const byte *disallowWrite)
Scheduler & getScheduler()
void setCPU(MSXCPU *cpu_)
void detach(Observer< T > &observer)
void attach(Observer< T > &observer)
This file implemented 3 utility functions:
constexpr static_string_view CPU_REGS_DESC
uint16_t word
16 bit unsigned integer
void serialize(Archive &ar, T &t, unsigned version)
constexpr void fill(ForwardRange &&range, const T &value)
size_t size(std::string_view utf8)
#define OUTER(type, member)
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
constexpr auto xrange(T e)
constexpr auto end(const zstring_view &x)