25 : motherboard(motherboard_)
27 motherboard.getCommandController(),
"cputrace",
28 "CPU tracing on/off", false,
Setting::DONT_SAVE)
30 motherboard.getCommandController(),
"di_halt_callback",
31 "Tcl proc called when the CPU executed a DI/HALT sequence")
33 motherboard,
"z80", traceSetting,
34 diHaltCallback, EmuTime::zero()))
35 , r800(motherboard.isTurboR()
37 motherboard,
"r800", traceSetting,
38 diHaltCallback, EmuTime::zero())
40 , timeInfo(motherboard.getMachineInfoCommand())
41 , z80FreqInfo(motherboard.getMachineInfoCommand(),
"z80_freq", *z80)
43 ? std::make_unique<CPUFreqInfoTopic>(
44 motherboard.getMachineInfoCommand(),
"r800_freq", *r800)
46 , debuggable(motherboard_)
47 , reference(EmuTime::zero())
50 newZ80Active = z80Active;
54 traceSetting.
attach(*
this);
56 z80->freqLocked.attach(*
this);
57 z80->freqValue.attach(*
this);
59 r800->freqLocked.attach(*
this);
60 r800->freqValue.attach(*
this);
62 invalidateMemCacheSlot();
67 traceSetting.
detach(*
this);
68 z80->freqLocked.detach(*
this);
69 z80->freqValue.detach(*
this);
71 r800->freqLocked.detach(*
this);
72 r800->freqValue.detach(*
this);
80 interface = interface_;
81 z80 ->setInterface(interface);
82 if (r800) r800->setInterface(interface);
88 if (r800) r800->doReset(time);
100 if (tmp != z80Active) {
109 r800->setDRAMmode(dram);
112 void MSXCPU::execute(
bool fastForward)
114 if (z80Active != newZ80Active) {
115 EmuTime time = getCurrentTime();
116 z80Active = newZ80Active;
117 z80Active ? z80 ->warp(time)
120 auto zCache = z80 ->getCacheLines();
121 auto rCache = r800->getCacheLines();
122 auto from = z80Active ? rCache : zCache;
123 auto to = z80Active ? zCache : rCache;
127 z80Active ? z80 ->execute(fastForward)
128 : r800->execute(fastForward);
133 z80Active ? z80 ->exitCPULoopSync()
134 : r800->exitCPULoopSync();
138 z80Active ? z80 ->exitCPULoopAsync()
139 : r800->exitCPULoopAsync();
142 EmuTime::param MSXCPU::getCurrentTime()
const
144 return z80Active ? z80 ->getCurrentTime()
145 : r800->getCurrentTime();
150 z80Active ? z80 ->setNextSyncPoint(time)
151 : r800->setNextSyncPoint(time);
154 void MSXCPU::invalidateMemCacheSlot()
159 for (
auto i :
xrange(16)) {
167 byte from = slots[page];
168 byte to = 4 * primarySlot + secondarySlot;
171 auto [cpuReadLines, cpuWriteLines] = z80Active ? z80->getCacheLines() : r800->getCacheLines();
175 std::copy_n(&cpuReadLines [first], num, &slotReadLines [from][first]);
176 std::copy_n(&slotReadLines [to][first], num, &cpuReadLines [first]);
177 std::copy_n(&cpuWriteLines [first], num, &slotWriteLines[from][first]);
178 std::copy_n(&slotWriteLines[to][first], num, &cpuWriteLines [first]);
180 if (r800) r800->updateVisiblePage(page, primarySlot, secondarySlot);
186 auto [cpuReadLines, cpuWriteLines] = z80Active ? z80->getCacheLines() : r800->getCacheLines();
190 std::fill_n(cpuReadLines + first, num,
nullptr);
191 std::fill_n(cpuWriteLines + first, num,
nullptr);
193 for (
auto i :
xrange(16)) {
194 std::fill_n(slotReadLines [i] + first, num,
nullptr);
195 std::fill_n(slotWriteLines[i] + first, num,
nullptr);
199 template<
bool READ,
bool WRITE,
bool SUB_START>
200 void MSXCPU::setRWCache(
unsigned start,
unsigned size,
const byte* rData,
byte* wData,
int ps,
int ss,
201 const byte* disallowRead,
const byte* disallowWrite)
204 assert(rData ==
nullptr);
205 assert(wData ==
nullptr);
212 int slot = 4 * ps + ss;
213 unsigned page = start >> 14;
214 assert(((start +
size - 1) >> 14) == page);
215 if (SUB_START && READ) rData -= start;
216 if (SUB_START && WRITE) wData -= start;
219 auto [readLines, writeLines] = [&] {
220 if (slot == slots[page]) {
221 return z80Active ? z80->getCacheLines() : r800->getCacheLines();
223 return std::pair{slotReadLines [slot],
224 slotWriteLines[slot]};
231 disallowRead += first;
232 disallowWrite += first;
235 static auto*
const NON_CACHEABLE =
reinterpret_cast<byte*
>(1);
236 for (
auto i :
xrange(num)) {
237 if (READ) readLines [i] = disallowRead [i] ? NON_CACHEABLE : rData;
238 if (WRITE) writeLines[i] = disallowWrite[i] ? NON_CACHEABLE : wData;
242 static constexpr
void extendForAlignment(
unsigned& start,
unsigned&
size)
253 const byte* disallowRead,
const byte* disallowWrite)
256 extendForAlignment(start,
size);
257 setRWCache<true, true, false>(start,
size,
nullptr,
nullptr, ps, ss, disallowRead, disallowWrite);
260 const byte* disallowRead)
262 extendForAlignment(start,
size);
263 setRWCache<true, false, false>(start,
size,
nullptr,
nullptr, ps, ss, disallowRead,
nullptr);
266 const byte* disallowWrite)
268 extendForAlignment(start,
size);
269 setRWCache<false, true, false>(start,
size,
nullptr,
nullptr, ps, ss,
nullptr, disallowWrite);
273 const byte* disallowRead,
const byte* disallowWrite)
275 setRWCache<true, true, true>(start,
size, rData, wData, ps, ss, disallowRead, disallowWrite);
278 const byte* disallowRead)
280 setRWCache<true, false, true>(start,
size, rData,
nullptr, ps, ss, disallowRead,
nullptr);
283 const byte* disallowWrite)
285 setRWCache<false, true, true>(start,
size,
nullptr, wData, ps, ss,
nullptr, disallowWrite);
291 if (r800) r800->raiseIRQ();
296 if (r800) r800->lowerIRQ();
301 if (r800) r800->raiseNMI();
306 if (r800) r800->lowerNMI();
311 return z80Active ? z80 ->isM1Cycle(address)
312 : r800->isM1Cycle(address);
322 z80Active ? z80 ->wait(time)
328 return z80Active ? z80 ->waitCycles(time, cycles)
334 return z80Active ? time
335 : r800->waitCycles(time, cycles);
347 void MSXCPU::update(
const Setting& setting) noexcept
349 z80 ->update(setting);
350 if (r800) r800->update(setting);
360 z80Active ? z80 ->disasmCommand(interp, tokens, result)
361 : r800->disasmCommand(interp, tokens, result);
367 z80 ->setExtHALT(paused);
368 z80 ->exitCPULoopSync();
370 r800->setExtHALT(paused);
371 r800->exitCPULoopSync();
378 MSXCPU::TimeInfoTopic::TimeInfoTopic(
InfoCommand& machineInfoCommand)
383 void MSXCPU::TimeInfoTopic::execute(
387 EmuDuration dur = cpu.getCurrentTime() - cpu.reference;
388 result = dur.toDouble();
391 string MSXCPU::TimeInfoTopic::help(
const vector<string>& )
const
393 return "Prints the time in seconds that the MSX is powered on\n";
399 MSXCPU::CPUFreqInfoTopic::CPUFreqInfoTopic(
400 InfoCommand& machineInfoCommand,
401 const string& name_,
CPUClock& clock_)
402 : InfoTopic(machineInfoCommand, name_)
407 void MSXCPU::CPUFreqInfoTopic::execute(
410 result = clock.getFreq();
413 string MSXCPU::CPUFreqInfoTopic::help(
const vector<string>& )
const
415 return "Returns the actual frequency of this CPU.\n"
416 "This frequency can vary because:\n"
417 " - the user has overridden the freq via the '{z80,r800}_freq' setting\n"
418 " - (only on some MSX machines) the MSX software can switch the Z80 between 2 frequencies\n"
419 "See also the '{z80,r800}_freq_locked' setting.\n";
426 "Registers of the active CPU (Z80 or R800).\n"
427 "Each byte in this debuggable represents one 8 bit register:\n"
428 " 0 -> A 1 -> F 2 -> B 3 -> C\n"
429 " 4 -> D 5 -> E 6 -> H 7 -> L\n"
430 " 8 -> A' 9 -> F' 10 -> B' 11 -> C'\n"
431 " 12 -> D' 13 -> E' 14 -> H' 15 -> L'\n"
432 " 16 -> IXH 17 -> IXL 18 -> IYH 19 -> IYL\n"
433 " 20 -> PCH 21 -> PCL 22 -> SPH 23 -> SPL\n"
434 " 24 -> I 25 -> R 26 -> IM 27 -> IFF1/2\n"
435 "The last position (27) contains the IFF1 and IFF2 flags in respectively\n"
436 "bit 0 and 1. Bit 2 contains 'IFF1 AND last-instruction-was-not-EI', so\n"
437 "this effectively indicates that the CPU could accept an interrupt at\n"
438 "the start of the current instruction.\n";
445 byte MSXCPU::Debuggable::read(
unsigned address)
448 const CPURegs& regs = cpu.getRegisters();
450 case 0:
return regs.getA();
451 case 1:
return regs.getF();
452 case 2:
return regs.getB();
453 case 3:
return regs.getC();
454 case 4:
return regs.getD();
455 case 5:
return regs.getE();
456 case 6:
return regs.getH();
457 case 7:
return regs.getL();
458 case 8:
return regs.getA2();
459 case 9:
return regs.getF2();
460 case 10:
return regs.getB2();
461 case 11:
return regs.getC2();
462 case 12:
return regs.getD2();
463 case 13:
return regs.getE2();
464 case 14:
return regs.getH2();
465 case 15:
return regs.getL2();
466 case 16:
return regs.getIXh();
467 case 17:
return regs.getIXl();
468 case 18:
return regs.getIYh();
469 case 19:
return regs.getIYl();
470 case 20:
return regs.getPCh();
471 case 21:
return regs.getPCl();
472 case 22:
return regs.getSPh();
473 case 23:
return regs.getSPl();
474 case 24:
return regs.getI();
475 case 25:
return regs.getR();
476 case 26:
return regs.getIM();
477 case 27:
return 1 * regs.getIFF1() +
479 4 * (regs.getIFF1() && !regs.prevWasEI());
484 void MSXCPU::Debuggable::write(
unsigned address,
byte value)
487 CPURegs& regs = cpu.getRegisters();
489 case 0: regs.setA(value);
break;
490 case 1: regs.setF(value);
break;
491 case 2: regs.setB(value);
break;
492 case 3: regs.setC(value);
break;
493 case 4: regs.setD(value);
break;
494 case 5: regs.setE(value);
break;
495 case 6: regs.setH(value);
break;
496 case 7: regs.setL(value);
break;
497 case 8: regs.setA2(value);
break;
498 case 9: regs.setF2(value);
break;
499 case 10: regs.setB2(value);
break;
500 case 11: regs.setC2(value);
break;
501 case 12: regs.setD2(value);
break;
502 case 13: regs.setE2(value);
break;
503 case 14: regs.setH2(value);
break;
504 case 15: regs.setL2(value);
break;
505 case 16: regs.setIXh(value);
break;
506 case 17: regs.setIXl(value);
break;
507 case 18: regs.setIYh(value);
break;
508 case 19: regs.setIYl(value);
break;
509 case 20: regs.setPCh(value);
break;
510 case 21: regs.setPCl(value);
break;
511 case 22: regs.setSPh(value);
break;
512 case 23: regs.setSPl(value);
break;
513 case 24: regs.setI(value);
break;
514 case 25: regs.setR(value);
break;
516 if (value < 3) regs.setIM(value);
519 regs.setIFF1((value & 0x01) != 0);
520 regs.setIFF2((value & 0x02) != 0);
530 template<
typename Archive>
533 if (ar.versionAtLeast(version, 2)) {
534 ar.serialize(
"z80", *z80);
535 if (r800) ar.serialize(
"r800", *r800);
536 ar.serialize(
"z80Active", z80Active,
537 "newZ80Active", newZ80Active);
540 assert(ar.isLoader());
542 ar.serializeWithID(
"z80", *z80);
543 if (r800) ar.serializeWithID(
"r800", *r800);
546 ar.serializePointerID(
"activeCPU", activeCPU);
547 ar.serializePointerID(
"newCPU", newCPU);
548 z80Active = activeCPU == z80.get();
550 newZ80Active = newCPU == z80.get();
552 newZ80Active = z80Active;
555 ar.serialize(
"resetTime", reference);
558 invalidateMemCacheSlot();
559 invalidateAllSlotsRWCache(0x0000, 0x10000);
void setCPU(MSXCPU *cpu_)
void setZ80Freq(unsigned freq)
Switch the Z80 clock freq.
void fillWCache(unsigned start, unsigned size, byte *wData, int ps, int ss, const byte *disallowWrite)
bool isM1Cycle(unsigned address) const
Should only be used from within a MSXDevice::readMem() method.
void lowerNMI()
This methods lowers the non-maskable interrupt again.
void fillRWCache(unsigned start, unsigned size, const byte *rData, byte *wData, int ps, int ss, const byte *disallowRead, const byte *disallowWrite)
Fill the read and write cache lines for a specific slot with the specified value.
void setActiveCPU(CPUType cpu)
Switch between Z80/R800.
void disasmCommand(Interpreter &interp, span< const TclObject > tokens, TclObject &result) const
void invalidateAllSlotsRWCache(word start, unsigned size)
Invalidate the CPU its cache for the interval [start, start + size) For example MSXMemoryMapper and M...
void fillRCache(unsigned start, unsigned size, const byte *rData, int ps, int ss, const byte *disallowRead)
void updateVisiblePage(byte page, byte primarySlot, byte secondarySlot)
Inform CPU of bank switch.
void invalidateRWCache(unsigned start, unsigned size, int ps, int ss, const byte *disallowRead, const byte *disallowWrite)
Similar to the method above, but only invalidates one specific slot.
EmuTime waitCyclesR800(EmuTime::param time, unsigned cycles)
void exitCPULoopSync()
See CPUCore::exitCPULoopsync()
void setNextSyncPoint(EmuTime::param time)
EmuTime waitCyclesZ80(EmuTime::param time, unsigned cycles)
void raiseIRQ()
This method raises a maskable interrupt.
void raiseNMI()
This method raises a non-maskable interrupt.
void wait(EmuTime::param time)
void invalidateRCache(unsigned start, unsigned size, int ps, int ss, const byte *disallowRead)
void doReset(EmuTime::param time)
Reset CPU.
void setInterface(MSXCPUInterface *interf)
void setPaused(bool paused)
(un)pause CPU.
void exitCPULoopAsync()
See CPUCore::exitCPULoopAsync()
void setDRAMmode(bool dram)
Sets DRAM or ROM mode (influences memory access speed for R800).
void lowerIRQ()
This methods lowers the maskable interrupt again.
MSXCPU(MSXMotherBoard &motherboard)
void invalidateWCache(unsigned start, unsigned size, int ps, int ss, const byte *disallowWrite)
Scheduler & getScheduler()
void setCPU(MSXCPU *cpu_)
void detach(Observer< T > &observer)
void attach(Observer< T > &observer)
This file implemented 3 utility functions:
constexpr static_string_view CPU_REGS_DESC
uint16_t word
16 bit unsigned integer
void serialize(Archive &ar, T &t, unsigned version)
void fill(ForwardRange &&range, const T &value)
size_t size(std::string_view utf8)
#define OUTER(type, member)
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
constexpr auto xrange(T e)
constexpr auto end(const zstring_view &x)