openMSX
MSXCPU.cc
Go to the documentation of this file.
1 #include "MSXCPU.hh"
2 #include "MSXMotherBoard.hh"
3 #include "Debugger.hh"
4 #include "Scheduler.hh"
5 #include "IntegerSetting.hh"
6 #include "CPUCore.hh"
7 #include "Z80.hh"
8 #include "R800.hh"
9 #include "TclObject.hh"
10 #include "memory.hh"
11 #include "outer.hh"
12 #include "serialize.hh"
13 #include "unreachable.hh"
14 #include <cassert>
15 
16 using std::string;
17 using std::vector;
18 
19 namespace openmsx {
20 
22  : motherboard(motherboard_)
23  , traceSetting(
24  motherboard.getCommandController(), "cputrace",
25  "CPU tracing on/off", false, Setting::DONT_SAVE)
26  , diHaltCallback(
27  motherboard.getCommandController(), "di_halt_callback",
28  "Tcl proc called when the CPU executed a DI/HALT sequence")
29  , z80(make_unique<CPUCore<Z80TYPE>>(
30  motherboard, "z80", traceSetting,
31  diHaltCallback, EmuTime::zero))
32  , r800(motherboard.isTurboR()
34  motherboard, "r800", traceSetting,
35  diHaltCallback, EmuTime::zero)
36  : nullptr)
37  , timeInfo(motherboard.getMachineInfoCommand())
38  , z80FreqInfo(motherboard.getMachineInfoCommand(), "z80_freq", *z80)
39  , r800FreqInfo(r800
40  ? make_unique<CPUFreqInfoTopic>(
41  motherboard.getMachineInfoCommand(), "r800_freq", *r800)
42  : nullptr)
43  , debuggable(motherboard_)
44  , reference(EmuTime::zero)
45 {
46  z80Active = true; // setActiveCPU(CPU_Z80);
47  newZ80Active = z80Active;
48 
49  motherboard.getDebugger().setCPU(this);
50  motherboard.getScheduler().setCPU(this);
51  traceSetting.attach(*this);
52 
53  z80->freqLocked.attach(*this);
54  z80->freqValue.attach(*this);
55  if (r800) {
56  r800->freqLocked.attach(*this);
57  r800->freqValue.attach(*this);
58  }
59 }
60 
62 {
63  traceSetting.detach(*this);
64  z80->freqLocked.detach(*this);
65  z80->freqValue.detach(*this);
66  if (r800) {
67  r800->freqLocked.detach(*this);
68  r800->freqValue.detach(*this);
69  }
70  motherboard.getScheduler().setCPU(nullptr);
71  motherboard.getDebugger() .setCPU(nullptr);
72 }
73 
75 {
76  z80 ->setInterface(interface);
77  if (r800) r800->setInterface(interface);
78 }
79 
81 {
82  z80 ->doReset(time);
83  if (r800) r800->doReset(time);
84 
85  reference = time;
86 }
87 
89 {
90  if (cpu == CPU_R800) assert(r800);
91 
92  bool tmp = cpu == CPU_Z80;
93  if (tmp != z80Active) {
95  newZ80Active = tmp;
96  }
97 }
98 
99 void MSXCPU::setDRAMmode(bool dram)
100 {
101  assert(r800);
102  r800->setDRAMmode(dram);
103 }
104 
105 void MSXCPU::execute(bool fastForward)
106 {
107  if (z80Active != newZ80Active) {
108  EmuTime time = getCurrentTime();
109  z80Active = newZ80Active;
110  z80Active ? z80 ->warp(time)
111  : r800->warp(time);
112  invalidateMemCache(0x0000, 0x10000);
113  }
114  z80Active ? z80 ->execute(fastForward)
115  : r800->execute(fastForward);
116 }
117 
119 {
120  z80Active ? z80 ->exitCPULoopSync()
121  : r800->exitCPULoopSync();
122 }
124 {
125  z80Active ? z80 ->exitCPULoopAsync()
126  : r800->exitCPULoopAsync();
127 }
128 
129 EmuTime::param MSXCPU::getCurrentTime() const
130 {
131  return z80Active ? z80 ->getCurrentTime()
132  : r800->getCurrentTime();
133 }
134 
136 {
137  z80Active ? z80 ->setNextSyncPoint(time)
138  : r800->setNextSyncPoint(time);
139 }
140 
141 void MSXCPU::updateVisiblePage(byte page, byte primarySlot, byte secondarySlot)
142 {
143  invalidateMemCache(page * 0x4000, 0x4000);
144  if (r800) r800->updateVisiblePage(page, primarySlot, secondarySlot);
145 }
146 
147 void MSXCPU::invalidateMemCache(word start, unsigned size)
148 {
149  z80Active ? z80 ->invalidateMemCache(start, size)
150  : r800->invalidateMemCache(start, size);
151 }
152 
154 {
155  z80 ->raiseIRQ();
156  if (r800) r800->raiseIRQ();
157 }
159 {
160  z80 ->lowerIRQ();
161  if (r800) r800->lowerIRQ();
162 }
164 {
165  z80 ->raiseNMI();
166  if (r800) r800->raiseNMI();
167 }
169 {
170  z80 ->lowerNMI();
171  if (r800) r800->lowerNMI();
172 }
173 
174 bool MSXCPU::isM1Cycle(unsigned address) const
175 {
176  return z80Active ? z80 ->isM1Cycle(address)
177  : r800->isM1Cycle(address);
178 }
179 
180 void MSXCPU::setZ80Freq(unsigned freq)
181 {
182  z80->setFreq(freq);
183 }
184 
186 {
187  z80Active ? z80 ->wait(time)
188  : r800->wait(time);
189 }
190 
191 void MSXCPU::waitCycles(unsigned cycles)
192 {
193  z80Active ? z80 ->waitCycles(cycles)
194  : r800->waitCycles(cycles);
195 }
196 
197 void MSXCPU::waitCyclesR800(unsigned cycles)
198 {
199  if (isR800Active()) {
200  r800->waitCycles(cycles);
201  }
202 }
203 
205 {
206  if (z80Active) {
207  return *z80;
208  } else {
209  return *r800;
210  }
211 }
212 
213 void MSXCPU::update(const Setting& setting)
214 {
215  z80 ->update(setting);
216  if (r800) r800->update(setting);
217  exitCPULoopSync();
218 }
219 
220 // Command
221 
223  Interpreter& interp, array_ref<TclObject> tokens,
224  TclObject& result) const
225 {
226  z80Active ? z80 ->disasmCommand(interp, tokens, result)
227  : r800->disasmCommand(interp, tokens, result);
228 }
229 
230 void MSXCPU::setPaused(bool paused)
231 {
232  if (z80Active) {
233  z80 ->setExtHALT(paused);
234  z80 ->exitCPULoopSync();
235  } else {
236  r800->setExtHALT(paused);
237  r800->exitCPULoopSync();
238  }
239 }
240 
241 
242 // class TimeInfoTopic
243 
244 MSXCPU::TimeInfoTopic::TimeInfoTopic(InfoCommand& machineInfoCommand)
245  : InfoTopic(machineInfoCommand, "time")
246 {
247 }
248 
249 void MSXCPU::TimeInfoTopic::execute(
250  array_ref<TclObject> /*tokens*/, TclObject& result) const
251 {
252  auto& cpu = OUTER(MSXCPU, timeInfo);
253  EmuDuration dur = cpu.getCurrentTime() - cpu.reference;
254  result.setDouble(dur.toDouble());
255 }
256 
257 string MSXCPU::TimeInfoTopic::help(const vector<string>& /*tokens*/) const
258 {
259  return "Prints the time in seconds that the MSX is powered on\n";
260 }
261 
262 
263 // class CPUFreqInfoTopic
264 
265 MSXCPU::CPUFreqInfoTopic::CPUFreqInfoTopic(
266  InfoCommand& machineInfoCommand,
267  const string& name, CPUClock& clock_)
268  : InfoTopic(machineInfoCommand, name)
269  , clock(clock_)
270 {
271 }
272 
273 void MSXCPU::CPUFreqInfoTopic::execute(
274  array_ref<TclObject> /*tokens*/, TclObject& result) const
275 {
276  result.setInt(clock.getFreq());
277 }
278 
279 string MSXCPU::CPUFreqInfoTopic::help(const vector<string>& /*tokens*/) const
280 {
281  return "Returns the actual frequency of this CPU.\n"
282  "This frequency can vary because:\n"
283  " - the user has overridden the freq via the '{z80,r800}_freq' setting\n"
284  " - (only on some MSX machines) the MSX software can switch the Z80 between 2 frequencies\n"
285  "See also the '{z80,r800}_freq_locked' setting.\n";
286 }
287 
288 
289 // class Debuggable
290 
291 static const char* const CPU_REGS_DESC =
292  "Registers of the active CPU (Z80 or R800).\n"
293  "Each byte in this debuggable represents one 8 bit register:\n"
294  " 0 -> A 1 -> F 2 -> B 3 -> C\n"
295  " 4 -> D 5 -> E 6 -> H 7 -> L\n"
296  " 8 -> A' 9 -> F' 10 -> B' 11 -> C'\n"
297  " 12 -> D' 13 -> E' 14 -> H' 15 -> L'\n"
298  " 16 -> IXH 17 -> IXL 18 -> IYH 19 -> IYL\n"
299  " 20 -> PCH 21 -> PCL 22 -> SPH 23 -> SPL\n"
300  " 24 -> I 25 -> R 26 -> IM 27 -> IFF1/2\n"
301  "The last position (27) contains the IFF1 and IFF2 flags in respectively\n"
302  "bit 0 and 1. Bit 2 contains 'IFF1 AND last-instruction-was-not-EI', so\n"
303  "this effectively indicates that the CPU could accept an interrupt at\n"
304  "the start of the current instruction.\n";
305 
306 MSXCPU::Debuggable::Debuggable(MSXMotherBoard& motherboard)
307  : SimpleDebuggable(motherboard, "CPU regs", CPU_REGS_DESC, 28)
308 {
309 }
310 
311 byte MSXCPU::Debuggable::read(unsigned address)
312 {
313  auto& cpu = OUTER(MSXCPU, debuggable);
314  const CPURegs& regs = cpu.getRegisters();
315  switch (address) {
316  case 0: return regs.getA();
317  case 1: return regs.getF();
318  case 2: return regs.getB();
319  case 3: return regs.getC();
320  case 4: return regs.getD();
321  case 5: return regs.getE();
322  case 6: return regs.getH();
323  case 7: return regs.getL();
324  case 8: return regs.getA2();
325  case 9: return regs.getF2();
326  case 10: return regs.getB2();
327  case 11: return regs.getC2();
328  case 12: return regs.getD2();
329  case 13: return regs.getE2();
330  case 14: return regs.getH2();
331  case 15: return regs.getL2();
332  case 16: return regs.getIXh();
333  case 17: return regs.getIXl();
334  case 18: return regs.getIYh();
335  case 19: return regs.getIYl();
336  case 20: return regs.getPCh();
337  case 21: return regs.getPCl();
338  case 22: return regs.getSPh();
339  case 23: return regs.getSPl();
340  case 24: return regs.getI();
341  case 25: return regs.getR();
342  case 26: return regs.getIM();
343  case 27: return 1 * regs.getIFF1() +
344  2 * regs.getIFF2() +
345  4 * (regs.getIFF1() && !regs.debugGetAfterEI());
346  default: UNREACHABLE; return 0;
347  }
348 }
349 
350 void MSXCPU::Debuggable::write(unsigned address, byte value)
351 {
352  auto& cpu = OUTER(MSXCPU, debuggable);
353  CPURegs& regs = cpu.getRegisters();
354  switch (address) {
355  case 0: regs.setA(value); break;
356  case 1: regs.setF(value); break;
357  case 2: regs.setB(value); break;
358  case 3: regs.setC(value); break;
359  case 4: regs.setD(value); break;
360  case 5: regs.setE(value); break;
361  case 6: regs.setH(value); break;
362  case 7: regs.setL(value); break;
363  case 8: regs.setA2(value); break;
364  case 9: regs.setF2(value); break;
365  case 10: regs.setB2(value); break;
366  case 11: regs.setC2(value); break;
367  case 12: regs.setD2(value); break;
368  case 13: regs.setE2(value); break;
369  case 14: regs.setH2(value); break;
370  case 15: regs.setL2(value); break;
371  case 16: regs.setIXh(value); break;
372  case 17: regs.setIXl(value); break;
373  case 18: regs.setIYh(value); break;
374  case 19: regs.setIYl(value); break;
375  case 20: regs.setPCh(value); break;
376  case 21: regs.setPCl(value); break;
377  case 22: regs.setSPh(value); break;
378  case 23: regs.setSPl(value); break;
379  case 24: regs.setI(value); break;
380  case 25: regs.setR(value); break;
381  case 26:
382  if (value < 3) regs.setIM(value);
383  break;
384  case 27:
385  regs.setIFF1((value & 0x01) != 0);
386  regs.setIFF2((value & 0x02) != 0);
387  // can't change afterEI
388  break;
389  default:
390  UNREACHABLE;
391  }
392 }
393 
394 // version 1: initial version
395 // version 2: activeCPU,newCPU -> z80Active,newZ80Active
396 template<typename Archive>
397 void MSXCPU::serialize(Archive& ar, unsigned version)
398 {
399  if (ar.versionAtLeast(version, 2)) {
400  ar.serialize("z80", *z80);
401  if (r800) ar.serialize("r800", *r800);
402  ar.serialize("z80Active", z80Active);
403  ar.serialize("newZ80Active", newZ80Active);
404  } else {
405  // backwards-compatibility
406  assert(ar.isLoader());
407 
408  ar.serializeWithID("z80", *z80);
409  if (r800) ar.serializeWithID("r800", *r800);
410  CPUBase* activeCPU = nullptr;
411  CPUBase* newCPU = nullptr;
412  ar.serializePointerID("activeCPU", activeCPU);
413  ar.serializePointerID("newCPU", newCPU);
414  z80Active = activeCPU == z80.get();
415  if (newCPU) {
416  newZ80Active = newCPU == z80.get();
417  } else {
418  newZ80Active = z80Active;
419  }
420  }
421  ar.serialize("resetTime", reference);
422 }
424 
425 } // namespace openmsx
void raiseNMI()
This method raises a non-maskable interrupt.
Definition: MSXCPU.cc:163
void updateVisiblePage(byte page, byte primarySlot, byte secondarySlot)
Inform CPU of bank switch.
Definition: MSXCPU.cc:141
void lowerIRQ()
This methods lowers the maskable interrupt again.
Definition: MSXCPU.cc:158
void setNextSyncPoint(EmuTime::param time)
Definition: MSXCPU.cc:135
void exitCPULoopAsync()
See CPUCore::exitCPULoopAsync()
Definition: MSXCPU.cc:123
bool isM1Cycle(unsigned address) const
Should only be used from within a MSXDevice::readMem() method.
Definition: MSXCPU.cc:174
CPURegs & getRegisters()
Definition: MSXCPU.cc:204
void doReset(EmuTime::param time)
Reset CPU.
Definition: MSXCPU.cc:80
void disasmCommand(Interpreter &interp, array_ref< TclObject > tokens, TclObject &result) const
Definition: MSXCPU.cc:222
void setCPU(MSXCPU *cpu_)
Definition: Debugger.hh:38
void setPaused(bool paused)
(un)pause CPU.
Definition: MSXCPU.cc:230
MSXCPU(MSXMotherBoard &motherboard)
Definition: MSXCPU.cc:21
void invalidateMemCache(word start, unsigned size)
Invalidate the CPU its cache for the interval [start, start + size) For example MSXMemoryMapper and M...
Definition: MSXCPU.cc:147
void setDRAMmode(bool dram)
Sets DRAM or ROM mode (influences memory access speed for R800).
Definition: MSXCPU.cc:99
void attach(Observer< T > &observer)
Definition: Subject.hh:52
void wait(EmuTime::param time)
Definition: MSXCPU.cc:185
This class implements a subset of the proposal for std::array_ref (proposed for the next c++ standard...
Definition: array_ref.hh:19
void setCPU(MSXCPU *cpu_)
Definition: Scheduler.hh:43
void serialize(Archive &ar, unsigned version)
Definition: MSXCPU.cc:397
Thanks to enen for testing this on a real cartridge:
Definition: Autofire.cc:5
unsigned char byte
8 bit unsigned integer
Definition: openmsx.hh:25
void raiseIRQ()
This method raises a maskable interrupt.
Definition: MSXCPU.cc:153
void lowerNMI()
This methods lowers the non-maskable interrupt again.
Definition: MSXCPU.cc:168
void setInterface(MSXCPUInterface *interf)
Definition: MSXCPU.cc:74
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
Definition: serialize.hh:802
void waitCycles(unsigned cycles)
Definition: MSXCPU.cc:191
void setZ80Freq(unsigned freq)
Switch the Z80 clock freq.
Definition: MSXCPU.cc:180
size_t size() const
void detach(Observer< T > &observer)
Definition: Subject.hh:58
void exitCPULoopSync()
See CPUCore::exitCPULoopsync()
Definition: MSXCPU.cc:118
bool isR800Active() const
Is the R800 currently active?
Definition: MSXCPU.hh:96
void setActiveCPU(CPUType cpu)
Switch between Z80/R800.
Definition: MSXCPU.cc:88
#define OUTER(type, member)
Definition: outer.hh:38
void waitCyclesR800(unsigned cycles)
Definition: MSXCPU.cc:197
std::unique_ptr< T > make_unique()
Definition: memory.hh:27
unsigned short word
16 bit unsigned integer
Definition: openmsx.hh:28
#define UNREACHABLE
Definition: unreachable.hh:35