openMSX
MSXCPU.hh
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1 #ifndef MSXCPU_HH
2 #define MSXCPU_HH
3 
4 #include "InfoTopic.hh"
5 #include "SimpleDebuggable.hh"
6 #include "Observer.hh"
7 #include "BooleanSetting.hh"
8 #include "CacheLine.hh"
9 #include "EmuTime.hh"
10 #include "TclCallback.hh"
11 #include "serialize_meta.hh"
12 #include "openmsx.hh"
13 #include "span.hh"
14 #include <memory>
15 
16 namespace openmsx {
17 
18 class MSXMotherBoard;
19 class MSXCPUInterface;
20 class CPUClock;
21 class CPURegs;
22 class Z80TYPE;
23 class R800TYPE;
24 template<typename T> class CPUCore;
25 class TclObject;
26 class Interpreter;
27 
28 class MSXCPU final : private Observer<Setting>
29 {
30 public:
32 
33  explicit MSXCPU(MSXMotherBoard& motherboard);
34  ~MSXCPU();
35 
40  void doReset(EmuTime::param time);
41 
43  void setActiveCPU(CPUType cpu);
44 
46  void setDRAMmode(bool dram);
47 
50  void updateVisiblePage(byte page, byte primarySlot, byte secondarySlot);
51 
55  void invalidateAllSlotsRWCache(word start, unsigned size);
56 
62  void invalidateRWCache(unsigned start, unsigned size, int ps, int ss,
63  const byte* disallowRead, const byte* disallowWrite);
64  void invalidateRCache (unsigned start, unsigned size, int ps, int ss,
65  const byte* disallowRead);
66  void invalidateWCache (unsigned start, unsigned size, int ps, int ss,
67  const byte* disallowWrite);
68 
78  void fillRWCache(unsigned start, unsigned size, const byte* rData, byte* wData, int ps, int ss,
79  const byte* disallowRead, const byte* disallowWrite);
80  void fillRCache (unsigned start, unsigned size, const byte* rData, int ps, int ss,
81  const byte* disallowRead);
82  void fillWCache (unsigned start, unsigned size, byte* wData, int ps, int ss,
83  const byte* disallowWrite);
84 
90  void raiseIRQ();
91 
96  void lowerIRQ();
97 
103  void raiseNMI();
104 
109  void lowerNMI();
110 
116  [[nodiscard]] bool isM1Cycle(unsigned address) const;
117 
119  void exitCPULoopSync();
121  void exitCPULoopAsync();
122 
124  [[nodiscard]] bool isR800Active() const { return !z80Active; }
125 
127  void setZ80Freq(unsigned freq);
128 
129  void setInterface(MSXCPUInterface* interf);
130 
131  void disasmCommand(Interpreter& interp,
132  span<const TclObject> tokens,
133  TclObject& result) const;
134 
137  void setPaused(bool paused);
138 
139  void setNextSyncPoint(EmuTime::param time);
140 
141  void wait(EmuTime::param time);
142  EmuTime waitCyclesZ80(EmuTime::param time, unsigned cycles);
143  EmuTime waitCyclesR800(EmuTime::param time, unsigned cycles);
144 
145  [[nodiscard]] CPURegs& getRegisters();
146 
147  template<typename Archive>
148  void serialize(Archive& ar, unsigned version);
149 
150 private:
151  void invalidateMemCacheSlot();
152 
153  // only for MSXMotherBoard
154  void execute(bool fastForward);
155  friend class MSXMotherBoard;
156 
162  EmuTime::param getCurrentTime() const;
163 
164  // Observer<Setting>
165  void update(const Setting& setting) noexcept override;
166 
167  template<bool READ, bool WRITE, bool SUB_START>
168  void setRWCache(unsigned start, unsigned size, const byte* rData, byte* wData, int ps, int ss,
169  const byte* disallowRead, const byte* disallowWrite);
170 
171 private:
172  MSXMotherBoard& motherboard;
173  BooleanSetting traceSetting;
174  TclCallback diHaltCallback;
175  const std::unique_ptr<CPUCore<Z80TYPE>> z80;
176  const std::unique_ptr<CPUCore<R800TYPE>> r800; // can be nullptr
177 
178  const byte* slotReadLines [16][CacheLine::NUM];
179  byte* slotWriteLines[16][CacheLine::NUM];
180  byte slots[4]; // active slot for page (= 4 * primSlot + secSlot)
181 
182  struct TimeInfoTopic final : InfoTopic {
183  explicit TimeInfoTopic(InfoCommand& machineInfoCommand);
184  void execute(span<const TclObject> tokens,
185  TclObject& result) const override;
186  [[nodiscard]] std::string help(span<const TclObject> tokens) const override;
187  } timeInfo;
188 
189  class CPUFreqInfoTopic final : public InfoTopic {
190  public:
191  CPUFreqInfoTopic(InfoCommand& machineInfoCommand,
192  const std::string& name, CPUClock& clock);
193  void execute(span<const TclObject> tokens,
194  TclObject& result) const override;
195  [[nodiscard]] std::string help(span<const TclObject> tokens) const override;
196  private:
197  CPUClock& clock;
198  };
199  CPUFreqInfoTopic z80FreqInfo; // always present
200  const std::unique_ptr<CPUFreqInfoTopic> r800FreqInfo; // can be nullptr
201 
202  struct Debuggable final : SimpleDebuggable {
203  explicit Debuggable(MSXMotherBoard& motherboard);
204  [[nodiscard]] byte read(unsigned address) override;
205  void write(unsigned address, byte value) override;
206  } debuggable;
207 
208  EmuTime reference;
209  bool z80Active;
210  bool newZ80Active;
211 
212  MSXCPUInterface* interface = nullptr; // only used for debug
213 };
215 
216 } // namespace openmsx
217 
218 #endif
BaseSetting * setting
Definition: Interpreter.cc:27
void setZ80Freq(unsigned freq)
Switch the Z80 clock freq.
Definition: MSXCPU.cc:312
void fillWCache(unsigned start, unsigned size, byte *wData, int ps, int ss, const byte *disallowWrite)
Definition: MSXCPU.cc:279
bool isM1Cycle(unsigned address) const
Should only be used from within a MSXDevice::readMem() method.
Definition: MSXCPU.cc:306
void lowerNMI()
This methods lowers the non-maskable interrupt again.
Definition: MSXCPU.cc:300
void serialize(Archive &ar, unsigned version)
Definition: MSXCPU.cc:528
void fillRWCache(unsigned start, unsigned size, const byte *rData, byte *wData, int ps, int ss, const byte *disallowRead, const byte *disallowWrite)
Fill the read and write cache lines for a specific slot with the specified value.
Definition: MSXCPU.cc:269
void setActiveCPU(CPUType cpu)
Switch between Z80/R800.
Definition: MSXCPU.cc:92
void disasmCommand(Interpreter &interp, span< const TclObject > tokens, TclObject &result) const
Definition: MSXCPU.cc:353
void invalidateAllSlotsRWCache(word start, unsigned size)
Invalidate the CPU its cache for the interval [start, start + size) For example MSXMemoryMapper and M...
Definition: MSXCPU.cc:180
void fillRCache(unsigned start, unsigned size, const byte *rData, int ps, int ss, const byte *disallowRead)
Definition: MSXCPU.cc:274
void updateVisiblePage(byte page, byte primarySlot, byte secondarySlot)
Inform CPU of bank switch.
Definition: MSXCPU.cc:162
void invalidateRWCache(unsigned start, unsigned size, int ps, int ss, const byte *disallowRead, const byte *disallowWrite)
Similar to the method above, but only invalidates one specific slot.
Definition: MSXCPU.cc:249
CPURegs & getRegisters()
Definition: MSXCPU.cc:335
bool isR800Active() const
Is the R800 currently active?
Definition: MSXCPU.hh:124
EmuTime waitCyclesR800(EmuTime::param time, unsigned cycles)
Definition: MSXCPU.cc:329
void exitCPULoopSync()
See CPUCore::exitCPULoopsync()
Definition: MSXCPU.cc:128
void setNextSyncPoint(EmuTime::param time)
Definition: MSXCPU.cc:145
EmuTime waitCyclesZ80(EmuTime::param time, unsigned cycles)
Definition: MSXCPU.cc:323
void raiseIRQ()
This method raises a maskable interrupt.
Definition: MSXCPU.cc:285
void raiseNMI()
This method raises a non-maskable interrupt.
Definition: MSXCPU.cc:295
void wait(EmuTime::param time)
Definition: MSXCPU.cc:317
void invalidateRCache(unsigned start, unsigned size, int ps, int ss, const byte *disallowRead)
Definition: MSXCPU.cc:256
void doReset(EmuTime::param time)
Reset CPU.
Definition: MSXCPU.cc:82
void setInterface(MSXCPUInterface *interf)
Definition: MSXCPU.cc:75
void setPaused(bool paused)
(un)pause CPU.
Definition: MSXCPU.cc:361
void exitCPULoopAsync()
See CPUCore::exitCPULoopAsync()
Definition: MSXCPU.cc:133
friend class MSXMotherBoard
Definition: MSXCPU.hh:155
void setDRAMmode(bool dram)
Sets DRAM or ROM mode (influences memory access speed for R800).
Definition: MSXCPU.cc:103
void lowerIRQ()
This methods lowers the maskable interrupt again.
Definition: MSXCPU.cc:290
MSXCPU(MSXMotherBoard &motherboard)
Definition: MSXCPU.cc:21
void invalidateWCache(unsigned start, unsigned size, int ps, int ss, const byte *disallowWrite)
Definition: MSXCPU.cc:262
Generic Gang-of-Four Observer class, templatized edition.
Definition: Observer.hh:10
Definition: span.hh:126
constexpr unsigned NUM
Definition: CacheLine.hh:8
This file implemented 3 utility functions:
Definition: Autofire.cc:9
uint16_t word
16 bit unsigned integer
Definition: openmsx.hh:29
SERIALIZE_CLASS_VERSION(CassettePlayer, 2)
size_t size(std::string_view utf8)