openMSX
MSXCPU.hh
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1#ifndef MSXCPU_HH
2#define MSXCPU_HH
3
4#include "InfoTopic.hh"
5#include "SimpleDebuggable.hh"
6#include "Observer.hh"
7#include "BooleanSetting.hh"
8#include "CacheLine.hh"
9#include "EmuTime.hh"
10#include "TclCallback.hh"
11#include "serialize_meta.hh"
12#include "openmsx.hh"
13
14#include <array>
15#include <memory>
16#include <span>
17
18namespace openmsx {
19
20class MSXMotherBoard;
21class MSXCPUInterface;
22class CPUClock;
23class CPURegs;
24class Z80TYPE;
25class R800TYPE;
26template<typename T> class CPUCore;
27class TclObject;
28class Interpreter;
29
30class MSXCPU final : private Observer<Setting>
31{
32public:
33 enum class Type { Z80, R800 };
34
35 explicit MSXCPU(MSXMotherBoard& motherboard);
36 ~MSXCPU();
37
42 void doReset(EmuTime::param time);
43
45 void setActiveCPU(Type cpu);
46
48 void setDRAMmode(bool dram);
49
52 void updateVisiblePage(byte page, byte primarySlot, byte secondarySlot);
53
57 void invalidateAllSlotsRWCache(word start, unsigned size);
58
64 void invalidateRWCache(unsigned start, unsigned size, int ps, int ss,
65 std::span<const byte, 256> disallowRead,
66 std::span<const byte, 256> disallowWrite);
67 void invalidateRCache (unsigned start, unsigned size, int ps, int ss,
68 std::span<const byte, 256> disallowRead,
69 std::span<const byte, 256> disallowWrite);
70 void invalidateWCache (unsigned start, unsigned size, int ps, int ss,
71 std::span<const byte, 256> disallowRead,
72 std::span<const byte, 256> disallowWrite);
73
83 void fillRWCache(unsigned start, unsigned size, const byte* rData, byte* wData, int ps, int ss,
84 std::span<const byte, 256> disallowRead,
85 std::span<const byte, 256> disallowWrite);
86 void fillRCache (unsigned start, unsigned size, const byte* rData, int ps, int ss,
87 std::span<const byte, 256> disallowRead,
88 std::span<const byte, 256> disallowWrite);
89 void fillWCache (unsigned start, unsigned size, byte* wData, int ps, int ss,
90 std::span<const byte, 256> disallowRead,
91 std::span<const byte, 256> disallowWrite);
92
98 void raiseIRQ();
99
104 void lowerIRQ();
105
111 void raiseNMI();
112
117 void lowerNMI();
118
124 [[nodiscard]] bool isM1Cycle(unsigned address) const;
125
127 void exitCPULoopSync();
129 void exitCPULoopAsync();
130
132 [[nodiscard]] bool isR800Active() const { return !z80Active; }
133
135 void setZ80Freq(unsigned freq);
136
137 void setInterface(MSXCPUInterface* interface);
138
141 void setPaused(bool paused);
142
143 void setNextSyncPoint(EmuTime::param time);
144
145 void wait(EmuTime::param time);
146 EmuTime waitCyclesZ80(EmuTime::param time, unsigned cycles);
147 EmuTime waitCyclesR800(EmuTime::param time, unsigned cycles);
148
149 [[nodiscard]] CPURegs& getRegisters();
150
151 [[nodiscard]] auto* getZ80() { return z80.get(); }
152 [[nodiscard]] auto* getR800() { return r800.get(); }
153
154 template<typename Archive>
155 void serialize(Archive& ar, unsigned version);
156
157private:
158 void invalidateMemCacheSlot();
159
160 // only for MSXMotherBoard
161 void execute(bool fastForward);
162 friend class MSXMotherBoard;
163
169 EmuTime::param getCurrentTime() const;
170
171 // Observer<Setting>
172 void update(const Setting& setting) noexcept override;
173
174 template<bool READ, bool WRITE, bool SUB_START>
175 void setRWCache(unsigned start, unsigned size, const byte* rData, byte* wData, int ps, int ss,
176 std::span<const byte, 256> disallowRead, std::span<const byte, 256> disallowWrite);
177
178private:
179 MSXMotherBoard& motherboard;
180 BooleanSetting traceSetting;
181 TclCallback diHaltCallback;
182 const std::unique_ptr<CPUCore<Z80TYPE>> z80;
183 const std::unique_ptr<CPUCore<R800TYPE>> r800; // can be nullptr
184
185 std::array<std::array<const byte*, CacheLine::NUM>, 16> slotReadLines;
186 std::array<std::array< byte*, CacheLine::NUM>, 16> slotWriteLines;
187 std::array<byte, 4> slots; // active slot for page (= 4 * primSlot + secSlot)
188
189 struct TimeInfoTopic final : InfoTopic {
190 explicit TimeInfoTopic(InfoCommand& machineInfoCommand);
191 void execute(std::span<const TclObject> tokens,
192 TclObject& result) const override;
193 [[nodiscard]] std::string help(std::span<const TclObject> tokens) const override;
194 } timeInfo;
195
196 class CPUFreqInfoTopic final : public InfoTopic {
197 public:
198 CPUFreqInfoTopic(InfoCommand& machineInfoCommand,
199 const std::string& name, CPUClock& clock);
200 void execute(std::span<const TclObject> tokens,
201 TclObject& result) const override;
202 [[nodiscard]] std::string help(std::span<const TclObject> tokens) const override;
203 private:
204 CPUClock& clock;
205 };
206 CPUFreqInfoTopic z80FreqInfo; // always present
207 const std::unique_ptr<CPUFreqInfoTopic> r800FreqInfo; // can be nullptr
208
209 struct Debuggable final : SimpleDebuggable {
210 explicit Debuggable(MSXMotherBoard& motherboard);
211 [[nodiscard]] byte read(unsigned address) override;
212 void write(unsigned address, byte value) override;
213 } debuggable;
214
215 EmuTime reference{EmuTime::zero()};
216 bool z80Active{true};
217 bool newZ80Active{true};
218
219 MSXCPUInterface* interface{nullptr}; // only used for debug
220};
222
223} // namespace openmsx
224
225#endif
BaseSetting * setting
void setZ80Freq(unsigned freq)
Switch the Z80 clock freq.
Definition MSXCPU.cc:320
bool isM1Cycle(unsigned address) const
Should only be used from within a MSXDevice::readMem() method.
Definition MSXCPU.cc:314
void lowerNMI()
This methods lowers the non-maskable interrupt again.
Definition MSXCPU.cc:308
void serialize(Archive &ar, unsigned version)
Definition MSXCPU.cc:526
void invalidateAllSlotsRWCache(word start, unsigned size)
Invalidate the CPU its cache for the interval [start, start + size) For example MSXMemoryMapper and M...
Definition MSXCPU.cc:185
void fillWCache(unsigned start, unsigned size, byte *wData, int ps, int ss, std::span< const byte, 256 > disallowRead, std::span< const byte, 256 > disallowWrite)
Definition MSXCPU.cc:286
void updateVisiblePage(byte page, byte primarySlot, byte secondarySlot)
Inform CPU of bank switch.
Definition MSXCPU.cc:164
void fillRCache(unsigned start, unsigned size, const byte *rData, int ps, int ss, std::span< const byte, 256 > disallowRead, std::span< const byte, 256 > disallowWrite)
Definition MSXCPU.cc:280
CPURegs & getRegisters()
Definition MSXCPU.cc:343
bool isR800Active() const
Is the R800 currently active?
Definition MSXCPU.hh:132
auto * getR800()
Definition MSXCPU.hh:152
void fillRWCache(unsigned start, unsigned size, const byte *rData, byte *wData, int ps, int ss, std::span< const byte, 256 > disallowRead, std::span< const byte, 256 > disallowWrite)
Fill the read and write cache lines for a specific slot with the specified value.
Definition MSXCPU.cc:274
void invalidateRCache(unsigned start, unsigned size, int ps, int ss, std::span< const byte, 256 > disallowRead, std::span< const byte, 256 > disallowWrite)
Definition MSXCPU.cc:259
EmuTime waitCyclesR800(EmuTime::param time, unsigned cycles)
Definition MSXCPU.cc:337
void exitCPULoopSync()
See CPUCore::exitCPULoopSync()
Definition MSXCPU.cc:130
void setNextSyncPoint(EmuTime::param time)
Definition MSXCPU.cc:147
EmuTime waitCyclesZ80(EmuTime::param time, unsigned cycles)
Definition MSXCPU.cc:331
void raiseIRQ()
This method raises a maskable interrupt.
Definition MSXCPU.cc:293
void raiseNMI()
This method raises a non-maskable interrupt.
Definition MSXCPU.cc:303
void wait(EmuTime::param time)
Definition MSXCPU.cc:325
void doReset(EmuTime::param time)
Reset CPU.
Definition MSXCPU.cc:84
void setActiveCPU(Type cpu)
Switch between Z80/R800.
Definition MSXCPU.cc:94
auto * getZ80()
Definition MSXCPU.hh:151
void invalidateRWCache(unsigned start, unsigned size, int ps, int ss, std::span< const byte, 256 > disallowRead, std::span< const byte, 256 > disallowWrite)
Similar to the method above, but only invalidates one specific slot.
Definition MSXCPU.cc:251
void setPaused(bool paused)
(un)pause CPU.
Definition MSXCPU.cc:359
void setInterface(MSXCPUInterface *interface)
Definition MSXCPU.cc:77
void exitCPULoopAsync()
See CPUCore::exitCPULoopAsync()
Definition MSXCPU.cc:135
friend class MSXMotherBoard
Definition MSXCPU.hh:162
void setDRAMmode(bool dram)
Sets DRAM or ROM mode (influences memory access speed for R800).
Definition MSXCPU.cc:105
void lowerIRQ()
This methods lowers the maskable interrupt again.
Definition MSXCPU.cc:298
void invalidateWCache(unsigned start, unsigned size, int ps, int ss, std::span< const byte, 256 > disallowRead, std::span< const byte, 256 > disallowWrite)
Definition MSXCPU.cc:266
Generic Gang-of-Four Observer class, templatized edition.
Definition Observer.hh:10
This file implemented 3 utility functions:
Definition Autofire.cc:11
uint16_t word
16 bit unsigned integer
Definition openmsx.hh:29
#define SERIALIZE_CLASS_VERSION(CLASS, VERSION)