openMSX
CPUCore.cc
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1 // MEMORY EMULATION
2 // ----------------
3 //
4 // Memory access emulation is a very important part of the CPU emulation.
5 // Because they happen so frequently they really need to be executed as fast as
6 // possible otherwise they will completely bring down the speed of the CPU
7 // emulation.
8 //
9 // A very fast way to emulate memory accesses is by simply reading/writing to a
10 // 64kb array (for a 16-bit address space). Unfortunately this doesn't allow
11 // for memory mapped IO (MMIO). These are memory regions where read/writes
12 // trigger side effects, so where we need to execute device-specific code on
13 // read or writes. An alternative that does work with MMIO is for every access
14 // execute a virtual method call, (this is the approach taken by most current
15 // MSX emulators). Unfortunately this is also a lot slower.
16 //
17 // It is possible to combine the speed of array accesses with the flexibility
18 // of virtual methods. In openMSX it's implemened as follows: the 64kb address
19 // space is divided in 256 regions of 256 bytes (called cacheLines in the code
20 // below). For each such region we store a pointer, if this pointer is nullptr
21 // then we have to use the slow way (=virtual method call). If it is not nullptr,
22 // the pointer points to a block of memory that can be directly accessed. In
23 // some contexts accesses via the pointer are known as backdoor accesses while
24 // the accesses directly to the device are known as frontdoor accesses.
25 //
26 // We keep different pointers for read and write accesses. This allows to also
27 // implement ROMs efficiently: read is handled as regular RAM, but writes end
28 // up in some dummy memory region. This region is called 'unmappedWrite' in the
29 // code. There is also a special region 'unmappedRead', this region is filled
30 // with 0xFF and can be used to model (parts of) a device that don't react to
31 // reads (so reads return 0xFF).
32 //
33 // Because of bankswitching (the MSX slot select mechanism, but also e.g.
34 // MegaROM backswitching) the memory map as seen by the Z80 is not static. This
35 // means that the cacheLine pointers also need to change during runtime. To
36 // solve this we made the bankswitch code also responsible for invalidating the
37 // cacheLines of the switched region. These pointers are filled-in again in a
38 // lazy way: the first read or write to a cache line will first get this
39 // pointer (see getReadCacheLine() and getWriteCacheLine() in the code below),
40 // from then on this pointer is used for all further accesses to this region,
41 // until the cache is invalidated again.
42 //
43 //
44 // INSTRUCTION EMULATION
45 // ---------------------
46 //
47 // UPDATE: the 'threaded interpreter model' is not enabled by default
48 // main reason is the huge memory requirement while compiling
49 // and that it doesn't work on non-gcc compilers
50 //
51 // The current implementation is based on a 'threaded interpreter model'. In
52 // the text below I'll call the older implementation the 'traditional
53 // interpreter model'. From a very high level these two models look like this:
54 //
55 // Traditional model:
56 // while (!needExit()) {
57 // byte opcode = fetch(PC++);
58 // switch (opcode) {
59 // case 0x00: nop(); break;
60 // case 0x01: ld_bc_nn(); break;
61 // ...
62 // }
63 // }
64 //
65 // Threaded model:
66 // byte opcode = fetch(PC++); //
67 // goto *(table[opcode]); // fetch-and-dispatch
68 // // note: the goto * syntax is a gcc extension called computed-gotos
69 //
70 // op00: nop(); if (!needExit()) [fetch-and-dispatch];
71 // op01: ld_bc_nn(); if (!needExit()) [fetch-and-dispatch];
72 // ...
73 //
74 // In the first model there is a central place in the code that fetches (the
75 // first byte of) the instruction and based on this byte jumps to the
76 // appropriate routine. In the second model, this fetch-and-dispatch logic is
77 // duplicated at the end of each instruction.
78 //
79 // Typically the 'dispatch' part in above paragraph is implemented (either by
80 // the compiler or manually using computed goto's) via a jump table. Thus on
81 // assembler level via an indirect jump. For the host CPU it's hard to predict
82 // the destination address of such an indirect jump, certainly if there's only
83 // one such jump for all dispatching (the traditional model). If each
84 // instruction has its own indirect jump instruction (the threaded model), it
85 // becomes a bit easier, because often one particular z80 instructions is
86 // followed by a specific other z80 instruction (or one from a small subset).
87 // For example a z80 'cp' instruction is most likely followed by a 'conditional
88 // jump' z80 instruction. Modern CPUs are quite sensitive to
89 // branch-(mis)predictions, so the above optimization helps quite a lot. I
90 // measured a speedup of more than 10%!
91 //
92 // There is another advantage to the threaded model. Because also the
93 // needExit() test is duplicated for each instruction, it becomes possible to
94 // tweak it for individual instructions. But first let me explain this
95 // exit-test in more detail.
96 //
97 // These are the main reasons why the emulator should stop emulating CPU
98 // instructions:
99 // 1) When other devices than the CPU must be emulated (e.g. video frame
100 // rendering). In openMSX this is handled by the Scheduler class and
101 // actually we don't exit the CPU loop (anymore) for this. Instead we
102 // simply execute the device code as a subroutine. Each time right before
103 // we access an IO port or do a frontdoor memory access, there is a check
104 // whether we should emulate device code (search for schedule() in the code
105 // below).
106 // 2) To keep the inner CPU loop as fast as possible we don't check for IRQ,
107 // NMI or HALT status in this loop. Instead this condition is checked only
108 // once at the beginning outside of the loop (if there wasn't a pending IRQ
109 // on the first instruction there also won't be one on the second
110 // instruction, if all we did was emulating cpu instructions). Now when one
111 // of these conditions changes, we must exit the inner loop and re-evaluate
112 // them. For example after an EI instruction we must check the IRQ status
113 // again.
114 // 3) Various reasons like:
115 // * Z80/R800 switch
116 // * executing a Tcl command (could be a cpu-register debug read)
117 // * exit the emulator
118 // 4) 'once-in-a-while': To avoid threading problems and race conditions,
119 // several threads in openMSX only 'schedule' work that will later be
120 // executed by the main emulation thread. The main thread checks for such
121 // task outside of the cpu emulation loop. So once-in-a-while we need to
122 // exit the loop. The exact timing doesn't matter here because anyway the
123 // relative timing between threads is undefined.
124 // So for 1) we don't need to do anything (we don't actually exit). For 2) and
125 // 3) we need the exit the loop as soon as possible (right after the current
126 // instruction is finished). For 4) it's OK to exit 'eventually' (a few hundred
127 // z80 instructions late is still OK).
128 //
129 // Condition 2) is implemented with the 'slowInstructions' mechanism. Condition
130 // 3) via exitCPULoopSync() (may only get called by the main emulation thread)
131 // and condition 4) is implemented via exitCPULoopAsync() (can be called from
132 // any thread).
133 //
134 // Now back to the exit-test optimization: in the threaded model each
135 // instruction ends with:
136 //
137 // if (needExit()) return
138 // byte opcode = fetch(PC++);
139 // goto *(table[opcode]);
140 //
141 // And if we look in more detail at fetch():
142 //
143 // if (canDoBackdoor(addr)) {
144 // doBackdoorAccess(addr);
145 // } else {
146 // doFrontdoorAccess(addr);
147 // }
148 //
149 // So there are in fact two checks per instruction. This can be reduced to only
150 // one check with the following trick:
151 //
152 // !!!WRONG!!!
153 // In the past we optimized this to only check canDoBackdoor() (and make sure
154 // canDoBackdoor() returned false when needExit() would return true). This
155 // worked rather well, except for one case: when we exit the CPU loop we also
156 // check for pending Syncronization points. It is possible such a SyncPoint
157 // raises the IRQ line. So it is important to check for exit after every
158 // instruction, otherwise we would enter the IRQ routine a couple of
159 // instructions too late.
160 
161 #include "CPUCore.hh"
162 #include "MSXCPUInterface.hh"
163 #include "Scheduler.hh"
164 #include "MSXMotherBoard.hh"
165 #include "CliComm.hh"
166 #include "TclCallback.hh"
167 #include "Dasm.hh"
168 #include "Z80.hh"
169 #include "R800.hh"
170 #include "Thread.hh"
171 #include "endian.hh"
172 #include "likely.hh"
173 #include "inline.hh"
174 #include "unreachable.hh"
175 #include <iomanip>
176 #include <iostream>
177 #include <type_traits>
178 #include <cassert>
179 #include <cstring>
180 
181 
182 //
183 // #define USE_COMPUTED_GOTO
184 //
185 // Computed goto's are not enabled by default:
186 // - Computed goto's are a gcc extension, it's not part of the official c++
187 // standard. So this will only work if you use gcc as your compiler (it
188 // won't work with visual c++ for example)
189 // - This is only beneficial on CPUs with branch prediction for indirect jumps
190 // and a reasonable amout of cache. For example it is very benefical for a
191 // intel core2 cpu (10% faster), but not for a ARM920 (a few percent slower)
192 // - Compiling src/cpu/CPUCore.cc with computed goto's enabled is very demanding
193 // on the compiler. On older gcc versions it requires up to 1.5GB of memory.
194 // But even on more recent gcc versions it still requires around 700MB.
195 //
196 // Probably the easiest way to enable this, is to pass the -DUSE_COMPUTED_GOTO
197 // flag to the compiler. This is for example done in the super-opt flavour.
198 // See build/flavour-super-opt.mk
199 
200 
201 using std::string;
202 
203 namespace openmsx {
204 
205 // This actually belongs in Z80.cc and R800.cc (these files don't exist yet).
206 // As a quick hack I put these two lines here because I found it overkill to
207 // create two files each containing only a single line.
208 // Technically these two lines _are_ required according to the c++ standard.
209 // Though usually it works just find without them, but during experiments I did
210 // get a link error when these lines were missing (it only happened during a
211 // debug build with some specific compiler version and only with some
212 // combination of other code changes, but again when strictly following the
213 // language rules, these lines should be here).
214 // ... But visual studio is not fully standard compliant, see also comment
215 // in SectorAccesibleDisk.cc
216 #ifndef _MSC_VER
217 const int Z80TYPE ::CLOCK_FREQ;
218 const int R800TYPE::CLOCK_FREQ;
219 #endif
220 
221 enum Reg8 : int { A, F, B, C, D, E, H, L, IXH, IXL, IYH, IYL, REG_I, REG_R, DUMMY };
222 enum Reg16 : int { AF, BC, DE, HL, IX, IY, SP };
223 
224 // flag positions
225 static const byte S_FLAG = 0x80;
226 static const byte Z_FLAG = 0x40;
227 static const byte Y_FLAG = 0x20;
228 static const byte H_FLAG = 0x10;
229 static const byte X_FLAG = 0x08;
230 static const byte V_FLAG = 0x04;
231 static const byte P_FLAG = V_FLAG;
232 static const byte N_FLAG = 0x02;
233 static const byte C_FLAG = 0x01;
234 
235 // flag-register lookup tables
236 struct Table {
237  byte ZS [256];
238  byte ZSXY [256];
239  byte ZSP [256];
240  byte ZSPXY[256];
241  byte ZSPH [256];
242 };
243 
244 static const byte ZS0 = Z_FLAG;
245 static const byte ZSXY0 = Z_FLAG;
246 static const byte ZSP0 = Z_FLAG | V_FLAG;
247 static const byte ZSPXY0 = Z_FLAG | V_FLAG;
248 static const byte ZS255 = S_FLAG;
249 static const byte ZSXY255 = S_FLAG | X_FLAG | Y_FLAG;
250 
251 static constexpr Table initTables()
252 {
253  Table table = {};
254 
255  for (int i = 0; i < 256; ++i) {
256  byte zFlag = (i == 0) ? Z_FLAG : 0;
257  byte sFlag = i & S_FLAG;
258  byte xFlag = i & X_FLAG;
259  byte yFlag = i & Y_FLAG;
260  byte vFlag = V_FLAG;
261  for (int v = 128; v != 0; v >>= 1) {
262  if (i & v) vFlag ^= V_FLAG;
263  }
264  table.ZS [i] = zFlag | sFlag;
265  table.ZSXY [i] = zFlag | sFlag | xFlag | yFlag;
266  table.ZSP [i] = zFlag | sFlag | vFlag;
267  table.ZSPXY[i] = zFlag | sFlag | xFlag | yFlag | vFlag;
268  table.ZSPH [i] = zFlag | sFlag | vFlag | H_FLAG;
269  }
270  assert(table.ZS [ 0] == ZS0);
271  assert(table.ZSXY [ 0] == ZSXY0);
272  assert(table.ZSP [ 0] == ZSP0);
273  assert(table.ZSPXY[ 0] == ZSPXY0);
274  assert(table.ZS [255] == ZS255);
275  assert(table.ZSXY [255] == ZSXY255);
276 
277  return table;
278 }
279 
280 static constexpr Table table = initTables();
281 
282 // Global variable, because it should be shared between Z80 and R800.
283 // It must not be shared between the CPUs of different MSX machines, but
284 // the (logical) lifetime of this variable cannot overlap between execution
285 // of two MSX machines.
286 static word start_pc;
287 
288 // conditions
289 struct CondC { bool operator()(byte f) const { return (f & C_FLAG) != 0; } };
290 struct CondNC { bool operator()(byte f) const { return !(f & C_FLAG); } };
291 struct CondZ { bool operator()(byte f) const { return (f & Z_FLAG) != 0; } };
292 struct CondNZ { bool operator()(byte f) const { return !(f & Z_FLAG); } };
293 struct CondM { bool operator()(byte f) const { return (f & S_FLAG) != 0; } };
294 struct CondP { bool operator()(byte f) const { return !(f & S_FLAG); } };
295 struct CondPE { bool operator()(byte f) const { return (f & V_FLAG) != 0; } };
296 struct CondPO { bool operator()(byte f) const { return !(f & V_FLAG); } };
297 struct CondTrue { bool operator()(byte /*f*/) const { return true; } };
298 
299 template<class T> CPUCore<T>::CPUCore(
300  MSXMotherBoard& motherboard_, const string& name,
301  const BooleanSetting& traceSetting_,
302  TclCallback& diHaltCallback_, EmuTime::param time)
303  : CPURegs(T::isR800())
304  , T(time, motherboard_.getScheduler())
305  , motherboard(motherboard_)
306  , scheduler(motherboard.getScheduler())
307  , interface(nullptr)
308  , traceSetting(traceSetting_)
309  , diHaltCallback(diHaltCallback_)
310  , IRQStatus(motherboard.getDebugger(), name + ".pendingIRQ",
311  "Non-zero if there are pending IRQs (thus CPU would enter "
312  "interrupt routine in EI mode).",
313  0)
314  , IRQAccept(motherboard.getDebugger(), name + ".acceptIRQ",
315  "This probe is only useful to set a breakpoint on (the value "
316  "return by read is meaningless). The breakpoint gets triggered "
317  "right after the CPU accepted an IRQ.")
318  , freqLocked(
319  motherboard.getCommandController(), name + "_freq_locked",
320  strCat("real (locked) or custom (unlocked) ", name, " frequency"),
321  true)
322  , freqValue(
323  motherboard.getCommandController(), name + "_freq",
324  strCat("custom ", name, " frequency (only valid when unlocked)"),
325  T::CLOCK_FREQ, 1000000, 1000000000)
326  , freq(T::CLOCK_FREQ)
327  , NMIStatus(0)
328  , nmiEdge(false)
329  , exitLoop(false)
330  , tracingEnabled(traceSetting.getBoolean())
331  , isTurboR(motherboard.isTurboR())
332 {
333  static_assert(!std::is_polymorphic<CPUCore<T>>::value,
334  "keep CPUCore non-virtual to keep PC at offset 0");
335  doSetFreq();
336  doReset(time);
337 }
338 
339 template<class T> void CPUCore<T>::warp(EmuTime::param time)
340 {
341  assert(T::getTimeFast() <= time);
342  T::setTime(time);
343 }
344 
345 template<class T> EmuTime::param CPUCore<T>::getCurrentTime() const
346 {
347  return T::getTime();
348 }
349 
350 template<class T> void CPUCore<T>::invalidateMemCache(unsigned start, unsigned size)
351 {
352  unsigned first = start / CacheLine::SIZE;
353  unsigned num = (size + CacheLine::SIZE - 1) / CacheLine::SIZE;
354  memset(&readCacheLine [first], 0, num * sizeof(byte*)); // nullptr
355  memset(&writeCacheLine [first], 0, num * sizeof(byte*)); //
356  memset(&readCacheTried [first], 0, num * sizeof(bool)); // FALSE
357  memset(&writeCacheTried[first], 0, num * sizeof(bool)); //
358 }
359 
360 template<class T> void CPUCore<T>::doReset(EmuTime::param time)
361 {
362  // AF and SP are 0xFFFF
363  // PC, R, IFF1, IFF2, HALT and IM are 0x0
364  // all others are random
365  setAF(0xFFFF);
366  setBC(0xFFFF);
367  setDE(0xFFFF);
368  setHL(0xFFFF);
369  setIX(0xFFFF);
370  setIY(0xFFFF);
371  setPC(0x0000);
372  setSP(0xFFFF);
373  setAF2(0xFFFF);
374  setBC2(0xFFFF);
375  setDE2(0xFFFF);
376  setHL2(0xFFFF);
377  setIFF1(false);
378  setIFF2(false);
379  setHALT(false);
380  setExtHALT(false);
381  setIM(0);
382  setI(0x00);
383  setR(0x00);
384  T::setMemPtr(0xFFFF);
385  clearPrevious();
386  invalidateMemCache(0x0000, 0x10000);
387 
388  // We expect this assert to be valid
389  // assert(T::getTimeFast() <= time); // time shouldn't go backwards
390  // But it's disabled for the following reason:
391  // 'motion' (IRC nickname) managed to create a replay file that
392  // contains a reset command that falls in the middle of a Z80
393  // instruction. Replayed commands go via the Scheduler, and are
394  // (typically) executed right after a complete CPU instruction. So
395  // the CPU is (slightly) ahead in time of the about to be executed
396  // reset command.
397  // Normally this situation should never occur: console commands,
398  // hotkeys, commands over clicomm, ... are all handled via the global
399  // event mechanism. Such global events are scheduled between CPU
400  // instructions, so also in a replay they should fall between CPU
401  // instructions.
402  // However if for some reason the timing of the emulation changed
403  // (improved emulation accuracy or a bug so that emulation isn't
404  // deterministic or the replay file was edited, ...), then the above
405  // reasoning no longer holds and the assert can trigger.
406  // We need to be robust against loading older replays (when emulation
407  // timing has changed). So in that respect disabling the assert is
408  // good. Though in the example above (motion's replay) it's not clear
409  // whether the assert is really triggered by mixing an old replay
410  // with a newer openMSX version. In any case so far we haven't been
411  // able to reproduce this assert by recording and replaying using a
412  // single openMSX version.
413  T::setTime(time);
414 
415  assert(NMIStatus == 0); // other devices must reset their NMI source
416  assert(IRQStatus == 0); // other devices must reset their IRQ source
417 }
418 
419 // I believe the following two methods are thread safe even without any
420 // locking. The worst that can happen is that we occasionally needlessly
421 // exit the CPU loop, but that's harmless
422 // TODO thread issues are always tricky, can someone confirm this really
423 // is thread safe
424 template<class T> void CPUCore<T>::exitCPULoopAsync()
425 {
426  // can get called from non-main threads
427  exitLoop = true;
428 }
429 template<class T> void CPUCore<T>::exitCPULoopSync()
430 {
431  assert(Thread::isMainThread());
432  exitLoop = true;
433  T::disableLimit();
434 }
435 template<class T> inline bool CPUCore<T>::needExitCPULoop()
436 {
437  // always executed in main thread
438  if (unlikely(exitLoop)) {
439  // Note: The test-and-set is _not_ atomic! But that's fine.
440  // An atomic implementation is trivial (see below), but
441  // this version (at least on x86) avoids the more expensive
442  // instructions on the likely path.
443  exitLoop = false;
444  return true;
445  }
446  return false;
447 
448  // Alternative implementation:
449  // atomically set to false and return the old value
450  //return exitLoop.exchange(false);
451 }
452 
453 template<class T> void CPUCore<T>::setSlowInstructions()
454 {
455  slowInstructions = 2;
456  T::disableLimit();
457 }
458 
459 template<class T> void CPUCore<T>::raiseIRQ()
460 {
461  assert(IRQStatus >= 0);
462  if (IRQStatus == 0) {
463  setSlowInstructions();
464  }
465  IRQStatus = IRQStatus + 1;
466 }
467 
468 template<class T> void CPUCore<T>::lowerIRQ()
469 {
470  IRQStatus = IRQStatus - 1;
471  assert(IRQStatus >= 0);
472 }
473 
474 template<class T> void CPUCore<T>::raiseNMI()
475 {
476  assert(NMIStatus >= 0);
477  if (NMIStatus == 0) {
478  nmiEdge = true;
479  setSlowInstructions();
480  }
481  NMIStatus++;
482 }
483 
484 template<class T> void CPUCore<T>::lowerNMI()
485 {
486  NMIStatus--;
487  assert(NMIStatus >= 0);
488 }
489 
490 template<class T> bool CPUCore<T>::isM1Cycle(unsigned address) const
491 {
492  // This method should only be called from within a MSXDevice::readMem()
493  // method. It can be used to check whether the current read action has
494  // the M1 pin active. The 'address' parameter that is give to readMem()
495  // should be passed (unchanged) to this method.
496  //
497  // This simple implementation works because the rest of the CPUCore
498  // code is careful to only update the PC register on M1 cycles. In
499  // practice that means that the PC is (only) updated at the very end of
500  // every instruction, even if is a multi-byte instruction. Or for
501  // prefix-instructions the PC is also updated after the prefix is
502  // fetched (because such instructions activate M1 twice).
503  return address == getPC();
504 }
505 
506 template<class T> void CPUCore<T>::wait(EmuTime::param time)
507 {
508  assert(time >= getCurrentTime());
509  scheduler.schedule(time);
510  T::advanceTime(time);
511 }
512 
513 template<class T> EmuTime CPUCore<T>::waitCycles(EmuTime::param time, unsigned cycles)
514 {
515  T::add(cycles);
516  EmuTime time2 = T::calcTime(time, cycles);
517  // note: time2 is not necessarily equal to T::getTime() because of the
518  // way how WRITE_PORT() is implemented.
519  scheduler.schedule(time2);
520  return time2;
521 }
522 
523 template<class T> void CPUCore<T>::setNextSyncPoint(EmuTime::param time)
524 {
525  T::setLimit(time);
526 }
527 
528 
529 static inline char toHex(byte x)
530 {
531  return (x < 10) ? (x + '0') : (x - 10 + 'A');
532 }
533 static void toHex(byte x, char* buf)
534 {
535  buf[0] = toHex(x / 16);
536  buf[1] = toHex(x & 15);
537 }
538 
539 template<class T> void CPUCore<T>::disasmCommand(
540  Interpreter& interp, span<const TclObject> tokens, TclObject& result) const
541 {
542  word address = (tokens.size() < 3) ? getPC() : tokens[2].getInt(interp);
543  byte outBuf[4];
544  std::string dasmOutput;
545  unsigned len = dasm(*interface, address, outBuf, dasmOutput,
546  T::getTimeFast());
547  result.addListElement(dasmOutput);
548  char tmp[3]; tmp[2] = 0;
549  for (unsigned i = 0; i < len; ++i) {
550  toHex(outBuf[i], tmp);
551  result.addListElement(tmp);
552  }
553 }
554 
555 template<class T> void CPUCore<T>::update(const Setting& setting)
556 {
557  if (&setting == &freqLocked) {
558  doSetFreq();
559  } else if (&setting == &freqValue) {
560  doSetFreq();
561  } else if (&setting == &traceSetting) {
562  tracingEnabled = traceSetting.getBoolean();
563  }
564 }
565 
566 template<class T> void CPUCore<T>::setFreq(unsigned freq_)
567 {
568  freq = freq_;
569  doSetFreq();
570 }
571 
572 template<class T> void CPUCore<T>::doSetFreq()
573 {
574  if (freqLocked.getBoolean()) {
575  // locked, use value set via setFreq()
576  T::setFreq(freq);
577  } else {
578  // unlocked, use value set by user
579  T::setFreq(freqValue.getInt());
580  }
581 }
582 
583 
584 template<class T> inline byte CPUCore<T>::READ_PORT(unsigned port, unsigned cc)
585 {
586  EmuTime time = T::getTimeFast(cc);
587  scheduler.schedule(time);
588  byte result = interface->readIO(port, time);
589  // note: no forced page-break after IO
590  return result;
591 }
592 
593 template<class T> inline void CPUCore<T>::WRITE_PORT(unsigned port, byte value, unsigned cc)
594 {
595  EmuTime time = T::getTimeFast(cc);
596  scheduler.schedule(time);
597  interface->writeIO(port, value, time);
598  // note: no forced page-break after IO
599 }
600 
601 template<class T> template<bool PRE_PB, bool POST_PB>
602 NEVER_INLINE byte CPUCore<T>::RDMEMslow(unsigned address, unsigned cc)
603 {
604  // not cached
605  unsigned high = address >> CacheLine::BITS;
606  if (!readCacheTried[high]) {
607  // try to cache now
608  unsigned addrBase = address & CacheLine::HIGH;
609  if (const byte* line = interface->getReadCacheLine(addrBase)) {
610  // cached ok
611  T::template PRE_MEM<PRE_PB, POST_PB>(address);
612  T::template POST_MEM< POST_PB>(address);
613  readCacheLine[high] = line - addrBase;
614  return readCacheLine[high][address];
615  }
616  }
617  // uncacheable
618  readCacheTried[high] = true;
619  T::template PRE_MEM<PRE_PB, POST_PB>(address);
620  EmuTime time = T::getTimeFast(cc);
621  scheduler.schedule(time);
622  byte result = interface->readMem(address, time);
623  T::template POST_MEM<POST_PB>(address);
624  return result;
625 }
626 template<class T> template<bool PRE_PB, bool POST_PB>
627 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl2(unsigned address, unsigned cc)
628 {
629  const byte* line = readCacheLine[address >> CacheLine::BITS];
630  if (likely(line != nullptr)) {
631  // cached, fast path
632  T::template PRE_MEM<PRE_PB, POST_PB>(address);
633  T::template POST_MEM< POST_PB>(address);
634  return line[address];
635  } else {
636  return RDMEMslow<PRE_PB, POST_PB>(address, cc); // not inlined
637  }
638 }
639 template<class T> template<bool PRE_PB, bool POST_PB>
640 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl(unsigned address, unsigned cc)
641 {
642  static const bool PRE = T::template Normalize<PRE_PB >::value;
643  static const bool POST = T::template Normalize<POST_PB>::value;
644  return RDMEM_impl2<PRE, POST>(address, cc);
645 }
646 template<class T> template<unsigned PC_OFFSET> ALWAYS_INLINE byte CPUCore<T>::RDMEM_OPCODE(unsigned cc)
647 {
648  // Real Z80 would update the PC register now. In this implementation
649  // we've chosen to instead update PC only once at the end of the
650  // instruction. (Of course we made sure this difference is not
651  // noticeable by the program).
652  //
653  // See the comments in isM1Cycle() for the motivation for this
654  // deviation. Apart from that functional aspect it also turns out to be
655  // faster to only update PC once per instruction instead of after each
656  // fetch.
657  unsigned address = (getPC() + PC_OFFSET) & 0xFFFF;
658  return RDMEM_impl<false, false>(address, cc);
659 }
660 template<class T> ALWAYS_INLINE byte CPUCore<T>::RDMEM(unsigned address, unsigned cc)
661 {
662  return RDMEM_impl<true, true>(address, cc);
663 }
664 
665 template<class T> template<bool PRE_PB, bool POST_PB>
666 NEVER_INLINE unsigned CPUCore<T>::RD_WORD_slow(unsigned address, unsigned cc)
667 {
668  unsigned res = RDMEM_impl<PRE_PB, false>(address, cc);
669  res += RDMEM_impl<false, POST_PB>((address + 1) & 0xFFFF, cc + T::CC_RDMEM) << 8;
670  return res;
671 }
672 template<class T> template<bool PRE_PB, bool POST_PB>
673 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl2(unsigned address, unsigned cc)
674 {
675  const byte* line = readCacheLine[address >> CacheLine::BITS];
676  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
677  // fast path: cached and two bytes in same cache line
678  T::template PRE_WORD<PRE_PB, POST_PB>(address);
679  T::template POST_WORD< POST_PB>(address);
680  return Endian::read_UA_L16(&line[address]);
681  } else {
682  // slow path, not inline
683  return RD_WORD_slow<PRE_PB, POST_PB>(address, cc);
684  }
685 }
686 template<class T> template<bool PRE_PB, bool POST_PB>
687 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl(unsigned address, unsigned cc)
688 {
689  static const bool PRE = T::template Normalize<PRE_PB >::value;
690  static const bool POST = T::template Normalize<POST_PB>::value;
691  return RD_WORD_impl2<PRE, POST>(address, cc);
692 }
693 template<class T> template<unsigned PC_OFFSET> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_PC(unsigned cc)
694 {
695  unsigned addr = (getPC() + PC_OFFSET) & 0xFFFF;
696  return RD_WORD_impl<false, false>(addr, cc);
697 }
698 template<class T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD(
699  unsigned address, unsigned cc)
700 {
701  return RD_WORD_impl<true, true>(address, cc);
702 }
703 
704 template<class T> template<bool PRE_PB, bool POST_PB>
705 NEVER_INLINE void CPUCore<T>::WRMEMslow(unsigned address, byte value, unsigned cc)
706 {
707  // not cached
708  unsigned high = address >> CacheLine::BITS;
709  if (!writeCacheTried[high]) {
710  // try to cache now
711  unsigned addrBase = address & CacheLine::HIGH;
712  if (byte* line = interface->getWriteCacheLine(addrBase)) {
713  // cached ok
714  T::template PRE_MEM<PRE_PB, POST_PB>(address);
715  T::template POST_MEM< POST_PB>(address);
716  writeCacheLine[high] = line - addrBase;
717  writeCacheLine[high][address] = value;
718  return;
719  }
720  }
721  // uncacheable
722  writeCacheTried[high] = true;
723  T::template PRE_MEM<PRE_PB, POST_PB>(address);
724  EmuTime time = T::getTimeFast(cc);
725  scheduler.schedule(time);
726  interface->writeMem(address, value, time);
727  T::template POST_MEM<POST_PB>(address);
728 }
729 template<class T> template<bool PRE_PB, bool POST_PB>
731  unsigned address, byte value, unsigned cc)
732 {
733  byte* line = writeCacheLine[address >> CacheLine::BITS];
734  if (likely(line != nullptr)) {
735  // cached, fast path
736  T::template PRE_MEM<PRE_PB, POST_PB>(address);
737  T::template POST_MEM< POST_PB>(address);
738  line[address] = value;
739  } else {
740  WRMEMslow<PRE_PB, POST_PB>(address, value, cc); // not inlined
741  }
742 }
743 template<class T> template<bool PRE_PB, bool POST_PB>
745  unsigned address, byte value, unsigned cc)
746 {
747  static const bool PRE = T::template Normalize<PRE_PB >::value;
748  static const bool POST = T::template Normalize<POST_PB>::value;
749  WRMEM_impl2<PRE, POST>(address, value, cc);
750 }
751 template<class T> ALWAYS_INLINE void CPUCore<T>::WRMEM(
752  unsigned address, byte value, unsigned cc)
753 {
754  WRMEM_impl<true, true>(address, value, cc);
755 }
756 
757 template<class T> NEVER_INLINE void CPUCore<T>::WR_WORD_slow(
758  unsigned address, unsigned value, unsigned cc)
759 {
760  WRMEM_impl<true, false>( address, value & 255, cc);
761  WRMEM_impl<false, true>((address + 1) & 0xFFFF, value >> 8, cc + T::CC_WRMEM);
762 }
763 template<class T> ALWAYS_INLINE void CPUCore<T>::WR_WORD(
764  unsigned address, unsigned value, unsigned cc)
765 {
766  byte* line = writeCacheLine[address >> CacheLine::BITS];
767  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
768  // fast path: cached and two bytes in same cache line
769  T::template PRE_WORD<true, true>(address);
770  T::template POST_WORD< true>(address);
771  Endian::write_UA_L16(&line[address], value);
772  } else {
773  // slow path, not inline
774  WR_WORD_slow(address, value, cc);
775  }
776 }
777 
778 // same as WR_WORD, but writes high byte first
779 template<class T> template<bool PRE_PB, bool POST_PB>
781  unsigned address, unsigned value, unsigned cc)
782 {
783  WRMEM_impl<PRE_PB, false>((address + 1) & 0xFFFF, value >> 8, cc);
784  WRMEM_impl<false, POST_PB>( address, value & 255, cc + T::CC_WRMEM);
785 }
786 template<class T> template<bool PRE_PB, bool POST_PB>
788  unsigned address, unsigned value, unsigned cc)
789 {
790  byte* line = writeCacheLine[address >> CacheLine::BITS];
791  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
792  // fast path: cached and two bytes in same cache line
793  T::template PRE_WORD<PRE_PB, POST_PB>(address);
794  T::template POST_WORD< POST_PB>(address);
795  Endian::write_UA_L16(&line[address], value);
796  } else {
797  // slow path, not inline
798  WR_WORD_rev_slow<PRE_PB, POST_PB>(address, value, cc);
799  }
800 }
801 template<class T> template<bool PRE_PB, bool POST_PB>
803  unsigned address, unsigned value, unsigned cc)
804 {
805  static const bool PRE = T::template Normalize<PRE_PB >::value;
806  static const bool POST = T::template Normalize<POST_PB>::value;
807  WR_WORD_rev2<PRE, POST>(address, value, cc);
808 }
809 
810 
811 // NMI interrupt
812 template<class T> inline void CPUCore<T>::nmi()
813 {
814  incR(1);
815  setHALT(false);
816  setIFF1(false);
817  PUSH<T::EE_NMI_1>(getPC());
818  setPC(0x0066);
819  T::add(T::CC_NMI);
820 }
821 
822 // IM0 interrupt
823 template<class T> inline void CPUCore<T>::irq0()
824 {
825  // TODO current implementation only works for 1-byte instructions
826  // ok for MSX
827  assert(interface->readIRQVector() == 0xFF);
828  incR(1);
829  setHALT(false);
830  setIFF1(false);
831  setIFF2(false);
832  PUSH<T::EE_IRQ0_1>(getPC());
833  setPC(0x0038);
834  T::setMemPtr(getPC());
835  T::add(T::CC_IRQ0);
836 }
837 
838 // IM1 interrupt
839 template<class T> inline void CPUCore<T>::irq1()
840 {
841  incR(1);
842  setHALT(false);
843  setIFF1(false);
844  setIFF2(false);
845  PUSH<T::EE_IRQ1_1>(getPC());
846  setPC(0x0038);
847  T::setMemPtr(getPC());
848  T::add(T::CC_IRQ1);
849 }
850 
851 // IM2 interrupt
852 template<class T> inline void CPUCore<T>::irq2()
853 {
854  incR(1);
855  setHALT(false);
856  setIFF1(false);
857  setIFF2(false);
858  PUSH<T::EE_IRQ2_1>(getPC());
859  unsigned x = interface->readIRQVector() | (getI() << 8);
860  setPC(RD_WORD(x, T::CC_IRQ2_2));
861  T::setMemPtr(getPC());
862  T::add(T::CC_IRQ2);
863 }
864 
865 template<class T>
867 {
868  checkNoCurrentFlags();
869 #ifdef USE_COMPUTED_GOTO
870  // Addresses of all main-opcode routines,
871  // Note that 40/49/53/5B/64/6D/7F is replaced by 00 (ld r,r == nop)
872  static void* opcodeTable[256] = {
873  &&op00, &&op01, &&op02, &&op03, &&op04, &&op05, &&op06, &&op07,
874  &&op08, &&op09, &&op0A, &&op0B, &&op0C, &&op0D, &&op0E, &&op0F,
875  &&op10, &&op11, &&op12, &&op13, &&op14, &&op15, &&op16, &&op17,
876  &&op18, &&op19, &&op1A, &&op1B, &&op1C, &&op1D, &&op1E, &&op1F,
877  &&op20, &&op21, &&op22, &&op23, &&op24, &&op25, &&op26, &&op27,
878  &&op28, &&op29, &&op2A, &&op2B, &&op2C, &&op2D, &&op2E, &&op2F,
879  &&op30, &&op31, &&op32, &&op33, &&op34, &&op35, &&op36, &&op37,
880  &&op38, &&op39, &&op3A, &&op3B, &&op3C, &&op3D, &&op3E, &&op3F,
881  &&op00, &&op41, &&op42, &&op43, &&op44, &&op45, &&op46, &&op47,
882  &&op48, &&op00, &&op4A, &&op4B, &&op4C, &&op4D, &&op4E, &&op4F,
883  &&op50, &&op51, &&op00, &&op53, &&op54, &&op55, &&op56, &&op57,
884  &&op58, &&op59, &&op5A, &&op00, &&op5C, &&op5D, &&op5E, &&op5F,
885  &&op60, &&op61, &&op62, &&op63, &&op00, &&op65, &&op66, &&op67,
886  &&op68, &&op69, &&op6A, &&op6B, &&op6C, &&op00, &&op6E, &&op6F,
887  &&op70, &&op71, &&op72, &&op73, &&op74, &&op75, &&op76, &&op77,
888  &&op78, &&op79, &&op7A, &&op7B, &&op7C, &&op7D, &&op7E, &&op00,
889  &&op80, &&op81, &&op82, &&op83, &&op84, &&op85, &&op86, &&op87,
890  &&op88, &&op89, &&op8A, &&op8B, &&op8C, &&op8D, &&op8E, &&op8F,
891  &&op90, &&op91, &&op92, &&op93, &&op94, &&op95, &&op96, &&op97,
892  &&op98, &&op99, &&op9A, &&op9B, &&op9C, &&op9D, &&op9E, &&op9F,
893  &&opA0, &&opA1, &&opA2, &&opA3, &&opA4, &&opA5, &&opA6, &&opA7,
894  &&opA8, &&opA9, &&opAA, &&opAB, &&opAC, &&opAD, &&opAE, &&opAF,
895  &&opB0, &&opB1, &&opB2, &&opB3, &&opB4, &&opB5, &&opB6, &&opB7,
896  &&opB8, &&opB9, &&opBA, &&opBB, &&opBC, &&opBD, &&opBE, &&opBF,
897  &&opC0, &&opC1, &&opC2, &&opC3, &&opC4, &&opC5, &&opC6, &&opC7,
898  &&opC8, &&opC9, &&opCA, &&opCB, &&opCC, &&opCD, &&opCE, &&opCF,
899  &&opD0, &&opD1, &&opD2, &&opD3, &&opD4, &&opD5, &&opD6, &&opD7,
900  &&opD8, &&opD9, &&opDA, &&opDB, &&opDC, &&opDD, &&opDE, &&opDF,
901  &&opE0, &&opE1, &&opE2, &&opE3, &&opE4, &&opE5, &&opE6, &&opE7,
902  &&opE8, &&opE9, &&opEA, &&opEB, &&opEC, &&opED, &&opEE, &&opEF,
903  &&opF0, &&opF1, &&opF2, &&opF3, &&opF4, &&opF5, &&opF6, &&opF7,
904  &&opF8, &&opF9, &&opFA, &&opFB, &&opFC, &&opFD, &&opFE, &&opFF,
905  };
906 
907 // Check T::limitReached(). If it's OK to continue,
908 // fetch and execute next instruction.
909 #define NEXT \
910  setPC(getPC() + ii.length); \
911  T::add(ii.cycles); \
912  T::R800Refresh(*this); \
913  if (likely(!T::limitReached())) { \
914  incR(1); \
915  unsigned address = getPC(); \
916  const byte* line = readCacheLine[address >> CacheLine::BITS]; \
917  if (likely(line != nullptr)) { \
918  T::template PRE_MEM<false, false>(address); \
919  T::template POST_MEM< false>(address); \
920  byte op = line[address]; \
921  goto *(opcodeTable[op]); \
922  } else { \
923  goto fetchSlow; \
924  } \
925  } \
926  return;
927 
928 // After some instructions we must always exit the CPU loop (ei, halt, retn)
929 #define NEXT_STOP \
930  setPC(getPC() + ii.length); \
931  T::add(ii.cycles); \
932  T::R800Refresh(*this); \
933  assert(T::limitReached()); \
934  return;
935 
936 #define NEXT_EI \
937  setPC(getPC() + ii.length); \
938  T::add(ii.cycles); \
939  /* !! NO T::R800Refresh(*this); !! */ \
940  assert(T::limitReached()); \
941  return;
942 
943 // Define a label (instead of case in a switch statement)
944 #define CASE(X) op##X:
945 
946 #else // USE_COMPUTED_GOTO
947 
948 #define NEXT \
949  setPC(getPC() + ii.length); \
950  T::add(ii.cycles); \
951  T::R800Refresh(*this); \
952  if (likely(!T::limitReached())) { \
953  goto start; \
954  } \
955  return;
956 
957 #define NEXT_STOP \
958  setPC(getPC() + ii.length); \
959  T::add(ii.cycles); \
960  T::R800Refresh(*this); \
961  assert(T::limitReached()); \
962  return;
963 
964 #define NEXT_EI \
965  setPC(getPC() + ii.length); \
966  T::add(ii.cycles); \
967  /* !! NO T::R800Refresh(*this); !! */ \
968  assert(T::limitReached()); \
969  return;
970 
971 #define CASE(X) case 0x##X:
972 
973 #endif // USE_COMPUTED_GOTO
974 
975 #ifndef USE_COMPUTED_GOTO
976 start:
977 #endif
978  unsigned ixy; // for dd_cb/fd_cb
979  byte opcodeMain = RDMEM_OPCODE<0>(T::CC_MAIN);
980  incR(1);
981 #ifdef USE_COMPUTED_GOTO
982  goto *(opcodeTable[opcodeMain]);
983 
984 fetchSlow: {
985  unsigned address = getPC();
986  byte opcodeSlow = RDMEMslow<false, false>(address, T::CC_MAIN);
987  goto *(opcodeTable[opcodeSlow]);
988 }
989 #endif
990 
991 #ifndef USE_COMPUTED_GOTO
992 switchopcode:
993  switch (opcodeMain) {
994 CASE(40) // ld b,b
995 CASE(49) // ld c,c
996 CASE(52) // ld d,d
997 CASE(5B) // ld e,e
998 CASE(64) // ld h,h
999 CASE(6D) // ld l,l
1000 CASE(7F) // ld a,a
1001 #endif
1002 CASE(00) { II ii = nop(); NEXT; }
1003 CASE(07) { II ii = rlca(); NEXT; }
1004 CASE(0F) { II ii = rrca(); NEXT; }
1005 CASE(17) { II ii = rla(); NEXT; }
1006 CASE(1F) { II ii = rra(); NEXT; }
1007 CASE(08) { II ii = ex_af_af(); NEXT; }
1008 CASE(27) { II ii = daa(); NEXT; }
1009 CASE(2F) { II ii = cpl(); NEXT; }
1010 CASE(37) { II ii = scf(); NEXT; }
1011 CASE(3F) { II ii = ccf(); NEXT; }
1012 CASE(20) { II ii = jr(CondNZ()); NEXT; }
1013 CASE(28) { II ii = jr(CondZ ()); NEXT; }
1014 CASE(30) { II ii = jr(CondNC()); NEXT; }
1015 CASE(38) { II ii = jr(CondC ()); NEXT; }
1016 CASE(18) { II ii = jr(CondTrue()); NEXT; }
1017 CASE(10) { II ii = djnz(); NEXT; }
1018 CASE(32) { II ii = ld_xbyte_a(); NEXT; }
1019 CASE(3A) { II ii = ld_a_xbyte(); NEXT; }
1020 CASE(22) { II ii = ld_xword_SS<HL,0>(); NEXT; }
1021 CASE(2A) { II ii = ld_SS_xword<HL,0>(); NEXT; }
1022 CASE(02) { II ii = ld_SS_a<BC>(); NEXT; }
1023 CASE(12) { II ii = ld_SS_a<DE>(); NEXT; }
1024 CASE(1A) { II ii = ld_a_SS<DE>(); NEXT; }
1025 CASE(0A) { II ii = ld_a_SS<BC>(); NEXT; }
1026 CASE(03) { II ii = inc_SS<BC,0>(); NEXT; }
1027 CASE(13) { II ii = inc_SS<DE,0>(); NEXT; }
1028 CASE(23) { II ii = inc_SS<HL,0>(); NEXT; }
1029 CASE(33) { II ii = inc_SS<SP,0>(); NEXT; }
1030 CASE(0B) { II ii = dec_SS<BC,0>(); NEXT; }
1031 CASE(1B) { II ii = dec_SS<DE,0>(); NEXT; }
1032 CASE(2B) { II ii = dec_SS<HL,0>(); NEXT; }
1033 CASE(3B) { II ii = dec_SS<SP,0>(); NEXT; }
1034 CASE(09) { II ii = add_SS_TT<HL,BC,0>(); NEXT; }
1035 CASE(19) { II ii = add_SS_TT<HL,DE,0>(); NEXT; }
1036 CASE(29) { II ii = add_SS_SS<HL ,0>(); NEXT; }
1037 CASE(39) { II ii = add_SS_TT<HL,SP,0>(); NEXT; }
1038 CASE(01) { II ii = ld_SS_word<BC,0>(); NEXT; }
1039 CASE(11) { II ii = ld_SS_word<DE,0>(); NEXT; }
1040 CASE(21) { II ii = ld_SS_word<HL,0>(); NEXT; }
1041 CASE(31) { II ii = ld_SS_word<SP,0>(); NEXT; }
1042 CASE(04) { II ii = inc_R<B,0>(); NEXT; }
1043 CASE(0C) { II ii = inc_R<C,0>(); NEXT; }
1044 CASE(14) { II ii = inc_R<D,0>(); NEXT; }
1045 CASE(1C) { II ii = inc_R<E,0>(); NEXT; }
1046 CASE(24) { II ii = inc_R<H,0>(); NEXT; }
1047 CASE(2C) { II ii = inc_R<L,0>(); NEXT; }
1048 CASE(3C) { II ii = inc_R<A,0>(); NEXT; }
1049 CASE(34) { II ii = inc_xhl(); NEXT; }
1050 CASE(05) { II ii = dec_R<B,0>(); NEXT; }
1051 CASE(0D) { II ii = dec_R<C,0>(); NEXT; }
1052 CASE(15) { II ii = dec_R<D,0>(); NEXT; }
1053 CASE(1D) { II ii = dec_R<E,0>(); NEXT; }
1054 CASE(25) { II ii = dec_R<H,0>(); NEXT; }
1055 CASE(2D) { II ii = dec_R<L,0>(); NEXT; }
1056 CASE(3D) { II ii = dec_R<A,0>(); NEXT; }
1057 CASE(35) { II ii = dec_xhl(); NEXT; }
1058 CASE(06) { II ii = ld_R_byte<B,0>(); NEXT; }
1059 CASE(0E) { II ii = ld_R_byte<C,0>(); NEXT; }
1060 CASE(16) { II ii = ld_R_byte<D,0>(); NEXT; }
1061 CASE(1E) { II ii = ld_R_byte<E,0>(); NEXT; }
1062 CASE(26) { II ii = ld_R_byte<H,0>(); NEXT; }
1063 CASE(2E) { II ii = ld_R_byte<L,0>(); NEXT; }
1064 CASE(3E) { II ii = ld_R_byte<A,0>(); NEXT; }
1065 CASE(36) { II ii = ld_xhl_byte(); NEXT; }
1066 
1067 CASE(41) { II ii = ld_R_R<B,C,0>(); NEXT; }
1068 CASE(42) { II ii = ld_R_R<B,D,0>(); NEXT; }
1069 CASE(43) { II ii = ld_R_R<B,E,0>(); NEXT; }
1070 CASE(44) { II ii = ld_R_R<B,H,0>(); NEXT; }
1071 CASE(45) { II ii = ld_R_R<B,L,0>(); NEXT; }
1072 CASE(47) { II ii = ld_R_R<B,A,0>(); NEXT; }
1073 CASE(48) { II ii = ld_R_R<C,B,0>(); NEXT; }
1074 CASE(4A) { II ii = ld_R_R<C,D,0>(); NEXT; }
1075 CASE(4B) { II ii = ld_R_R<C,E,0>(); NEXT; }
1076 CASE(4C) { II ii = ld_R_R<C,H,0>(); NEXT; }
1077 CASE(4D) { II ii = ld_R_R<C,L,0>(); NEXT; }
1078 CASE(4F) { II ii = ld_R_R<C,A,0>(); NEXT; }
1079 CASE(50) { II ii = ld_R_R<D,B,0>(); NEXT; }
1080 CASE(51) { II ii = ld_R_R<D,C,0>(); NEXT; }
1081 CASE(53) { II ii = ld_R_R<D,E,0>(); NEXT; }
1082 CASE(54) { II ii = ld_R_R<D,H,0>(); NEXT; }
1083 CASE(55) { II ii = ld_R_R<D,L,0>(); NEXT; }
1084 CASE(57) { II ii = ld_R_R<D,A,0>(); NEXT; }
1085 CASE(58) { II ii = ld_R_R<E,B,0>(); NEXT; }
1086 CASE(59) { II ii = ld_R_R<E,C,0>(); NEXT; }
1087 CASE(5A) { II ii = ld_R_R<E,D,0>(); NEXT; }
1088 CASE(5C) { II ii = ld_R_R<E,H,0>(); NEXT; }
1089 CASE(5D) { II ii = ld_R_R<E,L,0>(); NEXT; }
1090 CASE(5F) { II ii = ld_R_R<E,A,0>(); NEXT; }
1091 CASE(60) { II ii = ld_R_R<H,B,0>(); NEXT; }
1092 CASE(61) { II ii = ld_R_R<H,C,0>(); NEXT; }
1093 CASE(62) { II ii = ld_R_R<H,D,0>(); NEXT; }
1094 CASE(63) { II ii = ld_R_R<H,E,0>(); NEXT; }
1095 CASE(65) { II ii = ld_R_R<H,L,0>(); NEXT; }
1096 CASE(67) { II ii = ld_R_R<H,A,0>(); NEXT; }
1097 CASE(68) { II ii = ld_R_R<L,B,0>(); NEXT; }
1098 CASE(69) { II ii = ld_R_R<L,C,0>(); NEXT; }
1099 CASE(6A) { II ii = ld_R_R<L,D,0>(); NEXT; }
1100 CASE(6B) { II ii = ld_R_R<L,E,0>(); NEXT; }
1101 CASE(6C) { II ii = ld_R_R<L,H,0>(); NEXT; }
1102 CASE(6F) { II ii = ld_R_R<L,A,0>(); NEXT; }
1103 CASE(78) { II ii = ld_R_R<A,B,0>(); NEXT; }
1104 CASE(79) { II ii = ld_R_R<A,C,0>(); NEXT; }
1105 CASE(7A) { II ii = ld_R_R<A,D,0>(); NEXT; }
1106 CASE(7B) { II ii = ld_R_R<A,E,0>(); NEXT; }
1107 CASE(7C) { II ii = ld_R_R<A,H,0>(); NEXT; }
1108 CASE(7D) { II ii = ld_R_R<A,L,0>(); NEXT; }
1109 CASE(70) { II ii = ld_xhl_R<B>(); NEXT; }
1110 CASE(71) { II ii = ld_xhl_R<C>(); NEXT; }
1111 CASE(72) { II ii = ld_xhl_R<D>(); NEXT; }
1112 CASE(73) { II ii = ld_xhl_R<E>(); NEXT; }
1113 CASE(74) { II ii = ld_xhl_R<H>(); NEXT; }
1114 CASE(75) { II ii = ld_xhl_R<L>(); NEXT; }
1115 CASE(77) { II ii = ld_xhl_R<A>(); NEXT; }
1116 CASE(46) { II ii = ld_R_xhl<B>(); NEXT; }
1117 CASE(4E) { II ii = ld_R_xhl<C>(); NEXT; }
1118 CASE(56) { II ii = ld_R_xhl<D>(); NEXT; }
1119 CASE(5E) { II ii = ld_R_xhl<E>(); NEXT; }
1120 CASE(66) { II ii = ld_R_xhl<H>(); NEXT; }
1121 CASE(6E) { II ii = ld_R_xhl<L>(); NEXT; }
1122 CASE(7E) { II ii = ld_R_xhl<A>(); NEXT; }
1123 CASE(76) { II ii = halt(); NEXT_STOP; }
1124 
1125 CASE(80) { II ii = add_a_R<B,0>(); NEXT; }
1126 CASE(81) { II ii = add_a_R<C,0>(); NEXT; }
1127 CASE(82) { II ii = add_a_R<D,0>(); NEXT; }
1128 CASE(83) { II ii = add_a_R<E,0>(); NEXT; }
1129 CASE(84) { II ii = add_a_R<H,0>(); NEXT; }
1130 CASE(85) { II ii = add_a_R<L,0>(); NEXT; }
1131 CASE(86) { II ii = add_a_xhl(); NEXT; }
1132 CASE(87) { II ii = add_a_a(); NEXT; }
1133 CASE(88) { II ii = adc_a_R<B,0>(); NEXT; }
1134 CASE(89) { II ii = adc_a_R<C,0>(); NEXT; }
1135 CASE(8A) { II ii = adc_a_R<D,0>(); NEXT; }
1136 CASE(8B) { II ii = adc_a_R<E,0>(); NEXT; }
1137 CASE(8C) { II ii = adc_a_R<H,0>(); NEXT; }
1138 CASE(8D) { II ii = adc_a_R<L,0>(); NEXT; }
1139 CASE(8E) { II ii = adc_a_xhl(); NEXT; }
1140 CASE(8F) { II ii = adc_a_a(); NEXT; }
1141 CASE(90) { II ii = sub_R<B,0>(); NEXT; }
1142 CASE(91) { II ii = sub_R<C,0>(); NEXT; }
1143 CASE(92) { II ii = sub_R<D,0>(); NEXT; }
1144 CASE(93) { II ii = sub_R<E,0>(); NEXT; }
1145 CASE(94) { II ii = sub_R<H,0>(); NEXT; }
1146 CASE(95) { II ii = sub_R<L,0>(); NEXT; }
1147 CASE(96) { II ii = sub_xhl(); NEXT; }
1148 CASE(97) { II ii = sub_a(); NEXT; }
1149 CASE(98) { II ii = sbc_a_R<B,0>(); NEXT; }
1150 CASE(99) { II ii = sbc_a_R<C,0>(); NEXT; }
1151 CASE(9A) { II ii = sbc_a_R<D,0>(); NEXT; }
1152 CASE(9B) { II ii = sbc_a_R<E,0>(); NEXT; }
1153 CASE(9C) { II ii = sbc_a_R<H,0>(); NEXT; }
1154 CASE(9D) { II ii = sbc_a_R<L,0>(); NEXT; }
1155 CASE(9E) { II ii = sbc_a_xhl(); NEXT; }
1156 CASE(9F) { II ii = sbc_a_a(); NEXT; }
1157 CASE(A0) { II ii = and_R<B,0>(); NEXT; }
1158 CASE(A1) { II ii = and_R<C,0>(); NEXT; }
1159 CASE(A2) { II ii = and_R<D,0>(); NEXT; }
1160 CASE(A3) { II ii = and_R<E,0>(); NEXT; }
1161 CASE(A4) { II ii = and_R<H,0>(); NEXT; }
1162 CASE(A5) { II ii = and_R<L,0>(); NEXT; }
1163 CASE(A6) { II ii = and_xhl(); NEXT; }
1164 CASE(A7) { II ii = and_a(); NEXT; }
1165 CASE(A8) { II ii = xor_R<B,0>(); NEXT; }
1166 CASE(A9) { II ii = xor_R<C,0>(); NEXT; }
1167 CASE(AA) { II ii = xor_R<D,0>(); NEXT; }
1168 CASE(AB) { II ii = xor_R<E,0>(); NEXT; }
1169 CASE(AC) { II ii = xor_R<H,0>(); NEXT; }
1170 CASE(AD) { II ii = xor_R<L,0>(); NEXT; }
1171 CASE(AE) { II ii = xor_xhl(); NEXT; }
1172 CASE(AF) { II ii = xor_a(); NEXT; }
1173 CASE(B0) { II ii = or_R<B,0>(); NEXT; }
1174 CASE(B1) { II ii = or_R<C,0>(); NEXT; }
1175 CASE(B2) { II ii = or_R<D,0>(); NEXT; }
1176 CASE(B3) { II ii = or_R<E,0>(); NEXT; }
1177 CASE(B4) { II ii = or_R<H,0>(); NEXT; }
1178 CASE(B5) { II ii = or_R<L,0>(); NEXT; }
1179 CASE(B6) { II ii = or_xhl(); NEXT; }
1180 CASE(B7) { II ii = or_a(); NEXT; }
1181 CASE(B8) { II ii = cp_R<B,0>(); NEXT; }
1182 CASE(B9) { II ii = cp_R<C,0>(); NEXT; }
1183 CASE(BA) { II ii = cp_R<D,0>(); NEXT; }
1184 CASE(BB) { II ii = cp_R<E,0>(); NEXT; }
1185 CASE(BC) { II ii = cp_R<H,0>(); NEXT; }
1186 CASE(BD) { II ii = cp_R<L,0>(); NEXT; }
1187 CASE(BE) { II ii = cp_xhl(); NEXT; }
1188 CASE(BF) { II ii = cp_a(); NEXT; }
1189 
1190 CASE(D3) { II ii = out_byte_a(); NEXT; }
1191 CASE(DB) { II ii = in_a_byte(); NEXT; }
1192 CASE(D9) { II ii = exx(); NEXT; }
1193 CASE(E3) { II ii = ex_xsp_SS<HL,0>(); NEXT; }
1194 CASE(EB) { II ii = ex_de_hl(); NEXT; }
1195 CASE(E9) { II ii = jp_SS<HL,0>(); NEXT; }
1196 CASE(F9) { II ii = ld_sp_SS<HL,0>(); NEXT; }
1197 CASE(F3) { II ii = di(); NEXT; }
1198 CASE(FB) { II ii = ei(); NEXT_EI; }
1199 CASE(C6) { II ii = add_a_byte(); NEXT; }
1200 CASE(CE) { II ii = adc_a_byte(); NEXT; }
1201 CASE(D6) { II ii = sub_byte(); NEXT; }
1202 CASE(DE) { II ii = sbc_a_byte(); NEXT; }
1203 CASE(E6) { II ii = and_byte(); NEXT; }
1204 CASE(EE) { II ii = xor_byte(); NEXT; }
1205 CASE(F6) { II ii = or_byte(); NEXT; }
1206 CASE(FE) { II ii = cp_byte(); NEXT; }
1207 CASE(C0) { II ii = ret(CondNZ()); NEXT; }
1208 CASE(C8) { II ii = ret(CondZ ()); NEXT; }
1209 CASE(D0) { II ii = ret(CondNC()); NEXT; }
1210 CASE(D8) { II ii = ret(CondC ()); NEXT; }
1211 CASE(E0) { II ii = ret(CondPO()); NEXT; }
1212 CASE(E8) { II ii = ret(CondPE()); NEXT; }
1213 CASE(F0) { II ii = ret(CondP ()); NEXT; }
1214 CASE(F8) { II ii = ret(CondM ()); NEXT; }
1215 CASE(C9) { II ii = ret(); NEXT; }
1216 CASE(C2) { II ii = jp(CondNZ()); NEXT; }
1217 CASE(CA) { II ii = jp(CondZ ()); NEXT; }
1218 CASE(D2) { II ii = jp(CondNC()); NEXT; }
1219 CASE(DA) { II ii = jp(CondC ()); NEXT; }
1220 CASE(E2) { II ii = jp(CondPO()); NEXT; }
1221 CASE(EA) { II ii = jp(CondPE()); NEXT; }
1222 CASE(F2) { II ii = jp(CondP ()); NEXT; }
1223 CASE(FA) { II ii = jp(CondM ()); NEXT; }
1224 CASE(C3) { II ii = jp(CondTrue()); NEXT; }
1225 CASE(C4) { II ii = call(CondNZ()); NEXT; }
1226 CASE(CC) { II ii = call(CondZ ()); NEXT; }
1227 CASE(D4) { II ii = call(CondNC()); NEXT; }
1228 CASE(DC) { II ii = call(CondC ()); NEXT; }
1229 CASE(E4) { II ii = call(CondPO()); NEXT; }
1230 CASE(EC) { II ii = call(CondPE()); NEXT; }
1231 CASE(F4) { II ii = call(CondP ()); NEXT; }
1232 CASE(FC) { II ii = call(CondM ()); NEXT; }
1233 CASE(CD) { II ii = call(CondTrue()); NEXT; }
1234 CASE(C1) { II ii = pop_SS <BC,0>(); NEXT; }
1235 CASE(D1) { II ii = pop_SS <DE,0>(); NEXT; }
1236 CASE(E1) { II ii = pop_SS <HL,0>(); NEXT; }
1237 CASE(F1) { II ii = pop_SS <AF,0>(); NEXT; }
1238 CASE(C5) { II ii = push_SS<BC,0>(); NEXT; }
1239 CASE(D5) { II ii = push_SS<DE,0>(); NEXT; }
1240 CASE(E5) { II ii = push_SS<HL,0>(); NEXT; }
1241 CASE(F5) { II ii = push_SS<AF,0>(); NEXT; }
1242 CASE(C7) { II ii = rst<0x00>(); NEXT; }
1243 CASE(CF) { II ii = rst<0x08>(); NEXT; }
1244 CASE(D7) { II ii = rst<0x10>(); NEXT; }
1245 CASE(DF) { II ii = rst<0x18>(); NEXT; }
1246 CASE(E7) { II ii = rst<0x20>(); NEXT; }
1247 CASE(EF) { II ii = rst<0x28>(); NEXT; }
1248 CASE(F7) { II ii = rst<0x30>(); NEXT; }
1249 CASE(FF) { II ii = rst<0x38>(); NEXT; }
1250 CASE(CB) {
1251  setPC(getPC() + 1); // M1 cycle at this point
1252  byte cb_opcode = RDMEM_OPCODE<0>(T::CC_PREFIX);
1253  incR(1);
1254  switch (cb_opcode) {
1255  case 0x00: { II ii = rlc_R<B>(); NEXT; }
1256  case 0x01: { II ii = rlc_R<C>(); NEXT; }
1257  case 0x02: { II ii = rlc_R<D>(); NEXT; }
1258  case 0x03: { II ii = rlc_R<E>(); NEXT; }
1259  case 0x04: { II ii = rlc_R<H>(); NEXT; }
1260  case 0x05: { II ii = rlc_R<L>(); NEXT; }
1261  case 0x07: { II ii = rlc_R<A>(); NEXT; }
1262  case 0x06: { II ii = rlc_xhl(); NEXT; }
1263  case 0x08: { II ii = rrc_R<B>(); NEXT; }
1264  case 0x09: { II ii = rrc_R<C>(); NEXT; }
1265  case 0x0a: { II ii = rrc_R<D>(); NEXT; }
1266  case 0x0b: { II ii = rrc_R<E>(); NEXT; }
1267  case 0x0c: { II ii = rrc_R<H>(); NEXT; }
1268  case 0x0d: { II ii = rrc_R<L>(); NEXT; }
1269  case 0x0f: { II ii = rrc_R<A>(); NEXT; }
1270  case 0x0e: { II ii = rrc_xhl(); NEXT; }
1271  case 0x10: { II ii = rl_R<B>(); NEXT; }
1272  case 0x11: { II ii = rl_R<C>(); NEXT; }
1273  case 0x12: { II ii = rl_R<D>(); NEXT; }
1274  case 0x13: { II ii = rl_R<E>(); NEXT; }
1275  case 0x14: { II ii = rl_R<H>(); NEXT; }
1276  case 0x15: { II ii = rl_R<L>(); NEXT; }
1277  case 0x17: { II ii = rl_R<A>(); NEXT; }
1278  case 0x16: { II ii = rl_xhl(); NEXT; }
1279  case 0x18: { II ii = rr_R<B>(); NEXT; }
1280  case 0x19: { II ii = rr_R<C>(); NEXT; }
1281  case 0x1a: { II ii = rr_R<D>(); NEXT; }
1282  case 0x1b: { II ii = rr_R<E>(); NEXT; }
1283  case 0x1c: { II ii = rr_R<H>(); NEXT; }
1284  case 0x1d: { II ii = rr_R<L>(); NEXT; }
1285  case 0x1f: { II ii = rr_R<A>(); NEXT; }
1286  case 0x1e: { II ii = rr_xhl(); NEXT; }
1287  case 0x20: { II ii = sla_R<B>(); NEXT; }
1288  case 0x21: { II ii = sla_R<C>(); NEXT; }
1289  case 0x22: { II ii = sla_R<D>(); NEXT; }
1290  case 0x23: { II ii = sla_R<E>(); NEXT; }
1291  case 0x24: { II ii = sla_R<H>(); NEXT; }
1292  case 0x25: { II ii = sla_R<L>(); NEXT; }
1293  case 0x27: { II ii = sla_R<A>(); NEXT; }
1294  case 0x26: { II ii = sla_xhl(); NEXT; }
1295  case 0x28: { II ii = sra_R<B>(); NEXT; }
1296  case 0x29: { II ii = sra_R<C>(); NEXT; }
1297  case 0x2a: { II ii = sra_R<D>(); NEXT; }
1298  case 0x2b: { II ii = sra_R<E>(); NEXT; }
1299  case 0x2c: { II ii = sra_R<H>(); NEXT; }
1300  case 0x2d: { II ii = sra_R<L>(); NEXT; }
1301  case 0x2f: { II ii = sra_R<A>(); NEXT; }
1302  case 0x2e: { II ii = sra_xhl(); NEXT; }
1303  case 0x30: { II ii = T::isR800() ? sla_R<B>() : sll_R<B>(); NEXT; }
1304  case 0x31: { II ii = T::isR800() ? sla_R<C>() : sll_R<C>(); NEXT; }
1305  case 0x32: { II ii = T::isR800() ? sla_R<D>() : sll_R<D>(); NEXT; }
1306  case 0x33: { II ii = T::isR800() ? sla_R<E>() : sll_R<E>(); NEXT; }
1307  case 0x34: { II ii = T::isR800() ? sla_R<H>() : sll_R<H>(); NEXT; }
1308  case 0x35: { II ii = T::isR800() ? sla_R<L>() : sll_R<L>(); NEXT; }
1309  case 0x37: { II ii = T::isR800() ? sla_R<A>() : sll_R<A>(); NEXT; }
1310  case 0x36: { II ii = T::isR800() ? sla_xhl() : sll_xhl(); NEXT; }
1311  case 0x38: { II ii = srl_R<B>(); NEXT; }
1312  case 0x39: { II ii = srl_R<C>(); NEXT; }
1313  case 0x3a: { II ii = srl_R<D>(); NEXT; }
1314  case 0x3b: { II ii = srl_R<E>(); NEXT; }
1315  case 0x3c: { II ii = srl_R<H>(); NEXT; }
1316  case 0x3d: { II ii = srl_R<L>(); NEXT; }
1317  case 0x3f: { II ii = srl_R<A>(); NEXT; }
1318  case 0x3e: { II ii = srl_xhl(); NEXT; }
1319 
1320  case 0x40: { II ii = bit_N_R<0,B>(); NEXT; }
1321  case 0x41: { II ii = bit_N_R<0,C>(); NEXT; }
1322  case 0x42: { II ii = bit_N_R<0,D>(); NEXT; }
1323  case 0x43: { II ii = bit_N_R<0,E>(); NEXT; }
1324  case 0x44: { II ii = bit_N_R<0,H>(); NEXT; }
1325  case 0x45: { II ii = bit_N_R<0,L>(); NEXT; }
1326  case 0x47: { II ii = bit_N_R<0,A>(); NEXT; }
1327  case 0x48: { II ii = bit_N_R<1,B>(); NEXT; }
1328  case 0x49: { II ii = bit_N_R<1,C>(); NEXT; }
1329  case 0x4a: { II ii = bit_N_R<1,D>(); NEXT; }
1330  case 0x4b: { II ii = bit_N_R<1,E>(); NEXT; }
1331  case 0x4c: { II ii = bit_N_R<1,H>(); NEXT; }
1332  case 0x4d: { II ii = bit_N_R<1,L>(); NEXT; }
1333  case 0x4f: { II ii = bit_N_R<1,A>(); NEXT; }
1334  case 0x50: { II ii = bit_N_R<2,B>(); NEXT; }
1335  case 0x51: { II ii = bit_N_R<2,C>(); NEXT; }
1336  case 0x52: { II ii = bit_N_R<2,D>(); NEXT; }
1337  case 0x53: { II ii = bit_N_R<2,E>(); NEXT; }
1338  case 0x54: { II ii = bit_N_R<2,H>(); NEXT; }
1339  case 0x55: { II ii = bit_N_R<2,L>(); NEXT; }
1340  case 0x57: { II ii = bit_N_R<2,A>(); NEXT; }
1341  case 0x58: { II ii = bit_N_R<3,B>(); NEXT; }
1342  case 0x59: { II ii = bit_N_R<3,C>(); NEXT; }
1343  case 0x5a: { II ii = bit_N_R<3,D>(); NEXT; }
1344  case 0x5b: { II ii = bit_N_R<3,E>(); NEXT; }
1345  case 0x5c: { II ii = bit_N_R<3,H>(); NEXT; }
1346  case 0x5d: { II ii = bit_N_R<3,L>(); NEXT; }
1347  case 0x5f: { II ii = bit_N_R<3,A>(); NEXT; }
1348  case 0x60: { II ii = bit_N_R<4,B>(); NEXT; }
1349  case 0x61: { II ii = bit_N_R<4,C>(); NEXT; }
1350  case 0x62: { II ii = bit_N_R<4,D>(); NEXT; }
1351  case 0x63: { II ii = bit_N_R<4,E>(); NEXT; }
1352  case 0x64: { II ii = bit_N_R<4,H>(); NEXT; }
1353  case 0x65: { II ii = bit_N_R<4,L>(); NEXT; }
1354  case 0x67: { II ii = bit_N_R<4,A>(); NEXT; }
1355  case 0x68: { II ii = bit_N_R<5,B>(); NEXT; }
1356  case 0x69: { II ii = bit_N_R<5,C>(); NEXT; }
1357  case 0x6a: { II ii = bit_N_R<5,D>(); NEXT; }
1358  case 0x6b: { II ii = bit_N_R<5,E>(); NEXT; }
1359  case 0x6c: { II ii = bit_N_R<5,H>(); NEXT; }
1360  case 0x6d: { II ii = bit_N_R<5,L>(); NEXT; }
1361  case 0x6f: { II ii = bit_N_R<5,A>(); NEXT; }
1362  case 0x70: { II ii = bit_N_R<6,B>(); NEXT; }
1363  case 0x71: { II ii = bit_N_R<6,C>(); NEXT; }
1364  case 0x72: { II ii = bit_N_R<6,D>(); NEXT; }
1365  case 0x73: { II ii = bit_N_R<6,E>(); NEXT; }
1366  case 0x74: { II ii = bit_N_R<6,H>(); NEXT; }
1367  case 0x75: { II ii = bit_N_R<6,L>(); NEXT; }
1368  case 0x77: { II ii = bit_N_R<6,A>(); NEXT; }
1369  case 0x78: { II ii = bit_N_R<7,B>(); NEXT; }
1370  case 0x79: { II ii = bit_N_R<7,C>(); NEXT; }
1371  case 0x7a: { II ii = bit_N_R<7,D>(); NEXT; }
1372  case 0x7b: { II ii = bit_N_R<7,E>(); NEXT; }
1373  case 0x7c: { II ii = bit_N_R<7,H>(); NEXT; }
1374  case 0x7d: { II ii = bit_N_R<7,L>(); NEXT; }
1375  case 0x7f: { II ii = bit_N_R<7,A>(); NEXT; }
1376  case 0x46: { II ii = bit_N_xhl<0>(); NEXT; }
1377  case 0x4e: { II ii = bit_N_xhl<1>(); NEXT; }
1378  case 0x56: { II ii = bit_N_xhl<2>(); NEXT; }
1379  case 0x5e: { II ii = bit_N_xhl<3>(); NEXT; }
1380  case 0x66: { II ii = bit_N_xhl<4>(); NEXT; }
1381  case 0x6e: { II ii = bit_N_xhl<5>(); NEXT; }
1382  case 0x76: { II ii = bit_N_xhl<6>(); NEXT; }
1383  case 0x7e: { II ii = bit_N_xhl<7>(); NEXT; }
1384 
1385  case 0x80: { II ii = res_N_R<0,B>(); NEXT; }
1386  case 0x81: { II ii = res_N_R<0,C>(); NEXT; }
1387  case 0x82: { II ii = res_N_R<0,D>(); NEXT; }
1388  case 0x83: { II ii = res_N_R<0,E>(); NEXT; }
1389  case 0x84: { II ii = res_N_R<0,H>(); NEXT; }
1390  case 0x85: { II ii = res_N_R<0,L>(); NEXT; }
1391  case 0x87: { II ii = res_N_R<0,A>(); NEXT; }
1392  case 0x88: { II ii = res_N_R<1,B>(); NEXT; }
1393  case 0x89: { II ii = res_N_R<1,C>(); NEXT; }
1394  case 0x8a: { II ii = res_N_R<1,D>(); NEXT; }
1395  case 0x8b: { II ii = res_N_R<1,E>(); NEXT; }
1396  case 0x8c: { II ii = res_N_R<1,H>(); NEXT; }
1397  case 0x8d: { II ii = res_N_R<1,L>(); NEXT; }
1398  case 0x8f: { II ii = res_N_R<1,A>(); NEXT; }
1399  case 0x90: { II ii = res_N_R<2,B>(); NEXT; }
1400  case 0x91: { II ii = res_N_R<2,C>(); NEXT; }
1401  case 0x92: { II ii = res_N_R<2,D>(); NEXT; }
1402  case 0x93: { II ii = res_N_R<2,E>(); NEXT; }
1403  case 0x94: { II ii = res_N_R<2,H>(); NEXT; }
1404  case 0x95: { II ii = res_N_R<2,L>(); NEXT; }
1405  case 0x97: { II ii = res_N_R<2,A>(); NEXT; }
1406  case 0x98: { II ii = res_N_R<3,B>(); NEXT; }
1407  case 0x99: { II ii = res_N_R<3,C>(); NEXT; }
1408  case 0x9a: { II ii = res_N_R<3,D>(); NEXT; }
1409  case 0x9b: { II ii = res_N_R<3,E>(); NEXT; }
1410  case 0x9c: { II ii = res_N_R<3,H>(); NEXT; }
1411  case 0x9d: { II ii = res_N_R<3,L>(); NEXT; }
1412  case 0x9f: { II ii = res_N_R<3,A>(); NEXT; }
1413  case 0xa0: { II ii = res_N_R<4,B>(); NEXT; }
1414  case 0xa1: { II ii = res_N_R<4,C>(); NEXT; }
1415  case 0xa2: { II ii = res_N_R<4,D>(); NEXT; }
1416  case 0xa3: { II ii = res_N_R<4,E>(); NEXT; }
1417  case 0xa4: { II ii = res_N_R<4,H>(); NEXT; }
1418  case 0xa5: { II ii = res_N_R<4,L>(); NEXT; }
1419  case 0xa7: { II ii = res_N_R<4,A>(); NEXT; }
1420  case 0xa8: { II ii = res_N_R<5,B>(); NEXT; }
1421  case 0xa9: { II ii = res_N_R<5,C>(); NEXT; }
1422  case 0xaa: { II ii = res_N_R<5,D>(); NEXT; }
1423  case 0xab: { II ii = res_N_R<5,E>(); NEXT; }
1424  case 0xac: { II ii = res_N_R<5,H>(); NEXT; }
1425  case 0xad: { II ii = res_N_R<5,L>(); NEXT; }
1426  case 0xaf: { II ii = res_N_R<5,A>(); NEXT; }
1427  case 0xb0: { II ii = res_N_R<6,B>(); NEXT; }
1428  case 0xb1: { II ii = res_N_R<6,C>(); NEXT; }
1429  case 0xb2: { II ii = res_N_R<6,D>(); NEXT; }
1430  case 0xb3: { II ii = res_N_R<6,E>(); NEXT; }
1431  case 0xb4: { II ii = res_N_R<6,H>(); NEXT; }
1432  case 0xb5: { II ii = res_N_R<6,L>(); NEXT; }
1433  case 0xb7: { II ii = res_N_R<6,A>(); NEXT; }
1434  case 0xb8: { II ii = res_N_R<7,B>(); NEXT; }
1435  case 0xb9: { II ii = res_N_R<7,C>(); NEXT; }
1436  case 0xba: { II ii = res_N_R<7,D>(); NEXT; }
1437  case 0xbb: { II ii = res_N_R<7,E>(); NEXT; }
1438  case 0xbc: { II ii = res_N_R<7,H>(); NEXT; }
1439  case 0xbd: { II ii = res_N_R<7,L>(); NEXT; }
1440  case 0xbf: { II ii = res_N_R<7,A>(); NEXT; }
1441  case 0x86: { II ii = res_N_xhl<0>(); NEXT; }
1442  case 0x8e: { II ii = res_N_xhl<1>(); NEXT; }
1443  case 0x96: { II ii = res_N_xhl<2>(); NEXT; }
1444  case 0x9e: { II ii = res_N_xhl<3>(); NEXT; }
1445  case 0xa6: { II ii = res_N_xhl<4>(); NEXT; }
1446  case 0xae: { II ii = res_N_xhl<5>(); NEXT; }
1447  case 0xb6: { II ii = res_N_xhl<6>(); NEXT; }
1448  case 0xbe: { II ii = res_N_xhl<7>(); NEXT; }
1449 
1450  case 0xc0: { II ii = set_N_R<0,B>(); NEXT; }
1451  case 0xc1: { II ii = set_N_R<0,C>(); NEXT; }
1452  case 0xc2: { II ii = set_N_R<0,D>(); NEXT; }
1453  case 0xc3: { II ii = set_N_R<0,E>(); NEXT; }
1454  case 0xc4: { II ii = set_N_R<0,H>(); NEXT; }
1455  case 0xc5: { II ii = set_N_R<0,L>(); NEXT; }
1456  case 0xc7: { II ii = set_N_R<0,A>(); NEXT; }
1457  case 0xc8: { II ii = set_N_R<1,B>(); NEXT; }
1458  case 0xc9: { II ii = set_N_R<1,C>(); NEXT; }
1459  case 0xca: { II ii = set_N_R<1,D>(); NEXT; }
1460  case 0xcb: { II ii = set_N_R<1,E>(); NEXT; }
1461  case 0xcc: { II ii = set_N_R<1,H>(); NEXT; }
1462  case 0xcd: { II ii = set_N_R<1,L>(); NEXT; }
1463  case 0xcf: { II ii = set_N_R<1,A>(); NEXT; }
1464  case 0xd0: { II ii = set_N_R<2,B>(); NEXT; }
1465  case 0xd1: { II ii = set_N_R<2,C>(); NEXT; }
1466  case 0xd2: { II ii = set_N_R<2,D>(); NEXT; }
1467  case 0xd3: { II ii = set_N_R<2,E>(); NEXT; }
1468  case 0xd4: { II ii = set_N_R<2,H>(); NEXT; }
1469  case 0xd5: { II ii = set_N_R<2,L>(); NEXT; }
1470  case 0xd7: { II ii = set_N_R<2,A>(); NEXT; }
1471  case 0xd8: { II ii = set_N_R<3,B>(); NEXT; }
1472  case 0xd9: { II ii = set_N_R<3,C>(); NEXT; }
1473  case 0xda: { II ii = set_N_R<3,D>(); NEXT; }
1474  case 0xdb: { II ii = set_N_R<3,E>(); NEXT; }
1475  case 0xdc: { II ii = set_N_R<3,H>(); NEXT; }
1476  case 0xdd: { II ii = set_N_R<3,L>(); NEXT; }
1477  case 0xdf: { II ii = set_N_R<3,A>(); NEXT; }
1478  case 0xe0: { II ii = set_N_R<4,B>(); NEXT; }
1479  case 0xe1: { II ii = set_N_R<4,C>(); NEXT; }
1480  case 0xe2: { II ii = set_N_R<4,D>(); NEXT; }
1481  case 0xe3: { II ii = set_N_R<4,E>(); NEXT; }
1482  case 0xe4: { II ii = set_N_R<4,H>(); NEXT; }
1483  case 0xe5: { II ii = set_N_R<4,L>(); NEXT; }
1484  case 0xe7: { II ii = set_N_R<4,A>(); NEXT; }
1485  case 0xe8: { II ii = set_N_R<5,B>(); NEXT; }
1486  case 0xe9: { II ii = set_N_R<5,C>(); NEXT; }
1487  case 0xea: { II ii = set_N_R<5,D>(); NEXT; }
1488  case 0xeb: { II ii = set_N_R<5,E>(); NEXT; }
1489  case 0xec: { II ii = set_N_R<5,H>(); NEXT; }
1490  case 0xed: { II ii = set_N_R<5,L>(); NEXT; }
1491  case 0xef: { II ii = set_N_R<5,A>(); NEXT; }
1492  case 0xf0: { II ii = set_N_R<6,B>(); NEXT; }
1493  case 0xf1: { II ii = set_N_R<6,C>(); NEXT; }
1494  case 0xf2: { II ii = set_N_R<6,D>(); NEXT; }
1495  case 0xf3: { II ii = set_N_R<6,E>(); NEXT; }
1496  case 0xf4: { II ii = set_N_R<6,H>(); NEXT; }
1497  case 0xf5: { II ii = set_N_R<6,L>(); NEXT; }
1498  case 0xf7: { II ii = set_N_R<6,A>(); NEXT; }
1499  case 0xf8: { II ii = set_N_R<7,B>(); NEXT; }
1500  case 0xf9: { II ii = set_N_R<7,C>(); NEXT; }
1501  case 0xfa: { II ii = set_N_R<7,D>(); NEXT; }
1502  case 0xfb: { II ii = set_N_R<7,E>(); NEXT; }
1503  case 0xfc: { II ii = set_N_R<7,H>(); NEXT; }
1504  case 0xfd: { II ii = set_N_R<7,L>(); NEXT; }
1505  case 0xff: { II ii = set_N_R<7,A>(); NEXT; }
1506  case 0xc6: { II ii = set_N_xhl<0>(); NEXT; }
1507  case 0xce: { II ii = set_N_xhl<1>(); NEXT; }
1508  case 0xd6: { II ii = set_N_xhl<2>(); NEXT; }
1509  case 0xde: { II ii = set_N_xhl<3>(); NEXT; }
1510  case 0xe6: { II ii = set_N_xhl<4>(); NEXT; }
1511  case 0xee: { II ii = set_N_xhl<5>(); NEXT; }
1512  case 0xf6: { II ii = set_N_xhl<6>(); NEXT; }
1513  case 0xfe: { II ii = set_N_xhl<7>(); NEXT; }
1514  default: UNREACHABLE; return;
1515  }
1516 }
1517 CASE(ED) {
1518  setPC(getPC() + 1); // M1 cycle at this point
1519  byte ed_opcode = RDMEM_OPCODE<0>(T::CC_PREFIX);
1520  incR(1);
1521  switch (ed_opcode) {
1522  case 0x00: case 0x01: case 0x02: case 0x03:
1523  case 0x04: case 0x05: case 0x06: case 0x07:
1524  case 0x08: case 0x09: case 0x0a: case 0x0b:
1525  case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1526  case 0x10: case 0x11: case 0x12: case 0x13:
1527  case 0x14: case 0x15: case 0x16: case 0x17:
1528  case 0x18: case 0x19: case 0x1a: case 0x1b:
1529  case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1530  case 0x20: case 0x21: case 0x22: case 0x23:
1531  case 0x24: case 0x25: case 0x26: case 0x27:
1532  case 0x28: case 0x29: case 0x2a: case 0x2b:
1533  case 0x2c: case 0x2d: case 0x2e: case 0x2f:
1534  case 0x30: case 0x31: case 0x32: case 0x33:
1535  case 0x34: case 0x35: case 0x36: case 0x37:
1536  case 0x38: case 0x39: case 0x3a: case 0x3b:
1537  case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1538 
1539  case 0x77: case 0x7f:
1540 
1541  case 0x80: case 0x81: case 0x82: case 0x83:
1542  case 0x84: case 0x85: case 0x86: case 0x87:
1543  case 0x88: case 0x89: case 0x8a: case 0x8b:
1544  case 0x8c: case 0x8d: case 0x8e: case 0x8f:
1545  case 0x90: case 0x91: case 0x92: case 0x93:
1546  case 0x94: case 0x95: case 0x96: case 0x97:
1547  case 0x98: case 0x99: case 0x9a: case 0x9b:
1548  case 0x9c: case 0x9d: case 0x9e: case 0x9f:
1549  case 0xa4: case 0xa5: case 0xa6: case 0xa7:
1550  case 0xac: case 0xad: case 0xae: case 0xaf:
1551  case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1552  case 0xbc: case 0xbd: case 0xbe: case 0xbf:
1553 
1554  case 0xc0: case 0xc2:
1555  case 0xc4: case 0xc5: case 0xc6: case 0xc7:
1556  case 0xc8: case 0xca: case 0xcb:
1557  case 0xcc: case 0xcd: case 0xce: case 0xcf:
1558  case 0xd0: case 0xd2: case 0xd3:
1559  case 0xd4: case 0xd5: case 0xd6: case 0xd7:
1560  case 0xd8: case 0xda: case 0xdb:
1561  case 0xdc: case 0xdd: case 0xde: case 0xdf:
1562  case 0xe0: case 0xe1: case 0xe2: case 0xe3:
1563  case 0xe4: case 0xe5: case 0xe6: case 0xe7:
1564  case 0xe8: case 0xe9: case 0xea: case 0xeb:
1565  case 0xec: case 0xed: case 0xee: case 0xef:
1566  case 0xf0: case 0xf1: case 0xf2:
1567  case 0xf4: case 0xf5: case 0xf6: case 0xf7:
1568  case 0xf8: case 0xf9: case 0xfa: case 0xfb:
1569  case 0xfc: case 0xfd: case 0xfe: case 0xff:
1570  { II ii = nop(); NEXT; }
1571 
1572  case 0x40: { II ii = in_R_c<B>(); NEXT; }
1573  case 0x48: { II ii = in_R_c<C>(); NEXT; }
1574  case 0x50: { II ii = in_R_c<D>(); NEXT; }
1575  case 0x58: { II ii = in_R_c<E>(); NEXT; }
1576  case 0x60: { II ii = in_R_c<H>(); NEXT; }
1577  case 0x68: { II ii = in_R_c<L>(); NEXT; }
1578  case 0x70: { II ii = in_R_c<DUMMY>(); NEXT; }
1579  case 0x78: { II ii = in_R_c<A>(); NEXT; }
1580 
1581  case 0x41: { II ii = out_c_R<B>(); NEXT; }
1582  case 0x49: { II ii = out_c_R<C>(); NEXT; }
1583  case 0x51: { II ii = out_c_R<D>(); NEXT; }
1584  case 0x59: { II ii = out_c_R<E>(); NEXT; }
1585  case 0x61: { II ii = out_c_R<H>(); NEXT; }
1586  case 0x69: { II ii = out_c_R<L>(); NEXT; }
1587  case 0x71: { II ii = out_c_0(); NEXT; }
1588  case 0x79: { II ii = out_c_R<A>(); NEXT; }
1589 
1590  case 0x42: { II ii = sbc_hl_SS<BC>(); NEXT; }
1591  case 0x52: { II ii = sbc_hl_SS<DE>(); NEXT; }
1592  case 0x62: { II ii = sbc_hl_hl (); NEXT; }
1593  case 0x72: { II ii = sbc_hl_SS<SP>(); NEXT; }
1594 
1595  case 0x4a: { II ii = adc_hl_SS<BC>(); NEXT; }
1596  case 0x5a: { II ii = adc_hl_SS<DE>(); NEXT; }
1597  case 0x6a: { II ii = adc_hl_hl (); NEXT; }
1598  case 0x7a: { II ii = adc_hl_SS<SP>(); NEXT; }
1599 
1600  case 0x43: { II ii = ld_xword_SS_ED<BC>(); NEXT; }
1601  case 0x53: { II ii = ld_xword_SS_ED<DE>(); NEXT; }
1602  case 0x63: { II ii = ld_xword_SS_ED<HL>(); NEXT; }
1603  case 0x73: { II ii = ld_xword_SS_ED<SP>(); NEXT; }
1604 
1605  case 0x4b: { II ii = ld_SS_xword_ED<BC>(); NEXT; }
1606  case 0x5b: { II ii = ld_SS_xword_ED<DE>(); NEXT; }
1607  case 0x6b: { II ii = ld_SS_xword_ED<HL>(); NEXT; }
1608  case 0x7b: { II ii = ld_SS_xword_ED<SP>(); NEXT; }
1609 
1610  case 0x47: { II ii = ld_i_a(); NEXT; }
1611  case 0x4f: { II ii = ld_r_a(); NEXT; }
1612  case 0x57: { II ii = ld_a_IR<REG_I>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1613  case 0x5f: { II ii = ld_a_IR<REG_R>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1614 
1615  case 0x67: { II ii = rrd(); NEXT; }
1616  case 0x6f: { II ii = rld(); NEXT; }
1617 
1618  case 0x45: case 0x4d: case 0x55: case 0x5d:
1619  case 0x65: case 0x6d: case 0x75: case 0x7d:
1620  { II ii = retn(); NEXT_STOP; }
1621  case 0x46: case 0x4e: case 0x66: case 0x6e:
1622  { II ii = im_N<0>(); NEXT; }
1623  case 0x56: case 0x76:
1624  { II ii = im_N<1>(); NEXT; }
1625  case 0x5e: case 0x7e:
1626  { II ii = im_N<2>(); NEXT; }
1627  case 0x44: case 0x4c: case 0x54: case 0x5c:
1628  case 0x64: case 0x6c: case 0x74: case 0x7c:
1629  { II ii = neg(); NEXT; }
1630 
1631  case 0xa0: { II ii = ldi(); NEXT; }
1632  case 0xa1: { II ii = cpi(); NEXT; }
1633  case 0xa2: { II ii = ini(); NEXT; }
1634  case 0xa3: { II ii = outi(); NEXT; }
1635  case 0xa8: { II ii = ldd(); NEXT; }
1636  case 0xa9: { II ii = cpd(); NEXT; }
1637  case 0xaa: { II ii = ind(); NEXT; }
1638  case 0xab: { II ii = outd(); NEXT; }
1639  case 0xb0: { II ii = ldir(); NEXT; }
1640  case 0xb1: { II ii = cpir(); NEXT; }
1641  case 0xb2: { II ii = inir(); NEXT; }
1642  case 0xb3: { II ii = otir(); NEXT; }
1643  case 0xb8: { II ii = lddr(); NEXT; }
1644  case 0xb9: { II ii = cpdr(); NEXT; }
1645  case 0xba: { II ii = indr(); NEXT; }
1646  case 0xbb: { II ii = otdr(); NEXT; }
1647 
1648  case 0xc1: { II ii = T::isR800() ? mulub_a_R<B>() : nop(); NEXT; }
1649  case 0xc9: { II ii = T::isR800() ? mulub_a_R<C>() : nop(); NEXT; }
1650  case 0xd1: { II ii = T::isR800() ? mulub_a_R<D>() : nop(); NEXT; }
1651  case 0xd9: { II ii = T::isR800() ? mulub_a_R<E>() : nop(); NEXT; }
1652  case 0xc3: { II ii = T::isR800() ? muluw_hl_SS<BC>() : nop(); NEXT; }
1653  case 0xf3: { II ii = T::isR800() ? muluw_hl_SS<SP>() : nop(); NEXT; }
1654  default: UNREACHABLE; return;
1655  }
1656 }
1657 opDD_2:
1658 CASE(DD) {
1659  setPC(getPC() + 1); // M1 cycle at this point
1660  byte opcodeDD = RDMEM_OPCODE<0>(T::CC_DD + T::CC_MAIN);
1661  incR(1);
1662  switch (opcodeDD) {
1663  case 0x00: // nop();
1664  case 0x01: // ld_bc_word();
1665  case 0x02: // ld_xbc_a();
1666  case 0x03: // inc_bc();
1667  case 0x04: // inc_b();
1668  case 0x05: // dec_b();
1669  case 0x06: // ld_b_byte();
1670  case 0x07: // rlca();
1671  case 0x08: // ex_af_af();
1672  case 0x0a: // ld_a_xbc();
1673  case 0x0b: // dec_bc();
1674  case 0x0c: // inc_c();
1675  case 0x0d: // dec_c();
1676  case 0x0e: // ld_c_byte();
1677  case 0x0f: // rrca();
1678  case 0x10: // djnz();
1679  case 0x11: // ld_de_word();
1680  case 0x12: // ld_xde_a();
1681  case 0x13: // inc_de();
1682  case 0x14: // inc_d();
1683  case 0x15: // dec_d();
1684  case 0x16: // ld_d_byte();
1685  case 0x17: // rla();
1686  case 0x18: // jr();
1687  case 0x1a: // ld_a_xde();
1688  case 0x1b: // dec_de();
1689  case 0x1c: // inc_e();
1690  case 0x1d: // dec_e();
1691  case 0x1e: // ld_e_byte();
1692  case 0x1f: // rra();
1693  case 0x20: // jr_nz();
1694  case 0x27: // daa();
1695  case 0x28: // jr_z();
1696  case 0x2f: // cpl();
1697  case 0x30: // jr_nc();
1698  case 0x31: // ld_sp_word();
1699  case 0x32: // ld_xbyte_a();
1700  case 0x33: // inc_sp();
1701  case 0x37: // scf();
1702  case 0x38: // jr_c();
1703  case 0x3a: // ld_a_xbyte();
1704  case 0x3b: // dec_sp();
1705  case 0x3c: // inc_a();
1706  case 0x3d: // dec_a();
1707  case 0x3e: // ld_a_byte();
1708  case 0x3f: // ccf();
1709 
1710  case 0x40: // ld_b_b();
1711  case 0x41: // ld_b_c();
1712  case 0x42: // ld_b_d();
1713  case 0x43: // ld_b_e();
1714  case 0x47: // ld_b_a();
1715  case 0x48: // ld_c_b();
1716  case 0x49: // ld_c_c();
1717  case 0x4a: // ld_c_d();
1718  case 0x4b: // ld_c_e();
1719  case 0x4f: // ld_c_a();
1720  case 0x50: // ld_d_b();
1721  case 0x51: // ld_d_c();
1722  case 0x52: // ld_d_d();
1723  case 0x53: // ld_d_e();
1724  case 0x57: // ld_d_a();
1725  case 0x58: // ld_e_b();
1726  case 0x59: // ld_e_c();
1727  case 0x5a: // ld_e_d();
1728  case 0x5b: // ld_e_e();
1729  case 0x5f: // ld_e_a();
1730  case 0x64: // ld_ixh_ixh(); == nop
1731  case 0x6d: // ld_ixl_ixl(); == nop
1732  case 0x76: // halt();
1733  case 0x78: // ld_a_b();
1734  case 0x79: // ld_a_c();
1735  case 0x7a: // ld_a_d();
1736  case 0x7b: // ld_a_e();
1737  case 0x7f: // ld_a_a();
1738 
1739  case 0x80: // add_a_b();
1740  case 0x81: // add_a_c();
1741  case 0x82: // add_a_d();
1742  case 0x83: // add_a_e();
1743  case 0x87: // add_a_a();
1744  case 0x88: // adc_a_b();
1745  case 0x89: // adc_a_c();
1746  case 0x8a: // adc_a_d();
1747  case 0x8b: // adc_a_e();
1748  case 0x8f: // adc_a_a();
1749  case 0x90: // sub_b();
1750  case 0x91: // sub_c();
1751  case 0x92: // sub_d();
1752  case 0x93: // sub_e();
1753  case 0x97: // sub_a();
1754  case 0x98: // sbc_a_b();
1755  case 0x99: // sbc_a_c();
1756  case 0x9a: // sbc_a_d();
1757  case 0x9b: // sbc_a_e();
1758  case 0x9f: // sbc_a_a();
1759  case 0xa0: // and_b();
1760  case 0xa1: // and_c();
1761  case 0xa2: // and_d();
1762  case 0xa3: // and_e();
1763  case 0xa7: // and_a();
1764  case 0xa8: // xor_b();
1765  case 0xa9: // xor_c();
1766  case 0xaa: // xor_d();
1767  case 0xab: // xor_e();
1768  case 0xaf: // xor_a();
1769  case 0xb0: // or_b();
1770  case 0xb1: // or_c();
1771  case 0xb2: // or_d();
1772  case 0xb3: // or_e();
1773  case 0xb7: // or_a();
1774  case 0xb8: // cp_b();
1775  case 0xb9: // cp_c();
1776  case 0xba: // cp_d();
1777  case 0xbb: // cp_e();
1778  case 0xbf: // cp_a();
1779 
1780  case 0xc0: // ret_nz();
1781  case 0xc1: // pop_bc();
1782  case 0xc2: // jp_nz();
1783  case 0xc3: // jp();
1784  case 0xc4: // call_nz();
1785  case 0xc5: // push_bc();
1786  case 0xc6: // add_a_byte();
1787  case 0xc7: // rst_00();
1788  case 0xc8: // ret_z();
1789  case 0xc9: // ret();
1790  case 0xca: // jp_z();
1791  case 0xcc: // call_z();
1792  case 0xcd: // call();
1793  case 0xce: // adc_a_byte();
1794  case 0xcf: // rst_08();
1795  case 0xd0: // ret_nc();
1796  case 0xd1: // pop_de();
1797  case 0xd2: // jp_nc();
1798  case 0xd3: // out_byte_a();
1799  case 0xd4: // call_nc();
1800  case 0xd5: // push_de();
1801  case 0xd6: // sub_byte();
1802  case 0xd7: // rst_10();
1803  case 0xd8: // ret_c();
1804  case 0xd9: // exx();
1805  case 0xda: // jp_c();
1806  case 0xdb: // in_a_byte();
1807  case 0xdc: // call_c();
1808  case 0xde: // sbc_a_byte();
1809  case 0xdf: // rst_18();
1810  case 0xe0: // ret_po();
1811  case 0xe2: // jp_po();
1812  case 0xe4: // call_po();
1813  case 0xe6: // and_byte();
1814  case 0xe7: // rst_20();
1815  case 0xe8: // ret_pe();
1816  case 0xea: // jp_pe();
1817  case 0xeb: // ex_de_hl();
1818  case 0xec: // call_pe();
1819  case 0xed: // ed();
1820  case 0xee: // xor_byte();
1821  case 0xef: // rst_28();
1822  case 0xf0: // ret_p();
1823  case 0xf1: // pop_af();
1824  case 0xf2: // jp_p();
1825  case 0xf3: // di();
1826  case 0xf4: // call_p();
1827  case 0xf5: // push_af();
1828  case 0xf6: // or_byte();
1829  case 0xf7: // rst_30();
1830  case 0xf8: // ret_m();
1831  case 0xfa: // jp_m();
1832  case 0xfb: // ei();
1833  case 0xfc: // call_m();
1834  case 0xfe: // cp_byte();
1835  case 0xff: // rst_38();
1836  if (T::isR800()) {
1837  II ii = nop();
1838  ii.cycles += T::CC_DD;
1839  NEXT;
1840  } else {
1841  T::add(T::CC_DD);
1842  #ifdef USE_COMPUTED_GOTO
1843  goto *(opcodeTable[opcodeDD]);
1844  #else
1845  opcodeMain = opcodeDD;
1846  goto switchopcode;
1847  #endif
1848  }
1849 
1850  case 0x09: { II ii = add_SS_TT<IX,BC,T::CC_DD>(); NEXT; }
1851  case 0x19: { II ii = add_SS_TT<IX,DE,T::CC_DD>(); NEXT; }
1852  case 0x29: { II ii = add_SS_SS<IX ,T::CC_DD>(); NEXT; }
1853  case 0x39: { II ii = add_SS_TT<IX,SP,T::CC_DD>(); NEXT; }
1854  case 0x21: { II ii = ld_SS_word<IX,T::CC_DD>(); NEXT; }
1855  case 0x22: { II ii = ld_xword_SS<IX,T::CC_DD>(); NEXT; }
1856  case 0x2a: { II ii = ld_SS_xword<IX,T::CC_DD>(); NEXT; }
1857  case 0x23: { II ii = inc_SS<IX,T::CC_DD>(); NEXT; }
1858  case 0x2b: { II ii = dec_SS<IX,T::CC_DD>(); NEXT; }
1859  case 0x24: { II ii = inc_R<IXH,T::CC_DD>(); NEXT; }
1860  case 0x2c: { II ii = inc_R<IXL,T::CC_DD>(); NEXT; }
1861  case 0x25: { II ii = dec_R<IXH,T::CC_DD>(); NEXT; }
1862  case 0x2d: { II ii = dec_R<IXL,T::CC_DD>(); NEXT; }
1863  case 0x26: { II ii = ld_R_byte<IXH,T::CC_DD>(); NEXT; }
1864  case 0x2e: { II ii = ld_R_byte<IXL,T::CC_DD>(); NEXT; }
1865  case 0x34: { II ii = inc_xix<IX>(); NEXT; }
1866  case 0x35: { II ii = dec_xix<IX>(); NEXT; }
1867  case 0x36: { II ii = ld_xix_byte<IX>(); NEXT; }
1868 
1869  case 0x44: { II ii = ld_R_R<B,IXH,T::CC_DD>(); NEXT; }
1870  case 0x45: { II ii = ld_R_R<B,IXL,T::CC_DD>(); NEXT; }
1871  case 0x4c: { II ii = ld_R_R<C,IXH,T::CC_DD>(); NEXT; }
1872  case 0x4d: { II ii = ld_R_R<C,IXL,T::CC_DD>(); NEXT; }
1873  case 0x54: { II ii = ld_R_R<D,IXH,T::CC_DD>(); NEXT; }
1874  case 0x55: { II ii = ld_R_R<D,IXL,T::CC_DD>(); NEXT; }
1875  case 0x5c: { II ii = ld_R_R<E,IXH,T::CC_DD>(); NEXT; }
1876  case 0x5d: { II ii = ld_R_R<E,IXL,T::CC_DD>(); NEXT; }
1877  case 0x7c: { II ii = ld_R_R<A,IXH,T::CC_DD>(); NEXT; }
1878  case 0x7d: { II ii = ld_R_R<A,IXL,T::CC_DD>(); NEXT; }
1879  case 0x60: { II ii = ld_R_R<IXH,B,T::CC_DD>(); NEXT; }
1880  case 0x61: { II ii = ld_R_R<IXH,C,T::CC_DD>(); NEXT; }
1881  case 0x62: { II ii = ld_R_R<IXH,D,T::CC_DD>(); NEXT; }
1882  case 0x63: { II ii = ld_R_R<IXH,E,T::CC_DD>(); NEXT; }
1883  case 0x65: { II ii = ld_R_R<IXH,IXL,T::CC_DD>(); NEXT; }
1884  case 0x67: { II ii = ld_R_R<IXH,A,T::CC_DD>(); NEXT; }
1885  case 0x68: { II ii = ld_R_R<IXL,B,T::CC_DD>(); NEXT; }
1886  case 0x69: { II ii = ld_R_R<IXL,C,T::CC_DD>(); NEXT; }
1887  case 0x6a: { II ii = ld_R_R<IXL,D,T::CC_DD>(); NEXT; }
1888  case 0x6b: { II ii = ld_R_R<IXL,E,T::CC_DD>(); NEXT; }
1889  case 0x6c: { II ii = ld_R_R<IXL,IXH,T::CC_DD>(); NEXT; }
1890  case 0x6f: { II ii = ld_R_R<IXL,A,T::CC_DD>(); NEXT; }
1891  case 0x70: { II ii = ld_xix_R<IX,B>(); NEXT; }
1892  case 0x71: { II ii = ld_xix_R<IX,C>(); NEXT; }
1893  case 0x72: { II ii = ld_xix_R<IX,D>(); NEXT; }
1894  case 0x73: { II ii = ld_xix_R<IX,E>(); NEXT; }
1895  case 0x74: { II ii = ld_xix_R<IX,H>(); NEXT; }
1896  case 0x75: { II ii = ld_xix_R<IX,L>(); NEXT; }
1897  case 0x77: { II ii = ld_xix_R<IX,A>(); NEXT; }
1898  case 0x46: { II ii = ld_R_xix<B,IX>(); NEXT; }
1899  case 0x4e: { II ii = ld_R_xix<C,IX>(); NEXT; }
1900  case 0x56: { II ii = ld_R_xix<D,IX>(); NEXT; }
1901  case 0x5e: { II ii = ld_R_xix<E,IX>(); NEXT; }
1902  case 0x66: { II ii = ld_R_xix<H,IX>(); NEXT; }
1903  case 0x6e: { II ii = ld_R_xix<L,IX>(); NEXT; }
1904  case 0x7e: { II ii = ld_R_xix<A,IX>(); NEXT; }
1905 
1906  case 0x84: { II ii = add_a_R<IXH,T::CC_DD>(); NEXT; }
1907  case 0x85: { II ii = add_a_R<IXL,T::CC_DD>(); NEXT; }
1908  case 0x86: { II ii = add_a_xix<IX>(); NEXT; }
1909  case 0x8c: { II ii = adc_a_R<IXH,T::CC_DD>(); NEXT; }
1910  case 0x8d: { II ii = adc_a_R<IXL,T::CC_DD>(); NEXT; }
1911  case 0x8e: { II ii = adc_a_xix<IX>(); NEXT; }
1912  case 0x94: { II ii = sub_R<IXH,T::CC_DD>(); NEXT; }
1913  case 0x95: { II ii = sub_R<IXL,T::CC_DD>(); NEXT; }
1914  case 0x96: { II ii = sub_xix<IX>(); NEXT; }
1915  case 0x9c: { II ii = sbc_a_R<IXH,T::CC_DD>(); NEXT; }
1916  case 0x9d: { II ii = sbc_a_R<IXL,T::CC_DD>(); NEXT; }
1917  case 0x9e: { II ii = sbc_a_xix<IX>(); NEXT; }
1918  case 0xa4: { II ii = and_R<IXH,T::CC_DD>(); NEXT; }
1919  case 0xa5: { II ii = and_R<IXL,T::CC_DD>(); NEXT; }
1920  case 0xa6: { II ii = and_xix<IX>(); NEXT; }
1921  case 0xac: { II ii = xor_R<IXH,T::CC_DD>(); NEXT; }
1922  case 0xad: { II ii = xor_R<IXL,T::CC_DD>(); NEXT; }
1923  case 0xae: { II ii = xor_xix<IX>(); NEXT; }
1924  case 0xb4: { II ii = or_R<IXH,T::CC_DD>(); NEXT; }
1925  case 0xb5: { II ii = or_R<IXL,T::CC_DD>(); NEXT; }
1926  case 0xb6: { II ii = or_xix<IX>(); NEXT; }
1927  case 0xbc: { II ii = cp_R<IXH,T::CC_DD>(); NEXT; }
1928  case 0xbd: { II ii = cp_R<IXL,T::CC_DD>(); NEXT; }
1929  case 0xbe: { II ii = cp_xix<IX>(); NEXT; }
1930 
1931  case 0xe1: { II ii = pop_SS <IX,T::CC_DD>(); NEXT; }
1932  case 0xe5: { II ii = push_SS<IX,T::CC_DD>(); NEXT; }
1933  case 0xe3: { II ii = ex_xsp_SS<IX,T::CC_DD>(); NEXT; }
1934  case 0xe9: { II ii = jp_SS<IX,T::CC_DD>(); NEXT; }
1935  case 0xf9: { II ii = ld_sp_SS<IX,T::CC_DD>(); NEXT; }
1936  case 0xcb: ixy = getIX(); goto xx_cb;
1937  case 0xdd: T::add(T::CC_DD); goto opDD_2;
1938  case 0xfd: T::add(T::CC_DD); goto opFD_2;
1939  default: UNREACHABLE; return;
1940  }
1941 }
1942 opFD_2:
1943 CASE(FD) {
1944  setPC(getPC() + 1); // M1 cycle at this point
1945  byte opcodeFD = RDMEM_OPCODE<0>(T::CC_DD + T::CC_MAIN);
1946  incR(1);
1947  switch (opcodeFD) {
1948  case 0x00: // nop();
1949  case 0x01: // ld_bc_word();
1950  case 0x02: // ld_xbc_a();
1951  case 0x03: // inc_bc();
1952  case 0x04: // inc_b();
1953  case 0x05: // dec_b();
1954  case 0x06: // ld_b_byte();
1955  case 0x07: // rlca();
1956  case 0x08: // ex_af_af();
1957  case 0x0a: // ld_a_xbc();
1958  case 0x0b: // dec_bc();
1959  case 0x0c: // inc_c();
1960  case 0x0d: // dec_c();
1961  case 0x0e: // ld_c_byte();
1962  case 0x0f: // rrca();
1963  case 0x10: // djnz();
1964  case 0x11: // ld_de_word();
1965  case 0x12: // ld_xde_a();
1966  case 0x13: // inc_de();
1967  case 0x14: // inc_d();
1968  case 0x15: // dec_d();
1969  case 0x16: // ld_d_byte();
1970  case 0x17: // rla();
1971  case 0x18: // jr();
1972  case 0x1a: // ld_a_xde();
1973  case 0x1b: // dec_de();
1974  case 0x1c: // inc_e();
1975  case 0x1d: // dec_e();
1976  case 0x1e: // ld_e_byte();
1977  case 0x1f: // rra();
1978  case 0x20: // jr_nz();
1979  case 0x27: // daa();
1980  case 0x28: // jr_z();
1981  case 0x2f: // cpl();
1982  case 0x30: // jr_nc();
1983  case 0x31: // ld_sp_word();
1984  case 0x32: // ld_xbyte_a();
1985  case 0x33: // inc_sp();
1986  case 0x37: // scf();
1987  case 0x38: // jr_c();
1988  case 0x3a: // ld_a_xbyte();
1989  case 0x3b: // dec_sp();
1990  case 0x3c: // inc_a();
1991  case 0x3d: // dec_a();
1992  case 0x3e: // ld_a_byte();
1993  case 0x3f: // ccf();
1994 
1995  case 0x40: // ld_b_b();
1996  case 0x41: // ld_b_c();
1997  case 0x42: // ld_b_d();
1998  case 0x43: // ld_b_e();
1999  case 0x47: // ld_b_a();
2000  case 0x48: // ld_c_b();
2001  case 0x49: // ld_c_c();
2002  case 0x4a: // ld_c_d();
2003  case 0x4b: // ld_c_e();
2004  case 0x4f: // ld_c_a();
2005  case 0x50: // ld_d_b();
2006  case 0x51: // ld_d_c();
2007  case 0x52: // ld_d_d();
2008  case 0x53: // ld_d_e();
2009  case 0x57: // ld_d_a();
2010  case 0x58: // ld_e_b();
2011  case 0x59: // ld_e_c();
2012  case 0x5a: // ld_e_d();
2013  case 0x5b: // ld_e_e();
2014  case 0x5f: // ld_e_a();
2015  case 0x64: // ld_ixh_ixh(); == nop
2016  case 0x6d: // ld_ixl_ixl(); == nop
2017  case 0x76: // halt();
2018  case 0x78: // ld_a_b();
2019  case 0x79: // ld_a_c();
2020  case 0x7a: // ld_a_d();
2021  case 0x7b: // ld_a_e();
2022  case 0x7f: // ld_a_a();
2023 
2024  case 0x80: // add_a_b();
2025  case 0x81: // add_a_c();
2026  case 0x82: // add_a_d();
2027  case 0x83: // add_a_e();
2028  case 0x87: // add_a_a();
2029  case 0x88: // adc_a_b();
2030  case 0x89: // adc_a_c();
2031  case 0x8a: // adc_a_d();
2032  case 0x8b: // adc_a_e();
2033  case 0x8f: // adc_a_a();
2034  case 0x90: // sub_b();
2035  case 0x91: // sub_c();
2036  case 0x92: // sub_d();
2037  case 0x93: // sub_e();
2038  case 0x97: // sub_a();
2039  case 0x98: // sbc_a_b();
2040  case 0x99: // sbc_a_c();
2041  case 0x9a: // sbc_a_d();
2042  case 0x9b: // sbc_a_e();
2043  case 0x9f: // sbc_a_a();
2044  case 0xa0: // and_b();
2045  case 0xa1: // and_c();
2046  case 0xa2: // and_d();
2047  case 0xa3: // and_e();
2048  case 0xa7: // and_a();
2049  case 0xa8: // xor_b();
2050  case 0xa9: // xor_c();
2051  case 0xaa: // xor_d();
2052  case 0xab: // xor_e();
2053  case 0xaf: // xor_a();
2054  case 0xb0: // or_b();
2055  case 0xb1: // or_c();
2056  case 0xb2: // or_d();
2057  case 0xb3: // or_e();
2058  case 0xb7: // or_a();
2059  case 0xb8: // cp_b();
2060  case 0xb9: // cp_c();
2061  case 0xba: // cp_d();
2062  case 0xbb: // cp_e();
2063  case 0xbf: // cp_a();
2064 
2065  case 0xc0: // ret_nz();
2066  case 0xc1: // pop_bc();
2067  case 0xc2: // jp_nz();
2068  case 0xc3: // jp();
2069  case 0xc4: // call_nz();
2070  case 0xc5: // push_bc();
2071  case 0xc6: // add_a_byte();
2072  case 0xc7: // rst_00();
2073  case 0xc8: // ret_z();
2074  case 0xc9: // ret();
2075  case 0xca: // jp_z();
2076  case 0xcc: // call_z();
2077  case 0xcd: // call();
2078  case 0xce: // adc_a_byte();
2079  case 0xcf: // rst_08();
2080  case 0xd0: // ret_nc();
2081  case 0xd1: // pop_de();
2082  case 0xd2: // jp_nc();
2083  case 0xd3: // out_byte_a();
2084  case 0xd4: // call_nc();
2085  case 0xd5: // push_de();
2086  case 0xd6: // sub_byte();
2087  case 0xd7: // rst_10();
2088  case 0xd8: // ret_c();
2089  case 0xd9: // exx();
2090  case 0xda: // jp_c();
2091  case 0xdb: // in_a_byte();
2092  case 0xdc: // call_c();
2093  case 0xde: // sbc_a_byte();
2094  case 0xdf: // rst_18();
2095  case 0xe0: // ret_po();
2096  case 0xe2: // jp_po();
2097  case 0xe4: // call_po();
2098  case 0xe6: // and_byte();
2099  case 0xe7: // rst_20();
2100  case 0xe8: // ret_pe();
2101  case 0xea: // jp_pe();
2102  case 0xeb: // ex_de_hl();
2103  case 0xec: // call_pe();
2104  case 0xed: // ed();
2105  case 0xee: // xor_byte();
2106  case 0xef: // rst_28();
2107  case 0xf0: // ret_p();
2108  case 0xf1: // pop_af();
2109  case 0xf2: // jp_p();
2110  case 0xf3: // di();
2111  case 0xf4: // call_p();
2112  case 0xf5: // push_af();
2113  case 0xf6: // or_byte();
2114  case 0xf7: // rst_30();
2115  case 0xf8: // ret_m();
2116  case 0xfa: // jp_m();
2117  case 0xfb: // ei();
2118  case 0xfc: // call_m();
2119  case 0xfe: // cp_byte();
2120  case 0xff: // rst_38();
2121  if (T::isR800()) {
2122  II ii = nop();
2123  ii.cycles += T::CC_DD;
2124  NEXT;
2125  } else {
2126  T::add(T::CC_DD);
2127  #ifdef USE_COMPUTED_GOTO
2128  goto *(opcodeTable[opcodeFD]);
2129  #else
2130  opcodeMain = opcodeFD;
2131  goto switchopcode;
2132  #endif
2133  }
2134 
2135  case 0x09: { II ii = add_SS_TT<IY,BC,T::CC_DD>(); NEXT; }
2136  case 0x19: { II ii = add_SS_TT<IY,DE,T::CC_DD>(); NEXT; }
2137  case 0x29: { II ii = add_SS_SS<IY ,T::CC_DD>(); NEXT; }
2138  case 0x39: { II ii = add_SS_TT<IY,SP,T::CC_DD>(); NEXT; }
2139  case 0x21: { II ii = ld_SS_word<IY,T::CC_DD>(); NEXT; }
2140  case 0x22: { II ii = ld_xword_SS<IY,T::CC_DD>(); NEXT; }
2141  case 0x2a: { II ii = ld_SS_xword<IY,T::CC_DD>(); NEXT; }
2142  case 0x23: { II ii = inc_SS<IY,T::CC_DD>(); NEXT; }
2143  case 0x2b: { II ii = dec_SS<IY,T::CC_DD>(); NEXT; }
2144  case 0x24: { II ii = inc_R<IYH,T::CC_DD>(); NEXT; }
2145  case 0x2c: { II ii = inc_R<IYL,T::CC_DD>(); NEXT; }
2146  case 0x25: { II ii = dec_R<IYH,T::CC_DD>(); NEXT; }
2147  case 0x2d: { II ii = dec_R<IYL,T::CC_DD>(); NEXT; }
2148  case 0x26: { II ii = ld_R_byte<IYH,T::CC_DD>(); NEXT; }
2149  case 0x2e: { II ii = ld_R_byte<IYL,T::CC_DD>(); NEXT; }
2150  case 0x34: { II ii = inc_xix<IY>(); NEXT; }
2151  case 0x35: { II ii = dec_xix<IY>(); NEXT; }
2152  case 0x36: { II ii = ld_xix_byte<IY>(); NEXT; }
2153 
2154  case 0x44: { II ii = ld_R_R<B,IYH,T::CC_DD>(); NEXT; }
2155  case 0x45: { II ii = ld_R_R<B,IYL,T::CC_DD>(); NEXT; }
2156  case 0x4c: { II ii = ld_R_R<C,IYH,T::CC_DD>(); NEXT; }
2157  case 0x4d: { II ii = ld_R_R<C,IYL,T::CC_DD>(); NEXT; }
2158  case 0x54: { II ii = ld_R_R<D,IYH,T::CC_DD>(); NEXT; }
2159  case 0x55: { II ii = ld_R_R<D,IYL,T::CC_DD>(); NEXT; }
2160  case 0x5c: { II ii = ld_R_R<E,IYH,T::CC_DD>(); NEXT; }
2161  case 0x5d: { II ii = ld_R_R<E,IYL,T::CC_DD>(); NEXT; }
2162  case 0x7c: { II ii = ld_R_R<A,IYH,T::CC_DD>(); NEXT; }
2163  case 0x7d: { II ii = ld_R_R<A,IYL,T::CC_DD>(); NEXT; }
2164  case 0x60: { II ii = ld_R_R<IYH,B,T::CC_DD>(); NEXT; }
2165  case 0x61: { II ii = ld_R_R<IYH,C,T::CC_DD>(); NEXT; }
2166  case 0x62: { II ii = ld_R_R<IYH,D,T::CC_DD>(); NEXT; }
2167  case 0x63: { II ii = ld_R_R<IYH,E,T::CC_DD>(); NEXT; }
2168  case 0x65: { II ii = ld_R_R<IYH,IYL,T::CC_DD>(); NEXT; }
2169  case 0x67: { II ii = ld_R_R<IYH,A,T::CC_DD>(); NEXT; }
2170  case 0x68: { II ii = ld_R_R<IYL,B,T::CC_DD>(); NEXT; }
2171  case 0x69: { II ii = ld_R_R<IYL,C,T::CC_DD>(); NEXT; }
2172  case 0x6a: { II ii = ld_R_R<IYL,D,T::CC_DD>(); NEXT; }
2173  case 0x6b: { II ii = ld_R_R<IYL,E,T::CC_DD>(); NEXT; }
2174  case 0x6c: { II ii = ld_R_R<IYL,IYH,T::CC_DD>(); NEXT; }
2175  case 0x6f: { II ii = ld_R_R<IYL,A,T::CC_DD>(); NEXT; }
2176  case 0x70: { II ii = ld_xix_R<IY,B>(); NEXT; }
2177  case 0x71: { II ii = ld_xix_R<IY,C>(); NEXT; }
2178  case 0x72: { II ii = ld_xix_R<IY,D>(); NEXT; }
2179  case 0x73: { II ii = ld_xix_R<IY,E>(); NEXT; }
2180  case 0x74: { II ii = ld_xix_R<IY,H>(); NEXT; }
2181  case 0x75: { II ii = ld_xix_R<IY,L>(); NEXT; }
2182  case 0x77: { II ii = ld_xix_R<IY,A>(); NEXT; }
2183  case 0x46: { II ii = ld_R_xix<B,IY>(); NEXT; }
2184  case 0x4e: { II ii = ld_R_xix<C,IY>(); NEXT; }
2185  case 0x56: { II ii = ld_R_xix<D,IY>(); NEXT; }
2186  case 0x5e: { II ii = ld_R_xix<E,IY>(); NEXT; }
2187  case 0x66: { II ii = ld_R_xix<H,IY>(); NEXT; }
2188  case 0x6e: { II ii = ld_R_xix<L,IY>(); NEXT; }
2189  case 0x7e: { II ii = ld_R_xix<A,IY>(); NEXT; }
2190 
2191  case 0x84: { II ii = add_a_R<IYH,T::CC_DD>(); NEXT; }
2192  case 0x85: { II ii = add_a_R<IYL,T::CC_DD>(); NEXT; }
2193  case 0x86: { II ii = add_a_xix<IY>(); NEXT; }
2194  case 0x8c: { II ii = adc_a_R<IYH,T::CC_DD>(); NEXT; }
2195  case 0x8d: { II ii = adc_a_R<IYL,T::CC_DD>(); NEXT; }
2196  case 0x8e: { II ii = adc_a_xix<IY>(); NEXT; }
2197  case 0x94: { II ii = sub_R<IYH,T::CC_DD>(); NEXT; }
2198  case 0x95: { II ii = sub_R<IYL,T::CC_DD>(); NEXT; }
2199  case 0x96: { II ii = sub_xix<IY>(); NEXT; }
2200  case 0x9c: { II ii = sbc_a_R<IYH,T::CC_DD>(); NEXT; }
2201  case 0x9d: { II ii = sbc_a_R<IYL,T::CC_DD>(); NEXT; }
2202  case 0x9e: { II ii = sbc_a_xix<IY>(); NEXT; }
2203  case 0xa4: { II ii = and_R<IYH,T::CC_DD>(); NEXT; }
2204  case 0xa5: { II ii = and_R<IYL,T::CC_DD>(); NEXT; }
2205  case 0xa6: { II ii = and_xix<IY>(); NEXT; }
2206  case 0xac: { II ii = xor_R<IYH,T::CC_DD>(); NEXT; }
2207  case 0xad: { II ii = xor_R<IYL,T::CC_DD>(); NEXT; }
2208  case 0xae: { II ii = xor_xix<IY>(); NEXT; }
2209  case 0xb4: { II ii = or_R<IYH,T::CC_DD>(); NEXT; }
2210  case 0xb5: { II ii = or_R<IYL,T::CC_DD>(); NEXT; }
2211  case 0xb6: { II ii = or_xix<IY>(); NEXT; }
2212  case 0xbc: { II ii = cp_R<IYH,T::CC_DD>(); NEXT; }
2213  case 0xbd: { II ii = cp_R<IYL,T::CC_DD>(); NEXT; }
2214  case 0xbe: { II ii = cp_xix<IY>(); NEXT; }
2215 
2216  case 0xe1: { II ii = pop_SS <IY,T::CC_DD>(); NEXT; }
2217  case 0xe5: { II ii = push_SS<IY,T::CC_DD>(); NEXT; }
2218  case 0xe3: { II ii = ex_xsp_SS<IY,T::CC_DD>(); NEXT; }
2219  case 0xe9: { II ii = jp_SS<IY,T::CC_DD>(); NEXT; }
2220  case 0xf9: { II ii = ld_sp_SS<IY,T::CC_DD>(); NEXT; }
2221  case 0xcb: ixy = getIY(); goto xx_cb;
2222  case 0xdd: T::add(T::CC_DD); goto opDD_2;
2223  case 0xfd: T::add(T::CC_DD); goto opFD_2;
2224  default: UNREACHABLE; return;
2225  }
2226 }
2227 #ifndef USE_COMPUTED_GOTO
2228  default: UNREACHABLE; return;
2229 }
2230 #endif
2231 
2232 xx_cb: {
2233  unsigned tmp = RD_WORD_PC<1>(T::CC_DD + T::CC_DD_CB);
2234  int8_t ofst = tmp & 0xFF;
2235  unsigned addr = (ixy + ofst) & 0xFFFF;
2236  byte xxcb_opcode = tmp >> 8;
2237  switch (xxcb_opcode) {
2238  case 0x00: { II ii = rlc_xix_R<B>(addr); NEXT; }
2239  case 0x01: { II ii = rlc_xix_R<C>(addr); NEXT; }
2240  case 0x02: { II ii = rlc_xix_R<D>(addr); NEXT; }
2241  case 0x03: { II ii = rlc_xix_R<E>(addr); NEXT; }
2242  case 0x04: { II ii = rlc_xix_R<H>(addr); NEXT; }
2243  case 0x05: { II ii = rlc_xix_R<L>(addr); NEXT; }
2244  case 0x06: { II ii = rlc_xix_R<DUMMY>(addr); NEXT; }
2245  case 0x07: { II ii = rlc_xix_R<A>(addr); NEXT; }
2246  case 0x08: { II ii = rrc_xix_R<B>(addr); NEXT; }
2247  case 0x09: { II ii = rrc_xix_R<C>(addr); NEXT; }
2248  case 0x0a: { II ii = rrc_xix_R<D>(addr); NEXT; }
2249  case 0x0b: { II ii = rrc_xix_R<E>(addr); NEXT; }
2250  case 0x0c: { II ii = rrc_xix_R<H>(addr); NEXT; }
2251  case 0x0d: { II ii = rrc_xix_R<L>(addr); NEXT; }
2252  case 0x0e: { II ii = rrc_xix_R<DUMMY>(addr); NEXT; }
2253  case 0x0f: { II ii = rrc_xix_R<A>(addr); NEXT; }
2254  case 0x10: { II ii = rl_xix_R<B>(addr); NEXT; }
2255  case 0x11: { II ii = rl_xix_R<C>(addr); NEXT; }
2256  case 0x12: { II ii = rl_xix_R<D>(addr); NEXT; }
2257  case 0x13: { II ii = rl_xix_R<E>(addr); NEXT; }
2258  case 0x14: { II ii = rl_xix_R<H>(addr); NEXT; }
2259  case 0x15: { II ii = rl_xix_R<L>(addr); NEXT; }
2260  case 0x16: { II ii = rl_xix_R<DUMMY>(addr); NEXT; }
2261  case 0x17: { II ii = rl_xix_R<A>(addr); NEXT; }
2262  case 0x18: { II ii = rr_xix_R<B>(addr); NEXT; }
2263  case 0x19: { II ii = rr_xix_R<C>(addr); NEXT; }
2264  case 0x1a: { II ii = rr_xix_R<D>(addr); NEXT; }
2265  case 0x1b: { II ii = rr_xix_R<E>(addr); NEXT; }
2266  case 0x1c: { II ii = rr_xix_R<H>(addr); NEXT; }
2267  case 0x1d: { II ii = rr_xix_R<L>(addr); NEXT; }
2268  case 0x1e: { II ii = rr_xix_R<DUMMY>(addr); NEXT; }
2269  case 0x1f: { II ii = rr_xix_R<A>(addr); NEXT; }
2270  case 0x20: { II ii = sla_xix_R<B>(addr); NEXT; }
2271  case 0x21: { II ii = sla_xix_R<C>(addr); NEXT; }
2272  case 0x22: { II ii = sla_xix_R<D>(addr); NEXT; }
2273  case 0x23: { II ii = sla_xix_R<E>(addr); NEXT; }
2274  case 0x24: { II ii = sla_xix_R<H>(addr); NEXT; }
2275  case 0x25: { II ii = sla_xix_R<L>(addr); NEXT; }
2276  case 0x26: { II ii = sla_xix_R<DUMMY>(addr); NEXT; }
2277  case 0x27: { II ii = sla_xix_R<A>(addr); NEXT; }
2278  case 0x28: { II ii = sra_xix_R<B>(addr); NEXT; }
2279  case 0x29: { II ii = sra_xix_R<C>(addr); NEXT; }
2280  case 0x2a: { II ii = sra_xix_R<D>(addr); NEXT; }
2281  case 0x2b: { II ii = sra_xix_R<E>(addr); NEXT; }
2282  case 0x2c: { II ii = sra_xix_R<H>(addr); NEXT; }
2283  case 0x2d: { II ii = sra_xix_R<L>(addr); NEXT; }
2284  case 0x2e: { II ii = sra_xix_R<DUMMY>(addr); NEXT; }
2285  case 0x2f: { II ii = sra_xix_R<A>(addr); NEXT; }
2286  case 0x30: { II ii = T::isR800() ? sll2() : sll_xix_R<B>(addr); NEXT; }
2287  case 0x31: { II ii = T::isR800() ? sll2() : sll_xix_R<C>(addr); NEXT; }
2288  case 0x32: { II ii = T::isR800() ? sll2() : sll_xix_R<D>(addr); NEXT; }
2289  case 0x33: { II ii = T::isR800() ? sll2() : sll_xix_R<E>(addr); NEXT; }
2290  case 0x34: { II ii = T::isR800() ? sll2() : sll_xix_R<H>(addr); NEXT; }
2291  case 0x35: { II ii = T::isR800() ? sll2() : sll_xix_R<L>(addr); NEXT; }
2292  case 0x36: { II ii = T::isR800() ? sll2() : sll_xix_R<DUMMY>(addr); NEXT; }
2293  case 0x37: { II ii = T::isR800() ? sll2() : sll_xix_R<A>(addr); NEXT; }
2294  case 0x38: { II ii = srl_xix_R<B>(addr); NEXT; }
2295  case 0x39: { II ii = srl_xix_R<C>(addr); NEXT; }
2296  case 0x3a: { II ii = srl_xix_R<D>(addr); NEXT; }
2297  case 0x3b: { II ii = srl_xix_R<E>(addr); NEXT; }
2298  case 0x3c: { II ii = srl_xix_R<H>(addr); NEXT; }
2299  case 0x3d: { II ii = srl_xix_R<L>(addr); NEXT; }
2300  case 0x3e: { II ii = srl_xix_R<DUMMY>(addr); NEXT; }
2301  case 0x3f: { II ii = srl_xix_R<A>(addr); NEXT; }
2302 
2303  case 0x40: case 0x41: case 0x42: case 0x43:
2304  case 0x44: case 0x45: case 0x46: case 0x47:
2305  { II ii = bit_N_xix<0>(addr); NEXT; }
2306  case 0x48: case 0x49: case 0x4a: case 0x4b:
2307  case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2308  { II ii = bit_N_xix<1>(addr); NEXT; }
2309  case 0x50: case 0x51: case 0x52: case 0x53:
2310  case 0x54: case 0x55: case 0x56: case 0x57:
2311  { II ii = bit_N_xix<2>(addr); NEXT; }
2312  case 0x58: case 0x59: case 0x5a: case 0x5b:
2313  case 0x5c: case 0x5d: case 0x5e: case 0x5f:
2314  { II ii = bit_N_xix<3>(addr); NEXT; }
2315  case 0x60: case 0x61: case 0x62: case 0x63:
2316  case 0x64: case 0x65: case 0x66: case 0x67:
2317  { II ii = bit_N_xix<4>(addr); NEXT; }
2318  case 0x68: case 0x69: case 0x6a: case 0x6b:
2319  case 0x6c: case 0x6d: case 0x6e: case 0x6f:
2320  { II ii = bit_N_xix<5>(addr); NEXT; }
2321  case 0x70: case 0x71: case 0x72: case 0x73:
2322  case 0x74: case 0x75: case 0x76: case 0x77:
2323  { II ii = bit_N_xix<6>(addr); NEXT; }
2324  case 0x78: case 0x79: case 0x7a: case 0x7b:
2325  case 0x7c: case 0x7d: case 0x7e: case 0x7f:
2326  { II ii = bit_N_xix<7>(addr); NEXT; }
2327 
2328  case 0x80: { II ii = res_N_xix_R<0,B>(addr); NEXT; }
2329  case 0x81: { II ii = res_N_xix_R<0,C>(addr); NEXT; }
2330  case 0x82: { II ii = res_N_xix_R<0,D>(addr); NEXT; }
2331  case 0x83: { II ii = res_N_xix_R<0,E>(addr); NEXT; }
2332  case 0x84: { II ii = res_N_xix_R<0,H>(addr); NEXT; }
2333  case 0x85: { II ii = res_N_xix_R<0,L>(addr); NEXT; }
2334  case 0x87: { II ii = res_N_xix_R<0,A>(addr); NEXT; }
2335  case 0x88: { II ii = res_N_xix_R<1,B>(addr); NEXT; }
2336  case 0x89: { II ii = res_N_xix_R<1,C>(addr); NEXT; }
2337  case 0x8a: { II ii = res_N_xix_R<1,D>(addr); NEXT; }
2338  case 0x8b: { II ii = res_N_xix_R<1,E>(addr); NEXT; }
2339  case 0x8c: { II ii = res_N_xix_R<1,H>(addr); NEXT; }
2340  case 0x8d: { II ii = res_N_xix_R<1,L>(addr); NEXT; }
2341  case 0x8f: { II ii = res_N_xix_R<1,A>(addr); NEXT; }
2342  case 0x90: { II ii = res_N_xix_R<2,B>(addr); NEXT; }
2343  case 0x91: { II ii = res_N_xix_R<2,C>(addr); NEXT; }
2344  case 0x92: { II ii = res_N_xix_R<2,D>(addr); NEXT; }
2345  case 0x93: { II ii = res_N_xix_R<2,E>(addr); NEXT; }
2346  case 0x94: { II ii = res_N_xix_R<2,H>(addr); NEXT; }
2347  case 0x95: { II ii = res_N_xix_R<2,L>(addr); NEXT; }
2348  case 0x97: { II ii = res_N_xix_R<2,A>(addr); NEXT; }
2349  case 0x98: { II ii = res_N_xix_R<3,B>(addr); NEXT; }
2350  case 0x99: { II ii = res_N_xix_R<3,C>(addr); NEXT; }
2351  case 0x9a: { II ii = res_N_xix_R<3,D>(addr); NEXT; }
2352  case 0x9b: { II ii = res_N_xix_R<3,E>(addr); NEXT; }
2353  case 0x9c: { II ii = res_N_xix_R<3,H>(addr); NEXT; }
2354  case 0x9d: { II ii = res_N_xix_R<3,L>(addr); NEXT; }
2355  case 0x9f: { II ii = res_N_xix_R<3,A>(addr); NEXT; }
2356  case 0xa0: { II ii = res_N_xix_R<4,B>(addr); NEXT; }
2357  case 0xa1: { II ii = res_N_xix_R<4,C>(addr); NEXT; }
2358  case 0xa2: { II ii = res_N_xix_R<4,D>(addr); NEXT; }
2359  case 0xa3: { II ii = res_N_xix_R<4,E>(addr); NEXT; }
2360  case 0xa4: { II ii = res_N_xix_R<4,H>(addr); NEXT; }
2361  case 0xa5: { II ii = res_N_xix_R<4,L>(addr); NEXT; }
2362  case 0xa7: { II ii = res_N_xix_R<4,A>(addr); NEXT; }
2363  case 0xa8: { II ii = res_N_xix_R<5,B>(addr); NEXT; }
2364  case 0xa9: { II ii = res_N_xix_R<5,C>(addr); NEXT; }
2365  case 0xaa: { II ii = res_N_xix_R<5,D>(addr); NEXT; }
2366  case 0xab: { II ii = res_N_xix_R<5,E>(addr); NEXT; }
2367  case 0xac: { II ii = res_N_xix_R<5,H>(addr); NEXT; }
2368  case 0xad: { II ii = res_N_xix_R<5,L>(addr); NEXT; }
2369  case 0xaf: { II ii = res_N_xix_R<5,A>(addr); NEXT; }
2370  case 0xb0: { II ii = res_N_xix_R<6,B>(addr); NEXT; }
2371  case 0xb1: { II ii = res_N_xix_R<6,C>(addr); NEXT; }
2372  case 0xb2: { II ii = res_N_xix_R<6,D>(addr); NEXT; }
2373  case 0xb3: { II ii = res_N_xix_R<6,E>(addr); NEXT; }
2374  case 0xb4: { II ii = res_N_xix_R<6,H>(addr); NEXT; }
2375  case 0xb5: { II ii = res_N_xix_R<6,L>(addr); NEXT; }
2376  case 0xb7: { II ii = res_N_xix_R<6,A>(addr); NEXT; }
2377  case 0xb8: { II ii = res_N_xix_R<7,B>(addr); NEXT; }
2378  case 0xb9: { II ii = res_N_xix_R<7,C>(addr); NEXT; }
2379  case 0xba: { II ii = res_N_xix_R<7,D>(addr); NEXT; }
2380  case 0xbb: { II ii = res_N_xix_R<7,E>(addr); NEXT; }
2381  case 0xbc: { II ii = res_N_xix_R<7,H>(addr); NEXT; }
2382  case 0xbd: { II ii = res_N_xix_R<7,L>(addr); NEXT; }
2383  case 0xbf: { II ii = res_N_xix_R<7,A>(addr); NEXT; }
2384  case 0x86: { II ii = res_N_xix_R<0,DUMMY>(addr); NEXT; }
2385  case 0x8e: { II ii = res_N_xix_R<1,DUMMY>(addr); NEXT; }
2386  case 0x96: { II ii = res_N_xix_R<2,DUMMY>(addr); NEXT; }
2387  case 0x9e: { II ii = res_N_xix_R<3,DUMMY>(addr); NEXT; }
2388  case 0xa6: { II ii = res_N_xix_R<4,DUMMY>(addr); NEXT; }
2389  case 0xae: { II ii = res_N_xix_R<5,DUMMY>(addr); NEXT; }
2390  case 0xb6: { II ii = res_N_xix_R<6,DUMMY>(addr); NEXT; }
2391  case 0xbe: { II ii = res_N_xix_R<7,DUMMY>(addr); NEXT; }
2392 
2393  case 0xc0: { II ii = set_N_xix_R<0,B>(addr); NEXT; }
2394  case 0xc1: { II ii = set_N_xix_R<0,C>(addr); NEXT; }
2395  case 0xc2: { II ii = set_N_xix_R<0,D>(addr); NEXT; }
2396  case 0xc3: { II ii = set_N_xix_R<0,E>(addr); NEXT; }
2397  case 0xc4: { II ii = set_N_xix_R<0,H>(addr); NEXT; }
2398  case 0xc5: { II ii = set_N_xix_R<0,L>(addr); NEXT; }
2399  case 0xc7: { II ii = set_N_xix_R<0,A>(addr); NEXT; }
2400  case 0xc8: { II ii = set_N_xix_R<1,B>(addr); NEXT; }
2401  case 0xc9: { II ii = set_N_xix_R<1,C>(addr); NEXT; }
2402  case 0xca: { II ii = set_N_xix_R<1,D>(addr); NEXT; }
2403  case 0xcb: { II ii = set_N_xix_R<1,E>(addr); NEXT; }
2404  case 0xcc: { II ii = set_N_xix_R<1,H>(addr); NEXT; }
2405  case 0xcd: { II ii = set_N_xix_R<1,L>(addr); NEXT; }
2406  case 0xcf: { II ii = set_N_xix_R<1,A>(addr); NEXT; }
2407  case 0xd0: { II ii = set_N_xix_R<2,B>(addr); NEXT; }
2408  case 0xd1: { II ii = set_N_xix_R<2,C>(addr); NEXT; }
2409  case 0xd2: { II ii = set_N_xix_R<2,D>(addr); NEXT; }
2410  case 0xd3: { II ii = set_N_xix_R<2,E>(addr); NEXT; }
2411  case 0xd4: { II ii = set_N_xix_R<2,H>(addr); NEXT; }
2412  case 0xd5: { II ii = set_N_xix_R<2,L>(addr); NEXT; }
2413  case 0xd7: { II ii = set_N_xix_R<2,A>(addr); NEXT; }
2414  case 0xd8: { II ii = set_N_xix_R<3,B>(addr); NEXT; }
2415  case 0xd9: { II ii = set_N_xix_R<3,C>(addr); NEXT; }
2416  case 0xda: { II ii = set_N_xix_R<3,D>(addr); NEXT; }
2417  case 0xdb: { II ii = set_N_xix_R<3,E>(addr); NEXT; }
2418  case 0xdc: { II ii = set_N_xix_R<3,H>(addr); NEXT; }
2419  case 0xdd: { II ii = set_N_xix_R<3,L>(addr); NEXT; }
2420  case 0xdf: { II ii = set_N_xix_R<3,A>(addr); NEXT; }
2421  case 0xe0: { II ii = set_N_xix_R<4,B>(addr); NEXT; }
2422  case 0xe1: { II ii = set_N_xix_R<4,C>(addr); NEXT; }
2423  case 0xe2: { II ii = set_N_xix_R<4,D>(addr); NEXT; }
2424  case 0xe3: { II ii = set_N_xix_R<4,E>(addr); NEXT; }
2425  case 0xe4: { II ii = set_N_xix_R<4,H>(addr); NEXT; }
2426  case 0xe5: { II ii = set_N_xix_R<4,L>(addr); NEXT; }
2427  case 0xe7: { II ii = set_N_xix_R<4,A>(addr); NEXT; }
2428  case 0xe8: { II ii = set_N_xix_R<5,B>(addr); NEXT; }
2429  case 0xe9: { II ii = set_N_xix_R<5,C>(addr); NEXT; }
2430  case 0xea: { II ii = set_N_xix_R<5,D>(addr); NEXT; }
2431  case 0xeb: { II ii = set_N_xix_R<5,E>(addr); NEXT; }
2432  case 0xec: { II ii = set_N_xix_R<5,H>(addr); NEXT; }
2433  case 0xed: { II ii = set_N_xix_R<5,L>(addr); NEXT; }
2434  case 0xef: { II ii = set_N_xix_R<5,A>(addr); NEXT; }
2435  case 0xf0: { II ii = set_N_xix_R<6,B>(addr); NEXT; }
2436  case 0xf1: { II ii = set_N_xix_R<6,C>(addr); NEXT; }
2437  case 0xf2: { II ii = set_N_xix_R<6,D>(addr); NEXT; }
2438  case 0xf3: { II ii = set_N_xix_R<6,E>(addr); NEXT; }
2439  case 0xf4: { II ii = set_N_xix_R<6,H>(addr); NEXT; }
2440  case 0xf5: { II ii = set_N_xix_R<6,L>(addr); NEXT; }
2441  case 0xf7: { II ii = set_N_xix_R<6,A>(addr); NEXT; }
2442  case 0xf8: { II ii = set_N_xix_R<7,B>(addr); NEXT; }
2443  case 0xf9: { II ii = set_N_xix_R<7,C>(addr); NEXT; }
2444  case 0xfa: { II ii = set_N_xix_R<7,D>(addr); NEXT; }
2445  case 0xfb: { II ii = set_N_xix_R<7,E>(addr); NEXT; }
2446  case 0xfc: { II ii = set_N_xix_R<7,H>(addr); NEXT; }
2447  case 0xfd: { II ii = set_N_xix_R<7,L>(addr); NEXT; }
2448  case 0xff: { II ii = set_N_xix_R<7,A>(addr); NEXT; }
2449  case 0xc6: { II ii = set_N_xix_R<0,DUMMY>(addr); NEXT; }
2450  case 0xce: { II ii = set_N_xix_R<1,DUMMY>(addr); NEXT; }
2451  case 0xd6: { II ii = set_N_xix_R<2,DUMMY>(addr); NEXT; }
2452  case 0xde: { II ii = set_N_xix_R<3,DUMMY>(addr); NEXT; }
2453  case 0xe6: { II ii = set_N_xix_R<4,DUMMY>(addr); NEXT; }
2454  case 0xee: { II ii = set_N_xix_R<5,DUMMY>(addr); NEXT; }
2455  case 0xf6: { II ii = set_N_xix_R<6,DUMMY>(addr); NEXT; }
2456  case 0xfe: { II ii = set_N_xix_R<7,DUMMY>(addr); NEXT; }
2457  default: UNREACHABLE;
2458  }
2459  }
2460 }
2461 
2462 template<class T> inline void CPUCore<T>::cpuTracePre()
2463 {
2464  start_pc = getPC();
2465 }
2466 template<class T> inline void CPUCore<T>::cpuTracePost()
2467 {
2468  if (unlikely(tracingEnabled)) {
2469  cpuTracePost_slow();
2470  }
2471 }
2472 template<class T> void CPUCore<T>::cpuTracePost_slow()
2473 {
2474  byte opbuf[4];
2475  string dasmOutput;
2476  dasm(*interface, start_pc, opbuf, dasmOutput, T::getTimeFast());
2477  std::cout << std::setfill('0') << std::hex << std::setw(4) << start_pc
2478  << " : " << dasmOutput
2479  << " AF=" << std::setw(4) << getAF()
2480  << " BC=" << std::setw(4) << getBC()
2481  << " DE=" << std::setw(4) << getDE()
2482  << " HL=" << std::setw(4) << getHL()
2483  << " IX=" << std::setw(4) << getIX()
2484  << " IY=" << std::setw(4) << getIY()
2485  << " SP=" << std::setw(4) << getSP()
2486  << '\n' << std::flush << std::dec;
2487 }
2488 
2489 template<class T> void CPUCore<T>::executeSlow()
2490 {
2491  if (unlikely(nmiEdge)) {
2492  nmiEdge = false;
2493  nmi(); // NMI occured
2494  } else if (unlikely(IRQStatus && getIFF1() && !prevWasEI())) {
2495  // normal interrupt
2496  if (unlikely(prevWasLDAI())) {
2497  // HACK!!!
2498  // The 'ld a,i' or 'ld a,r' instruction copies the IFF2
2499  // bit to the V flag. Though when the Z80 accepts an
2500  // IRQ directly after this instruction, the V flag is 0
2501  // (instead of the expected value 1). This can probably
2502  // be explained if you look at the pipeline of the Z80.
2503  // But for speed reasons we implement it here as a
2504  // fix-up (a hack) in the IRQ routine. This behaviour
2505  // is actually a bug in the Z80.
2506  // Thanks to n_n for reporting this behaviour. I think
2507  // this was discovered by GuyveR800. Also thanks to
2508  // n_n for writing a test program that demonstrates
2509  // this quirk.
2510  // I also wrote a test program that demonstrates this
2511  // behaviour is the same whether 'ld a,i' is preceded
2512  // by a 'ei' instruction or not (so it's not caused by
2513  // the 'delayed IRQ acceptance of ei').
2514  assert(getF() & V_FLAG);
2515  setF(getF() & ~V_FLAG);
2516  }
2517  IRQAccept.signal();
2518  switch (getIM()) {
2519  case 0: irq0();
2520  break;
2521  case 1: irq1();
2522  break;
2523  case 2: irq2();
2524  break;
2525  default:
2526  UNREACHABLE;
2527  }
2528  } else if (unlikely(getHALT())) {
2529  // in halt mode
2530  incR(T::advanceHalt(T::haltStates(), scheduler.getNext()));
2531  setSlowInstructions();
2532  } else {
2533  cpuTracePre();
2534  assert(T::limitReached()); // we want only one instruction
2535  executeInstructions();
2536  endInstruction();
2537 
2538  if (T::isR800()) {
2539  if (unlikely(prev2WasCall()) && likely(!prevWasPopRet())) {
2540  // On R800 a CALL or RST instruction not _immediately_
2541  // followed by a (single-byte) POP or RET instruction
2542  // causes an extra cycle in that following instruction.
2543  // No idea why yet. See doc/internal/r800-call.txt
2544  // for more information.
2545  //
2546  // TODO this implementation adds the extra cycle at
2547  // the end of the instruction POP/RET. It is not known
2548  // where in the instruction the real R800 adds this cycle.
2549  T::add(1);
2550  }
2551  }
2552  cpuTracePost();
2553  }
2554 }
2555 
2556 template<class T> void CPUCore<T>::execute(bool fastForward)
2557 {
2558  // In fast-forward mode, breakpoints, watchpoints or debug condtions
2559  // won't trigger. It is possible we already are in break mode, but
2560  // break is ignored in fast-forward mode.
2561  assert(fastForward || !interface->isBreaked());
2562  if (fastForward) {
2563  interface->setFastForward(true);
2564  }
2565  execute2(fastForward);
2566  interface->setFastForward(false);
2567 }
2568 
2569 template<class T> void CPUCore<T>::execute2(bool fastForward)
2570 {
2571  // note: Don't use getTimeFast() here, because 'once in a while' we
2572  // need to CPUClock::sync() to avoid overflow.
2573  // Should be done at least once per second (approx). So only
2574  // once in this method is enough.
2575  scheduler.schedule(T::getTime());
2576  setSlowInstructions();
2577 
2578  if (!fastForward && (interface->isContinue() || interface->isStep())) {
2579  // at least one instruction
2580  interface->setContinue(false);
2581  executeSlow();
2582  scheduler.schedule(T::getTimeFast());
2583  --slowInstructions;
2584  if (interface->isStep()) {
2585  interface->setStep(false);
2586  interface->doBreak();
2587  return;
2588  }
2589  }
2590 
2591  // Note: we call scheduler _after_ executing the instruction and before
2592  // deciding between executeFast() and executeSlow() (because a
2593  // SyncPoint could set an IRQ and then we must choose executeSlow())
2594  if (fastForward ||
2595  (!interface->anyBreakPoints() && !tracingEnabled)) {
2596  // fast path, no breakpoints, no tracing
2597  while (!needExitCPULoop()) {
2598  if (slowInstructions) {
2599  --slowInstructions;
2600  executeSlow();
2601  scheduler.schedule(T::getTimeFast());
2602  } else {
2603  while (slowInstructions == 0) {
2604  T::enableLimit(); // does CPUClock::sync()
2605  if (likely(!T::limitReached())) {
2606  // multiple instructions
2607  executeInstructions();
2608  // note: pipeline only shifted one
2609  // step for multiple instructions
2610  endInstruction();
2611  }
2612  scheduler.schedule(T::getTimeFast());
2613  if (needExitCPULoop()) return;
2614  }
2615  }
2616  }
2617  } else {
2618  while (!needExitCPULoop()) {
2619  if (interface->checkBreakPoints(getPC(), motherboard)) {
2620  assert(interface->isBreaked());
2621  break;
2622  }
2623  if (slowInstructions == 0) {
2624  cpuTracePre();
2625  assert(T::limitReached()); // only one instruction
2626  executeInstructions();
2627  endInstruction();
2628  cpuTracePost();
2629  } else {
2630  --slowInstructions;
2631  executeSlow();
2632  }
2633  // Don't use getTimeFast() here, we need a call to
2634  // CPUClock::sync() 'once in a while'. (During a
2635  // reverse fast-forward this wasn't always the case).
2636  scheduler.schedule(T::getTime());
2637  }
2638  }
2639 }
2640 
2641 template<class T> template<Reg8 R8> ALWAYS_INLINE byte CPUCore<T>::get8() const {
2642  if (R8 == A) { return getA(); }
2643  else if (R8 == F) { return getF(); }
2644  else if (R8 == B) { return getB(); }
2645  else if (R8 == C) { return getC(); }
2646  else if (R8 == D) { return getD(); }
2647  else if (R8 == E) { return getE(); }
2648  else if (R8 == H) { return getH(); }
2649  else if (R8 == L) { return getL(); }
2650  else if (R8 == IXH) { return getIXh(); }
2651  else if (R8 == IXL) { return getIXl(); }
2652  else if (R8 == IYH) { return getIYh(); }
2653  else if (R8 == IYL) { return getIYl(); }
2654  else if (R8 == REG_I) { return getI(); }
2655  else if (R8 == REG_R) { return getR(); }
2656  else if (R8 == DUMMY) { return 0; }
2657  else { UNREACHABLE; return 0; }
2658 }
2659 template<class T> template<Reg16 R16> ALWAYS_INLINE unsigned CPUCore<T>::get16() const {
2660  if (R16 == AF) { return getAF(); }
2661  else if (R16 == BC) { return getBC(); }
2662  else if (R16 == DE) { return getDE(); }
2663  else if (R16 == HL) { return getHL(); }
2664  else if (R16 == IX) { return getIX(); }
2665  else if (R16 == IY) { return getIY(); }
2666  else if (R16 == SP) { return getSP(); }
2667  else { UNREACHABLE; return 0; }
2668 }
2669 template<class T> template<Reg8 R8> ALWAYS_INLINE void CPUCore<T>::set8(byte x) {
2670  if (R8 == A) { setA(x); }
2671  else if (R8 == F) { setF(x); }
2672  else if (R8 == B) { setB(x); }
2673  else if (R8 == C) { setC(x); }
2674  else if (R8 == D) { setD(x); }
2675  else if (R8 == E) { setE(x); }
2676  else if (R8 == H) { setH(x); }
2677  else if (R8 == L) { setL(x); }
2678  else if (R8 == IXH) { setIXh(x); }
2679  else if (R8 == IXL) { setIXl(x); }
2680  else if (R8 == IYH) { setIYh(x); }
2681  else if (R8 == IYL) { setIYl(x); }
2682  else if (R8 == REG_I) { setI(x); }
2683  else if (R8 == REG_R) { setR(x); }
2684  else if (R8 == DUMMY) { /* nothing */ }
2685  else { UNREACHABLE; }
2686 }
2687 template<class T> template<Reg16 R16> ALWAYS_INLINE void CPUCore<T>::set16(unsigned x) {
2688  if (R16 == AF) { setAF(x); }
2689  else if (R16 == BC) { setBC(x); }
2690  else if (R16 == DE) { setDE(x); }
2691  else if (R16 == HL) { setHL(x); }
2692  else if (R16 == IX) { setIX(x); }
2693  else if (R16 == IY) { setIY(x); }
2694  else if (R16 == SP) { setSP(x); }
2695  else { UNREACHABLE; }
2696 }
2697 
2698 // LD r,r
2699 template<class T> template<Reg8 DST, Reg8 SRC, int EE> II CPUCore<T>::ld_R_R() {
2700  set8<DST>(get8<SRC>()); return {1, T::CC_LD_R_R + EE};
2701 }
2702 
2703 // LD SP,ss
2704 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ld_sp_SS() {
2705  setSP(get16<REG>()); return {1, T::CC_LD_SP_HL + EE};
2706 }
2707 
2708 // LD (ss),a
2709 template<class T> template<Reg16 REG> II CPUCore<T>::ld_SS_a() {
2710  T::setMemPtr((getA() << 8) | ((get16<REG>() + 1) & 0xFF));
2711  WRMEM(get16<REG>(), getA(), T::CC_LD_SS_A_1);
2712  return {1, T::CC_LD_SS_A};
2713 }
2714 
2715 // LD (HL),r
2716 template<class T> template<Reg8 SRC> II CPUCore<T>::ld_xhl_R() {
2717  WRMEM(getHL(), get8<SRC>(), T::CC_LD_HL_R_1);
2718  return {1, T::CC_LD_HL_R};
2719 }
2720 
2721 // LD (IXY+e),r
2722 template<class T> template<Reg16 IXY, Reg8 SRC> II CPUCore<T>::ld_xix_R() {
2723  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_LD_XIX_R_1);
2724  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2725  T::setMemPtr(addr);
2726  WRMEM(addr, get8<SRC>(), T::CC_DD + T::CC_LD_XIX_R_2);
2727  return {2, T::CC_DD + T::CC_LD_XIX_R};
2728 }
2729 
2730 // LD (HL),n
2731 template<class T> II CPUCore<T>::ld_xhl_byte() {
2732  byte val = RDMEM_OPCODE<1>(T::CC_LD_HL_N_1);
2733  WRMEM(getHL(), val, T::CC_LD_HL_N_2);
2734  return {2, T::CC_LD_HL_N};
2735 }
2736 
2737 // LD (IXY+e),n
2738 template<class T> template<Reg16 IXY> II CPUCore<T>::ld_xix_byte() {
2739  unsigned tmp = RD_WORD_PC<1>(T::CC_DD + T::CC_LD_XIX_N_1);
2740  int8_t ofst = tmp & 0xFF;
2741  byte val = tmp >> 8;
2742  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2743  T::setMemPtr(addr);
2744  WRMEM(addr, val, T::CC_DD + T::CC_LD_XIX_N_2);
2745  return {3, T::CC_DD + T::CC_LD_XIX_N};
2746 }
2747 
2748 // LD (nn),A
2749 template<class T> II CPUCore<T>::ld_xbyte_a() {
2750  unsigned x = RD_WORD_PC<1>(T::CC_LD_NN_A_1);
2751  T::setMemPtr((getA() << 8) | ((x + 1) & 0xFF));
2752  WRMEM(x, getA(), T::CC_LD_NN_A_2);
2753  return {3, T::CC_LD_NN_A};
2754 }
2755 
2756 // LD (nn),ss
2757 template<class T> template<int EE> inline II CPUCore<T>::WR_NN_Y(unsigned reg) {
2758  unsigned addr = RD_WORD_PC<1>(T::CC_LD_XX_HL_1 + EE);
2759  T::setMemPtr(addr + 1);
2760  WR_WORD(addr, reg, T::CC_LD_XX_HL_2 + EE);
2761  return {3, T::CC_LD_XX_HL + EE};
2762 }
2763 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ld_xword_SS() {
2764  return WR_NN_Y<EE >(get16<REG>());
2765 }
2766 template<class T> template<Reg16 REG> II CPUCore<T>::ld_xword_SS_ED() {
2767  return WR_NN_Y<T::EE_ED>(get16<REG>());
2768 }
2769 
2770 // LD A,(ss)
2771 template<class T> template<Reg16 REG> II CPUCore<T>::ld_a_SS() {
2772  T::setMemPtr(get16<REG>() + 1);
2773  setA(RDMEM(get16<REG>(), T::CC_LD_A_SS_1));
2774  return {1, T::CC_LD_A_SS};
2775 }
2776 
2777 // LD A,(nn)
2778 template<class T> II CPUCore<T>::ld_a_xbyte() {
2779  unsigned addr = RD_WORD_PC<1>(T::CC_LD_A_NN_1);
2780  T::setMemPtr(addr + 1);
2781  setA(RDMEM(addr, T::CC_LD_A_NN_2));
2782  return {3, T::CC_LD_A_NN};
2783 }
2784 
2785 // LD r,n
2786 template<class T> template<Reg8 DST, int EE> II CPUCore<T>::ld_R_byte() {
2787  set8<DST>(RDMEM_OPCODE<1>(T::CC_LD_R_N_1 + EE)); return {2, T::CC_LD_R_N + EE};
2788 }
2789 
2790 // LD r,(hl)
2791 template<class T> template<Reg8 DST> II CPUCore<T>::ld_R_xhl() {
2792  set8<DST>(RDMEM(getHL(), T::CC_LD_R_HL_1)); return {1, T::CC_LD_R_HL};
2793 }
2794 
2795 // LD r,(IXY+e)
2796 template<class T> template<Reg8 DST, Reg16 IXY> II CPUCore<T>::ld_R_xix() {
2797  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_LD_R_XIX_1);
2798  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2799  T::setMemPtr(addr);
2800  set8<DST>(RDMEM(addr, T::CC_DD + T::CC_LD_R_XIX_2));
2801  return {2, T::CC_DD + T::CC_LD_R_XIX};
2802 }
2803 
2804 // LD ss,(nn)
2805 template<class T> template<int EE> inline unsigned CPUCore<T>::RD_P_XX() {
2806  unsigned addr = RD_WORD_PC<1>(T::CC_LD_HL_XX_1 + EE);
2807  T::setMemPtr(addr + 1);
2808  unsigned result = RD_WORD(addr, T::CC_LD_HL_XX_2 + EE);
2809  return result;
2810 }
2811 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ld_SS_xword() {
2812  set16<REG>(RD_P_XX<EE>()); return {3, T::CC_LD_HL_XX + EE};
2813 }
2814 template<class T> template<Reg16 REG> II CPUCore<T>::ld_SS_xword_ED() {
2815  set16<REG>(RD_P_XX<T::EE_ED>()); return {3, T::CC_LD_HL_XX + T::EE_ED};
2816 }
2817 
2818 // LD ss,nn
2819 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ld_SS_word() {
2820  set16<REG>(RD_WORD_PC<1>(T::CC_LD_SS_NN_1 + EE)); return {3, T::CC_LD_SS_NN + EE};
2821 }
2822 
2823 
2824 // ADC A,r
2825 template<class T> inline void CPUCore<T>::ADC(byte reg) {
2826  unsigned res = getA() + reg + ((getF() & C_FLAG) ? 1 : 0);
2827  byte f = ((res & 0x100) ? C_FLAG : 0) |
2828  ((getA() ^ res ^ reg) & H_FLAG) |
2829  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2830  0; // N_FLAG
2831  if (T::isR800()) {
2832  f |= table.ZS[res & 0xFF];
2833  f |= getF() & (X_FLAG | Y_FLAG);
2834  } else {
2835  f |= table.ZSXY[res & 0xFF];
2836  }
2837  setF(f);
2838  setA(res);
2839 }
2840 template<class T> inline II CPUCore<T>::adc_a_a() {
2841  unsigned res = 2 * getA() + ((getF() & C_FLAG) ? 1 : 0);
2842  byte f = ((res & 0x100) ? C_FLAG : 0) |
2843  (res & H_FLAG) |
2844  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2845  0; // N_FLAG
2846  if (T::isR800()) {
2847  f |= table.ZS[res & 0xFF];
2848  f |= getF() & (X_FLAG | Y_FLAG);
2849  } else {
2850  f |= table.ZSXY[res & 0xFF];
2851  }
2852  setF(f);
2853  setA(res);
2854  return {1, T::CC_CP_R};
2855 }
2856 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::adc_a_R() {
2857  ADC(get8<SRC>()); return {1, T::CC_CP_R + EE};
2858 }
2859 template<class T> II CPUCore<T>::adc_a_byte() {
2860  ADC(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2861 }
2862 template<class T> II CPUCore<T>::adc_a_xhl() {
2863  ADC(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2864 }
2865 template<class T> template<Reg16 IXY> II CPUCore<T>::adc_a_xix() {
2866  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2867  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2868  T::setMemPtr(addr);
2869  ADC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2870  return {2, T::CC_DD + T::CC_CP_XIX};
2871 }
2872 
2873 // ADD A,r
2874 template<class T> inline void CPUCore<T>::ADD(byte reg) {
2875  unsigned res = getA() + reg;
2876  byte f = ((res & 0x100) ? C_FLAG : 0) |
2877  ((getA() ^ res ^ reg) & H_FLAG) |
2878  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2879  0; // N_FLAG
2880  if (T::isR800()) {
2881  f |= table.ZS[res & 0xFF];
2882  f |= getF() & (X_FLAG | Y_FLAG);
2883  } else {
2884  f |= table.ZSXY[res & 0xFF];
2885  }
2886  setF(f);
2887  setA(res);
2888 }
2889 template<class T> inline II CPUCore<T>::add_a_a() {
2890  unsigned res = 2 * getA();
2891  byte f = ((res & 0x100) ? C_FLAG : 0) |
2892  (res & H_FLAG) |
2893  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2894  0; // N_FLAG
2895  if (T::isR800()) {
2896  f |= table.ZS[res & 0xFF];
2897  f |= getF() & (X_FLAG | Y_FLAG);
2898  } else {
2899  f |= table.ZSXY[res & 0xFF];
2900  }
2901  setF(f);
2902  setA(res);
2903  return {1, T::CC_CP_R};
2904 }
2905 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::add_a_R() {
2906  ADD(get8<SRC>()); return {1, T::CC_CP_R + EE};
2907 }
2908 template<class T> II CPUCore<T>::add_a_byte() {
2909  ADD(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2910 }
2911 template<class T> II CPUCore<T>::add_a_xhl() {
2912  ADD(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2913 }
2914 template<class T> template<Reg16 IXY> II CPUCore<T>::add_a_xix() {
2915  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2916  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2917  T::setMemPtr(addr);
2918  ADD(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2919  return {2, T::CC_DD + T::CC_CP_XIX};
2920 }
2921 
2922 // AND r
2923 template<class T> inline void CPUCore<T>::AND(byte reg) {
2924  setA(getA() & reg);
2925  byte f = 0;
2926  if (T::isR800()) {
2927  f |= table.ZSPH[getA()];
2928  f |= getF() & (X_FLAG | Y_FLAG);
2929  } else {
2930  f |= table.ZSPXY[getA()] | H_FLAG;
2931  }
2932  setF(f);
2933 }
2934 template<class T> II CPUCore<T>::and_a() {
2935  byte f = 0;
2936  if (T::isR800()) {
2937  f |= table.ZSPH[getA()];
2938  f |= getF() & (X_FLAG | Y_FLAG);
2939  } else {
2940  f |= table.ZSPXY[getA()] | H_FLAG;
2941  }
2942  setF(f);
2943  return {1, T::CC_CP_R};
2944 }
2945 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::and_R() {
2946  AND(get8<SRC>()); return {1, T::CC_CP_R + EE};
2947 }
2948 template<class T> II CPUCore<T>::and_byte() {
2949  AND(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2950 }
2951 template<class T> II CPUCore<T>::and_xhl() {
2952  AND(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2953 }
2954 template<class T> template<Reg16 IXY> II CPUCore<T>::and_xix() {
2955  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2956  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2957  T::setMemPtr(addr);
2958  AND(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2959  return {2, T::CC_DD + T::CC_CP_XIX};
2960 }
2961 
2962 // CP r
2963 template<class T> inline void CPUCore<T>::CP(byte reg) {
2964  unsigned q = getA() - reg;
2965  byte f = table.ZS[q & 0xFF] |
2966  ((q & 0x100) ? C_FLAG : 0) |
2967  N_FLAG |
2968  ((getA() ^ q ^ reg) & H_FLAG) |
2969  (((reg ^ getA()) & (getA() ^ q) & 0x80) >> 5); // V_FLAG
2970  if (T::isR800()) {
2971  f |= getF() & (X_FLAG | Y_FLAG);
2972  } else {
2973  f |= reg & (X_FLAG | Y_FLAG); // XY from operand, not from result
2974  }
2975  setF(f);
2976 }
2977 template<class T> II CPUCore<T>::cp_a() {
2978  byte f = ZS0 | N_FLAG;
2979  if (T::isR800()) {
2980  f |= getF() & (X_FLAG | Y_FLAG);
2981  } else {
2982  f |= getA() & (X_FLAG | Y_FLAG); // XY from operand, not from result
2983  }
2984  setF(f);
2985  return {1, T::CC_CP_R};
2986 }
2987 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::cp_R() {
2988  CP(get8<SRC>()); return {1, T::CC_CP_R + EE};
2989 }
2990 template<class T> II CPUCore<T>::cp_byte() {
2991  CP(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2992 }
2993 template<class T> II CPUCore<T>::cp_xhl() {
2994  CP(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2995 }
2996 template<class T> template<Reg16 IXY> II CPUCore<T>::cp_xix() {
2997  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2998  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2999  T::setMemPtr(addr);
3000  CP(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3001  return {2, T::CC_DD + T::CC_CP_XIX};
3002 }
3003 
3004 // OR r
3005 template<class T> inline void CPUCore<T>::OR(byte reg) {
3006  setA(getA() | reg);
3007  byte f = 0;
3008  if (T::isR800()) {
3009  f |= table.ZSP[getA()];
3010  f |= getF() & (X_FLAG | Y_FLAG);
3011  } else {
3012  f |= table.ZSPXY[getA()];
3013  }
3014  setF(f);
3015 }
3016 template<class T> II CPUCore<T>::or_a() {
3017  byte f = 0;
3018  if (T::isR800()) {
3019  f |= table.ZSP[getA()];
3020  f |= getF() & (X_FLAG | Y_FLAG);
3021  } else {
3022  f |= table.ZSPXY[getA()];
3023  }
3024  setF(f);
3025  return {1, T::CC_CP_R};
3026 }
3027 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::or_R() {
3028  OR(get8<SRC>()); return {1, T::CC_CP_R + EE};
3029 }
3030 template<class T> II CPUCore<T>::or_byte() {
3031  OR(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3032 }
3033 template<class T> II CPUCore<T>::or_xhl() {
3034  OR(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3035 }
3036 template<class T> template<Reg16 IXY> II CPUCore<T>::or_xix() {
3037  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3038  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3039  T::setMemPtr(addr);
3040  OR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3041  return {2, T::CC_DD + T::CC_CP_XIX};
3042 }
3043 
3044 // SBC A,r
3045 template<class T> inline void CPUCore<T>::SBC(byte reg) {
3046  unsigned res = getA() - reg - ((getF() & C_FLAG) ? 1 : 0);
3047  byte f = ((res & 0x100) ? C_FLAG : 0) |
3048  N_FLAG |
3049  ((getA() ^ res ^ reg) & H_FLAG) |
3050  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3051  if (T::isR800()) {
3052  f |= table.ZS[res & 0xFF];
3053  f |= getF() & (X_FLAG | Y_FLAG);
3054  } else {
3055  f |= table.ZSXY[res & 0xFF];
3056  }
3057  setF(f);
3058  setA(res);
3059 }
3060 template<class T> II CPUCore<T>::sbc_a_a() {
3061  if (T::isR800()) {
3062  word t = (getF() & C_FLAG)
3063  ? (255 * 256 | ZS255 | C_FLAG | H_FLAG | N_FLAG)
3064  : ( 0 * 256 | ZS0 | N_FLAG);
3065  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3066  } else {
3067  setAF((getF() & C_FLAG) ?
3068  (255 * 256 | ZSXY255 | C_FLAG | H_FLAG | N_FLAG) :
3069  ( 0 * 256 | ZSXY0 | N_FLAG));
3070  }
3071  return {1, T::CC_CP_R};
3072 }
3073 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::sbc_a_R() {
3074  SBC(get8<SRC>()); return {1, T::CC_CP_R + EE};
3075 }
3076 template<class T> II CPUCore<T>::sbc_a_byte() {
3077  SBC(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3078 }
3079 template<class T> II CPUCore<T>::sbc_a_xhl() {
3080  SBC(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3081 }
3082 template<class T> template<Reg16 IXY> II CPUCore<T>::sbc_a_xix() {
3083  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3084  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3085  T::setMemPtr(addr);
3086  SBC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3087  return {2, T::CC_DD + T::CC_CP_XIX};
3088 }
3089 
3090 // SUB r
3091 template<class T> inline void CPUCore<T>::SUB(byte reg) {
3092  unsigned res = getA() - reg;
3093  byte f = ((res & 0x100) ? C_FLAG : 0) |
3094  N_FLAG |
3095  ((getA() ^ res ^ reg) & H_FLAG) |
3096  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3097  if (T::isR800()) {
3098  f |= table.ZS[res & 0xFF];
3099  f |= getF() & (X_FLAG | Y_FLAG);
3100  } else {
3101  f |= table.ZSXY[res & 0xFF];
3102  }
3103  setF(f);
3104  setA(res);
3105 }
3106 template<class T> II CPUCore<T>::sub_a() {
3107  if (T::isR800()) {
3108  word t = 0 * 256 | ZS0 | N_FLAG;
3109  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3110  } else {
3111  setAF(0 * 256 | ZSXY0 | N_FLAG);
3112  }
3113  return {1, T::CC_CP_R};
3114 }
3115 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::sub_R() {
3116  SUB(get8<SRC>()); return {1, T::CC_CP_R + EE};
3117 }
3118 template<class T> II CPUCore<T>::sub_byte() {
3119  SUB(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3120 }
3121 template<class T> II CPUCore<T>::sub_xhl() {
3122  SUB(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3123 }
3124 template<class T> template<Reg16 IXY> II CPUCore<T>::sub_xix() {
3125  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3126  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3127  T::setMemPtr(addr);
3128  SUB(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3129  return {2, T::CC_DD + T::CC_CP_XIX};
3130 }
3131 
3132 // XOR r
3133 template<class T> inline void CPUCore<T>::XOR(byte reg) {
3134  setA(getA() ^ reg);
3135  byte f = 0;
3136  if (T::isR800()) {
3137  f |= table.ZSP[getA()];
3138  f |= getF() & (X_FLAG | Y_FLAG);
3139  } else {
3140  f |= table.ZSPXY[getA()];
3141  }
3142  setF(f);
3143 }
3144 template<class T> II CPUCore<T>::xor_a() {
3145  if (T::isR800()) {
3146  word t = 0 * 256 + ZSP0;
3147  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3148  } else {
3149  setAF(0 * 256 + ZSPXY0);
3150  }
3151  return {1, T::CC_CP_R};
3152 }
3153 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::xor_R() {
3154  XOR(get8<SRC>()); return {1, T::CC_CP_R + EE};
3155 }
3156 template<class T> II CPUCore<T>::xor_byte() {
3157  XOR(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3158 }
3159 template<class T> II CPUCore<T>::xor_xhl() {
3160  XOR(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3161 }
3162 template<class T> template<Reg16 IXY> II CPUCore<T>::xor_xix() {
3163  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3164  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3165  T::setMemPtr(addr);
3166  XOR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3167  return {2, T::CC_DD + T::CC_CP_XIX};
3168 }
3169 
3170 
3171 // DEC r
3172 template<class T> inline byte CPUCore<T>::DEC(byte reg) {
3173  byte res = reg - 1;
3174  byte f = ((reg & ~res & 0x80) >> 5) | // V_FLAG
3175  (((res & 0x0F) + 1) & H_FLAG) |
3176  N_FLAG;
3177  if (T::isR800()) {
3178  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3179  f |= table.ZS[res];
3180  } else {
3181  f |= getF() & C_FLAG;
3182  f |= table.ZSXY[res];
3183  }
3184  setF(f);
3185  return res;
3186 }
3187 template<class T> template<Reg8 REG, int EE> II CPUCore<T>::dec_R() {
3188  set8<REG>(DEC(get8<REG>())); return {1, T::CC_INC_R + EE};
3189 }
3190 template<class T> template<int EE> inline void CPUCore<T>::DEC_X(unsigned x) {
3191  byte val = DEC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3192  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3193 }
3194 template<class T> II CPUCore<T>::dec_xhl() {
3195  DEC_X<0>(getHL());
3196  return {1, T::CC_INC_XHL};
3197 }
3198 template<class T> template<Reg16 IXY> II CPUCore<T>::dec_xix() {
3199  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_INC_XIX_1);
3200  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3201  T::setMemPtr(addr);
3202  DEC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3203  return {2, T::CC_INC_XHL + T::CC_DD + T::EE_INC_XIX};
3204 }
3205 
3206 // INC r
3207 template<class T> inline byte CPUCore<T>::INC(byte reg) {
3208  reg++;
3209  byte f = ((reg & -reg & 0x80) >> 5) | // V_FLAG
3210  (((reg & 0x0F) - 1) & H_FLAG) |
3211  0; // N_FLAG
3212  if (T::isR800()) {
3213  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3214  f |= table.ZS[reg];
3215  } else {
3216  f |= getF() & C_FLAG;
3217  f |= table.ZSXY[reg];
3218  }
3219  setF(f);
3220  return reg;
3221 }
3222 template<class T> template<Reg8 REG, int EE> II CPUCore<T>::inc_R() {
3223  set8<REG>(INC(get8<REG>())); return {1, T::CC_INC_R + EE};
3224 }
3225 template<class T> template<int EE> inline void CPUCore<T>::INC_X(unsigned x) {
3226  byte val = INC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3227  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3228 }
3229 template<class T> II CPUCore<T>::inc_xhl() {
3230  INC_X<0>(getHL());
3231  return {1, T::CC_INC_XHL};
3232 }
3233 template<class T> template<Reg16 IXY> II CPUCore<T>::inc_xix() {
3234  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_INC_XIX_1);
3235  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3236  T::setMemPtr(addr);
3237  INC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3238  return {2, T::CC_INC_XHL + T::CC_DD + T::EE_INC_XIX};
3239 }
3240 
3241 
3242 // ADC HL,ss
3243 template<class T> template<Reg16 REG> inline II CPUCore<T>::adc_hl_SS() {
3244  unsigned reg = get16<REG>();
3245  T::setMemPtr(getHL() + 1);
3246  unsigned res = getHL() + reg + ((getF() & C_FLAG) ? 1 : 0);
3247  byte f = (res >> 16) | // C_FLAG
3248  0; // N_FLAG
3249  if (T::isR800()) {
3250  f |= getF() & (X_FLAG | Y_FLAG);
3251  }
3252  if (res & 0xFFFF) {
3253  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3254  f |= 0; // Z_FLAG
3255  f |= ((getHL() ^ res) & (reg ^ res) & 0x8000) >> 13; // V_FLAG
3256  if (T::isR800()) {
3257  f |= (res >> 8) & S_FLAG;
3258  } else {
3259  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3260  }
3261  } else {
3262  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3263  f |= Z_FLAG;
3264  f |= (getHL() & reg & 0x8000) >> 13; // V_FLAG
3265  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3266  }
3267  setF(f);
3268  setHL(res);
3269  return {1, T::CC_ADC_HL_SS};
3270 }
3271 template<class T> II CPUCore<T>::adc_hl_hl() {
3272  T::setMemPtr(getHL() + 1);
3273  unsigned res = 2 * getHL() + ((getF() & C_FLAG) ? 1 : 0);
3274  byte f = (res >> 16) | // C_FLAG
3275  0; // N_FLAG
3276  if (T::isR800()) {
3277  f |= getF() & (X_FLAG | Y_FLAG);
3278  }
3279  if (res & 0xFFFF) {
3280  f |= 0; // Z_FLAG
3281  f |= ((getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3282  if (T::isR800()) {
3283  f |= (res >> 8) & (H_FLAG | S_FLAG);
3284  } else {
3285  f |= (res >> 8) & (H_FLAG | S_FLAG | X_FLAG | Y_FLAG);
3286  }
3287  } else {
3288  f |= Z_FLAG;
3289  f |= (getHL() & 0x8000) >> 13; // V_FLAG
3290  f |= 0; // H_FLAG S_FLAG (X_FLAG Y_FLAG)
3291  }
3292  setF(f);
3293  setHL(res);
3294  return {1, T::CC_ADC_HL_SS};
3295 }
3296 
3297 // ADD HL/IX/IY,ss
3298 template<class T> template<Reg16 REG1, Reg16 REG2, int EE> II CPUCore<T>::add_SS_TT() {
3299  unsigned reg1 = get16<REG1>();
3300  unsigned reg2 = get16<REG2>();
3301  T::setMemPtr(reg1 + 1);
3302  unsigned res = reg1 + reg2;
3303  byte f = (((reg1 ^ res ^ reg2) >> 8) & H_FLAG) |
3304  (res >> 16) | // C_FLAG
3305  0; // N_FLAG
3306  if (T::isR800()) {
3307  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3308  } else {
3309  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3310  f |= (res >> 8) & (X_FLAG | Y_FLAG);
3311  }
3312  setF(f);
3313  set16<REG1>(res & 0xFFFF);
3314  return {1, T::CC_ADD_HL_SS + EE};
3315 }
3316 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::add_SS_SS() {
3317  unsigned reg = get16<REG>();
3318  T::setMemPtr(reg + 1);
3319  unsigned res = 2 * reg;
3320  byte f = (res >> 16) | // C_FLAG
3321  0; // N_FLAG
3322  if (T::isR800()) {
3323  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3324  f |= (res >> 8) & H_FLAG;
3325  } else {
3326  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3327  f |= (res >> 8) & (H_FLAG | X_FLAG | Y_FLAG);
3328  }
3329  setF(f);
3330  set16<REG>(res & 0xFFFF);
3331  return {1, T::CC_ADD_HL_SS + EE};
3332 }
3333 
3334 // SBC HL,ss
3335 template<class T> template<Reg16 REG> inline II CPUCore<T>::sbc_hl_SS() {
3336  unsigned reg = get16<REG>();
3337  T::setMemPtr(getHL() + 1);
3338  unsigned res = getHL() - reg - ((getF() & C_FLAG) ? 1 : 0);
3339  byte f = ((res & 0x10000) ? C_FLAG : 0) |
3340  N_FLAG;
3341  if (T::isR800()) {
3342  f |= getF() & (X_FLAG | Y_FLAG);
3343  }
3344  if (res & 0xFFFF) {
3345  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3346  f |= 0; // Z_FLAG
3347  f |= ((reg ^ getHL()) & (getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3348  if (T::isR800()) {
3349  f |= (res >> 8) & S_FLAG;
3350  } else {
3351  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3352  }
3353  } else {
3354  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3355  f |= Z_FLAG;
3356  f |= ((reg ^ getHL()) & getHL() & 0x8000) >> 13; // V_FLAG
3357  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3358  }
3359  setF(f);
3360  setHL(res);
3361  return {1, T::CC_ADC_HL_SS};
3362 }
3363 template<class T> II CPUCore<T>::sbc_hl_hl() {
3364  T::setMemPtr(getHL() + 1);
3365  byte f = T::isR800() ? (getF() & (X_FLAG | Y_FLAG)) : 0;
3366  if (getF() & C_FLAG) {
3367  f |= C_FLAG | H_FLAG | S_FLAG | N_FLAG;
3368  if (!T::isR800()) {
3369  f |= X_FLAG | Y_FLAG;
3370  }
3371  setHL(0xFFFF);
3372  } else {
3373  f |= Z_FLAG | N_FLAG;
3374  setHL(0);
3375  }
3376  setF(f);
3377  return {1, T::CC_ADC_HL_SS};
3378 }
3379 
3380 // DEC ss
3381 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::dec_SS() {
3382  set16<REG>(get16<REG>() - 1); return {1, T::CC_INC_SS + EE};
3383 }
3384 
3385 // INC ss
3386 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::inc_SS() {
3387  set16<REG>(get16<REG>() + 1); return {1, T::CC_INC_SS + EE};
3388 }
3389 
3390 
3391 // BIT n,r
3392 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::bit_N_R() {
3393  byte reg = get8<REG>();
3394  byte f = 0; // N_FLAG
3395  if (T::isR800()) {
3396  // this is very different from Z80 (not only XY flags)
3397  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3398  f |= H_FLAG;
3399  f |= (reg & (1 << N)) ? 0 : Z_FLAG;
3400  } else {
3401  f |= table.ZSPH[reg & (1 << N)];
3402  f |= getF() & C_FLAG;
3403  f |= reg & (X_FLAG | Y_FLAG);
3404  }
3405  setF(f);
3406  return {1, T::CC_BIT_R};
3407 }
3408 template<class T> template<unsigned N> inline II CPUCore<T>::bit_N_xhl() {
3409  byte m = RDMEM(getHL(), T::CC_BIT_XHL_1) & (1 << N);
3410  byte f = 0; // N_FLAG
3411  if (T::isR800()) {
3412  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3413  f |= H_FLAG;
3414  f |= m ? 0 : Z_FLAG;
3415  } else {
3416  f |= table.ZSPH[m];
3417  f |= getF() & C_FLAG;
3418  f |= (T::getMemPtr() >> 8) & (X_FLAG | Y_FLAG);
3419  }
3420  setF(f);
3421  return {1, T::CC_BIT_XHL};
3422 }
3423 template<class T> template<unsigned N> inline II CPUCore<T>::bit_N_xix(unsigned addr) {
3424  T::setMemPtr(addr);
3425  byte m = RDMEM(addr, T::CC_DD + T::CC_BIT_XIX_1) & (1 << N);
3426  byte f = 0; // N_FLAG
3427  if (T::isR800()) {
3428  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3429  f |= H_FLAG;
3430  f |= m ? 0 : Z_FLAG;
3431  } else {
3432  f |= table.ZSPH[m];
3433  f |= getF() & C_FLAG;
3434  f |= (addr >> 8) & (X_FLAG | Y_FLAG);
3435  }
3436  setF(f);
3437  return {3, T::CC_DD + T::CC_BIT_XIX};
3438 }
3439 
3440 // RES n,r
3441 static inline byte RES(unsigned b, byte reg) {
3442  return reg & ~(1 << b);
3443 }
3444 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::res_N_R() {
3445  set8<REG>(RES(N, get8<REG>())); return {1, T::CC_SET_R};
3446 }
3447 template<class T> template<int EE> inline byte CPUCore<T>::RES_X(unsigned bit, unsigned addr) {
3448  byte res = RES(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3449  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3450  return res;
3451 }
3452 template<class T> template<unsigned N> II CPUCore<T>::res_N_xhl() {
3453  RES_X<0>(N, getHL()); return {1, T::CC_SET_XHL};
3454 }
3455 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::res_N_xix_R(unsigned a) {
3456  T::setMemPtr(a);
3457  set8<REG>(RES_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3458  return {3, T::CC_DD + T::CC_SET_XIX};
3459 }
3460 
3461 // SET n,r
3462 static inline byte SET(unsigned b, byte reg) {
3463  return reg | (1 << b);
3464 }
3465 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::set_N_R() {
3466  set8<REG>(SET(N, get8<REG>())); return {1, T::CC_SET_R};
3467 }
3468 template<class T> template<int EE> inline byte CPUCore<T>::SET_X(unsigned bit, unsigned addr) {
3469  byte res = SET(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3470  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3471  return res;
3472 }
3473 template<class T> template<unsigned N> II CPUCore<T>::set_N_xhl() {
3474  SET_X<0>(N, getHL()); return {1, T::CC_SET_XHL};
3475 }
3476 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::set_N_xix_R(unsigned a) {
3477  T::setMemPtr(a);
3478  set8<REG>(SET_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3479  return {3, T::CC_DD + T::CC_SET_XIX};
3480 }
3481 
3482 // RL r
3483 template<class T> inline byte CPUCore<T>::RL(byte reg) {
3484  byte c = reg >> 7;
3485  reg = (reg << 1) | ((getF() & C_FLAG) ? 0x01 : 0);
3486  byte f = c ? C_FLAG : 0;
3487  if (T::isR800()) {
3488  f |= table.ZSP[reg];
3489  f |= getF() & (X_FLAG | Y_FLAG);
3490  } else {
3491  f |= table.ZSPXY[reg];
3492  }
3493  setF(f);
3494  return reg;
3495 }
3496 template<class T> template<int EE> inline byte CPUCore<T>::RL_X(unsigned x) {
3497  byte res = RL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3498  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3499  return res;
3500 }
3501 template<class T> template<Reg8 REG> II CPUCore<T>::rl_R() {
3502  set8<REG>(RL(get8<REG>())); return {1, T::CC_SET_R};
3503 }
3504 template<class T> II CPUCore<T>::rl_xhl() {
3505  RL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3506 }
3507 template<class T> template<Reg8 REG> II CPUCore<T>::rl_xix_R(unsigned a) {
3508  T::setMemPtr(a);
3509  set8<REG>(RL_X<T::CC_DD + T::EE_SET_XIX>(a));
3510  return {3, T::CC_DD + T::CC_SET_XIX};
3511 }
3512 
3513 // RLC r
3514 template<class T> inline byte CPUCore<T>::RLC(byte reg) {
3515  byte c = reg >> 7;
3516  reg = (reg << 1) | c;
3517  byte f = c ? C_FLAG : 0;
3518  if (T::isR800()) {
3519  f |= table.ZSP[reg];
3520  f |= getF() & (X_FLAG | Y_FLAG);
3521  } else {
3522  f |= table.ZSPXY[reg];
3523  }
3524  setF(f);
3525  return reg;
3526 }
3527 template<class T> template<int EE> inline byte CPUCore<T>::RLC_X(unsigned x) {
3528  byte res = RLC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3529  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3530  return res;
3531 }
3532 template<class T> template<Reg8 REG> II CPUCore<T>::rlc_R() {
3533  set8<REG>(RLC(get8<REG>())); return {1, T::CC_SET_R};
3534 }
3535 template<class T> II CPUCore<T>::rlc_xhl() {
3536  RLC_X<0>(getHL()); return {1, T::CC_SET_XHL};
3537 }
3538 template<class T> template<Reg8 REG> II CPUCore<T>::rlc_xix_R(unsigned a) {
3539  T::setMemPtr(a);
3540  set8<REG>(RLC_X<T::CC_DD + T::EE_SET_XIX>(a));
3541  return {3, T::CC_DD + T::CC_SET_XIX};
3542 }
3543 
3544 // RR r
3545 template<class T> inline byte CPUCore<T>::RR(byte reg) {
3546  byte c = reg & 1;
3547  reg = (reg >> 1) | ((getF() & C_FLAG) << 7);
3548  byte f = c ? C_FLAG : 0;
3549  if (T::isR800()) {
3550  f |= table.ZSP[reg];
3551  f |= getF() & (X_FLAG | Y_FLAG);
3552  } else {
3553  f |= table.ZSPXY[reg];
3554  }
3555  setF(f);
3556  return reg;
3557 }
3558 template<class T> template<int EE> inline byte CPUCore<T>::RR_X(unsigned x) {
3559  byte res = RR(RDMEM(x, T::CC_SET_XHL_1 + EE));
3560  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3561  return res;
3562 }
3563 template<class T> template<Reg8 REG> II CPUCore<T>::rr_R() {
3564  set8<REG>(RR(get8<REG>())); return {1, T::CC_SET_R};
3565 }
3566 template<class T> II CPUCore<T>::rr_xhl() {
3567  RR_X<0>(getHL()); return {1, T::CC_SET_XHL};
3568 }
3569 template<class T> template<Reg8 REG> II CPUCore<T>::rr_xix_R(unsigned a) {
3570  T::setMemPtr(a);
3571  set8<REG>(RR_X<T::CC_DD + T::EE_SET_XIX>(a));
3572  return {3, T::CC_DD + T::CC_SET_XIX};
3573 }
3574 
3575 // RRC r
3576 template<class T> inline byte CPUCore<T>::RRC(byte reg) {
3577  byte c = reg & 1;
3578  reg = (reg >> 1) | (c << 7);
3579  byte f = c ? C_FLAG : 0;
3580  if (T::isR800()) {
3581  f |= table.ZSP[reg];
3582  f |= getF() & (X_FLAG | Y_FLAG);
3583  } else {
3584  f |= table.ZSPXY[reg];
3585  }
3586  setF(f);
3587  return reg;
3588 }
3589 template<class T> template<int EE> inline byte CPUCore<T>::RRC_X(unsigned x) {
3590  byte res = RRC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3591  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3592  return res;
3593 }
3594 template<class T> template<Reg8 REG> II CPUCore<T>::rrc_R() {
3595  set8<REG>(RRC(get8<REG>())); return {1, T::CC_SET_R};
3596 }
3597 template<class T> II CPUCore<T>::rrc_xhl() {
3598  RRC_X<0>(getHL()); return {1, T::CC_SET_XHL};
3599 }
3600 template<class T> template<Reg8 REG> II CPUCore<T>::rrc_xix_R(unsigned a) {
3601  T::setMemPtr(a);
3602  set8<REG>(RRC_X<T::CC_DD + T::EE_SET_XIX>(a));
3603  return {3, T::CC_DD + T::CC_SET_XIX};
3604 }
3605 
3606 // SLA r
3607 template<class T> inline byte CPUCore<T>::SLA(byte reg) {
3608  byte c = reg >> 7;
3609  reg <<= 1;
3610  byte f = c ? C_FLAG : 0;
3611  if (T::isR800()) {
3612  f |= table.ZSP[reg];
3613  f |= getF() & (X_FLAG | Y_FLAG);
3614  } else {
3615  f |= table.ZSPXY[reg];
3616  }
3617  setF(f);
3618  return reg;
3619 }
3620 template<class T> template<int EE> inline byte CPUCore<T>::SLA_X(unsigned x) {
3621  byte res = SLA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3622  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3623  return res;
3624 }
3625 template<class T> template<Reg8 REG> II CPUCore<T>::sla_R() {
3626  set8<REG>(SLA(get8<REG>())); return {1, T::CC_SET_R};
3627 }
3628 template<class T> II CPUCore<T>::sla_xhl() {
3629  SLA_X<0>(getHL()); return {1, T::CC_SET_XHL};
3630 }
3631 template<class T> template<Reg8 REG> II CPUCore<T>::sla_xix_R(unsigned a) {
3632  T::setMemPtr(a);
3633  set8<REG>(SLA_X<T::CC_DD + T::EE_SET_XIX>(a));
3634  return {3, T::CC_DD + T::CC_SET_XIX};
3635 }
3636 
3637 // SLL r
3638 template<class T> inline byte CPUCore<T>::SLL(byte reg) {
3639  assert(!T::isR800()); // this instruction is Z80-only
3640  byte c = reg >> 7;
3641  reg = (reg << 1) | 1;
3642  byte f = c ? C_FLAG : 0;
3643  f |= table.ZSPXY[reg];
3644  setF(f);
3645  return reg;
3646 }
3647 template<class T> template<int EE> inline byte CPUCore<T>::SLL_X(unsigned x) {
3648  byte res = SLL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3649  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3650  return res;
3651 }
3652 template<class T> template<Reg8 REG> II CPUCore<T>::sll_R() {
3653  set8<REG>(SLL(get8<REG>())); return {1, T::CC_SET_R};
3654 }
3655 template<class T> II CPUCore<T>::sll_xhl() {
3656  SLL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3657 }
3658 template<class T> template<Reg8 REG> II CPUCore<T>::sll_xix_R(unsigned a) {
3659  T::setMemPtr(a);
3660  set8<REG>(SLL_X<T::CC_DD + T::EE_SET_XIX>(a));
3661  return {3, T::CC_DD + T::CC_SET_XIX};
3662 }
3663 template<class T> II CPUCore<T>::sll2() {
3664  assert(T::isR800()); // this instruction is R800-only
3665  byte f = (getF() & (X_FLAG | Y_FLAG)) |
3666  (getA() >> 7) | // C_FLAG
3667  0; // all other flags zero
3668  setF(f);
3669  return {3, T::CC_DD + T::CC_SET_XIX}; // TODO
3670 }
3671 
3672 // SRA r
3673 template<class T> inline byte CPUCore<T>::SRA(byte reg) {
3674  byte c = reg & 1;
3675  reg = (reg >> 1) | (reg & 0x80);
3676  byte f = c ? C_FLAG : 0;
3677  if (T::isR800()) {
3678  f |= table.ZSP[reg];
3679  f |= getF() & (X_FLAG | Y_FLAG);
3680  } else {
3681  f |= table.ZSPXY[reg];
3682  }
3683  setF(f);
3684  return reg;
3685 }
3686 template<class T> template<int EE> inline byte CPUCore<T>::SRA_X(unsigned x) {
3687  byte res = SRA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3688  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3689  return res;
3690 }
3691 template<class T> template<Reg8 REG> II CPUCore<T>::sra_R() {
3692  set8<REG>(SRA(get8<REG>())); return {1, T::CC_SET_R};
3693 }
3694 template<class T> II CPUCore<T>::sra_xhl() {
3695  SRA_X<0>(getHL()); return {1, T::CC_SET_XHL};
3696 }
3697 template<class T> template<Reg8 REG> II CPUCore<T>::sra_xix_R(unsigned a) {
3698  T::setMemPtr(a);
3699  set8<REG>(SRA_X<T::CC_DD + T::EE_SET_XIX>(a));
3700  return {3, T::CC_DD + T::CC_SET_XIX};
3701 }
3702 
3703 // SRL R
3704 template<class T> inline byte CPUCore<T>::SRL(byte reg) {
3705  byte c = reg & 1;
3706  reg >>= 1;
3707  byte f = c ? C_FLAG : 0;
3708  if (T::isR800()) {
3709  f |= table.ZSP[reg];
3710  f |= getF() & (X_FLAG | Y_FLAG);
3711  } else {
3712  f |= table.ZSPXY[reg];
3713  }
3714  setF(f);
3715  return reg;
3716 }
3717 template<class T> template<int EE> inline byte CPUCore<T>::SRL_X(unsigned x) {
3718  byte res = SRL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3719  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3720  return res;
3721 }
3722 template<class T> template<Reg8 REG> II CPUCore<T>::srl_R() {
3723  set8<REG>(SRL(get8<REG>())); return {1, T::CC_SET_R};
3724 }
3725 template<class T> II CPUCore<T>::srl_xhl() {
3726  SRL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3727 }
3728 template<class T> template<Reg8 REG> II CPUCore<T>::srl_xix_R(unsigned a) {
3729  T::setMemPtr(a);
3730  set8<REG>(SRL_X<T::CC_DD + T::EE_SET_XIX>(a));
3731  return {3, T::CC_DD + T::CC_SET_XIX};
3732 }
3733 
3734 // RLA RLCA RRA RRCA
3735 template<class T> II CPUCore<T>::rla() {
3736  byte c = getF() & C_FLAG;
3737  byte f = (getA() & 0x80) ? C_FLAG : 0;
3738  if (T::isR800()) {
3739  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3740  } else {
3741  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3742  }
3743  setA((getA() << 1) | (c ? 1 : 0));
3744  if (!T::isR800()) {
3745  f |= getA() & (X_FLAG | Y_FLAG);
3746  }
3747  setF(f);
3748  return {1, T::CC_RLA};
3749 }
3750 template<class T> II CPUCore<T>::rlca() {
3751  setA((getA() << 1) | (getA() >> 7));
3752  byte f = 0;
3753  if (T::isR800()) {
3754  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3755  f |= getA() & C_FLAG;
3756  } else {
3757  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3758  f |= getA() & (Y_FLAG | X_FLAG | C_FLAG);
3759  }
3760  setF(f);
3761  return {1, T::CC_RLA};
3762 }
3763 template<class T> II CPUCore<T>::rra() {
3764  byte c = (getF() & C_FLAG) << 7;
3765  byte f = (getA() & 0x01) ? C_FLAG : 0;
3766  if (T::isR800()) {
3767  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3768  } else {
3769  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3770  }
3771  setA((getA() >> 1) | c);
3772  if (!T::isR800()) {
3773  f |= getA() & (X_FLAG | Y_FLAG);
3774  }
3775  setF(f);
3776  return {1, T::CC_RLA};
3777 }
3778 template<class T> II CPUCore<T>::rrca() {
3779  byte f = getA() & C_FLAG;
3780  if (T::isR800()) {
3781  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3782  } else {
3783  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3784  }
3785  setA((getA() >> 1) | (getA() << 7));
3786  if (!T::isR800()) {
3787  f |= getA() & (X_FLAG | Y_FLAG);
3788  }
3789  setF(f);
3790  return {1, T::CC_RLA};
3791 }
3792 
3793 
3794 // RLD
3795 template<class T> II CPUCore<T>::rld() {
3796  byte val = RDMEM(getHL(), T::CC_RLD_1);
3797  T::setMemPtr(getHL() + 1);
3798  WRMEM(getHL(), (val << 4) | (getA() & 0x0F), T::CC_RLD_2);
3799  setA((getA() & 0xF0) | (val >> 4));
3800  byte f = 0;
3801  if (T::isR800()) {
3802  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3803  f |= table.ZSP[getA()];
3804  } else {
3805  f |= getF() & C_FLAG;
3806  f |= table.ZSPXY[getA()];
3807  }
3808  setF(f);
3809  return {1, T::CC_RLD};
3810 }
3811 
3812 // RRD
3813 template<class T> II CPUCore<T>::rrd() {
3814  byte val = RDMEM(getHL(), T::CC_RLD_1);
3815  T::setMemPtr(getHL() + 1);
3816  WRMEM(getHL(), (val >> 4) | (getA() << 4), T::CC_RLD_2);
3817  setA((getA() & 0xF0) | (val & 0x0F));
3818  byte f = 0;
3819  if (T::isR800()) {
3820  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3821  f |= table.ZSP[getA()];
3822  } else {
3823  f |= getF() & C_FLAG;
3824  f |= table.ZSPXY[getA()];
3825  }
3826  setF(f);
3827  return {1, T::CC_RLD};
3828 }
3829 
3830 
3831 // PUSH ss
3832 template<class T> template<int EE> inline void CPUCore<T>::PUSH(unsigned reg) {
3833  setSP(getSP() - 2);
3834  WR_WORD_rev<true, true>(getSP(), reg, T::CC_PUSH_1 + EE);
3835 }
3836 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::push_SS() {
3837  PUSH<EE>(get16<REG>()); return {1, T::CC_PUSH + EE};
3838 }
3839 
3840 // POP ss
3841 template<class T> template<int EE> inline unsigned CPUCore<T>::POP() {
3842  unsigned addr = getSP();
3843  setSP(addr + 2);
3844  if (T::isR800()) {
3845  // handles both POP and RET instructions (RET with condition = true)
3846  if (EE == 0) { // not reti/retn, not pop ix/iy
3847  setCurrentPopRet();
3848  // No need for setSlowInstructions()
3849  // -> this only matters directly after a CALL
3850  // instruction and in that case we're still
3851  // executing slow instructions.
3852  }
3853  }
3854  return RD_WORD(addr, T::CC_POP_1 + EE);
3855 }
3856 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::pop_SS() {
3857  set16<REG>(POP<EE>()); return {1, T::CC_POP + EE};
3858 }
3859 
3860 
3861 // CALL nn / CALL cc,nn
3862 template<class T> template<typename COND> II CPUCore<T>::call(COND cond) {
3863  unsigned addr = RD_WORD_PC<1>(T::CC_CALL_1);
3864  T::setMemPtr(addr);
3865  if (cond(getF())) {
3866  PUSH<T::EE_CALL>(getPC() + 3);
3867  setPC(addr);
3868  if (T::isR800()) {
3869  setCurrentCall();
3870  setSlowInstructions();
3871  }
3872  return {0/*3*/, T::CC_CALL_A};
3873  } else {
3874  return {3, T::CC_CALL_B};
3875  }
3876 }
3877 
3878 
3879 // RST n
3880 template<class T> template<unsigned ADDR> II CPUCore<T>::rst() {
3881  PUSH<0>(getPC() + 1);
3882  T::setMemPtr(ADDR);
3883  setPC(ADDR);
3884  if (T::isR800()) {
3885  setCurrentCall();
3886  setSlowInstructions();
3887  }
3888  return {0/*1*/, T::CC_RST};
3889 }
3890 
3891 
3892 // RET
3893 template<class T> template<int EE, typename COND> inline II CPUCore<T>::RET(COND cond) {
3894  if (cond(getF())) {
3895  unsigned addr = POP<EE>();
3896  T::setMemPtr(addr);
3897  setPC(addr);
3898  return {0/*1*/, T::CC_RET_A + EE};
3899  } else {
3900  return {1, T::CC_RET_B + EE};
3901  }
3902 }
3903 template<class T> template<typename COND> II CPUCore<T>::ret(COND cond) {
3904  return RET<T::EE_RET_C>(cond);
3905 }
3906 template<class T> II CPUCore<T>::ret() {
3907  return RET<0>(CondTrue());
3908 }
3909 template<class T> II CPUCore<T>::retn() { // also reti
3910  setIFF1(getIFF2());
3911  setSlowInstructions();
3912  return RET<T::EE_RETN>(CondTrue());
3913 }
3914 
3915 
3916 // JP ss
3917 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::jp_SS() {
3918  setPC(get16<REG>()); T::R800ForcePageBreak(); return {0/*1*/, T::CC_JP_HL + EE};
3919 }
3920 
3921 // JP nn / JP cc,nn
3922 template<class T> template<typename COND> II CPUCore<T>::jp(COND cond) {
3923  unsigned addr = RD_WORD_PC<1>(T::CC_JP_1);
3924  T::setMemPtr(addr);
3925  if (cond(getF())) {
3926  setPC(addr);
3927  T::R800ForcePageBreak();
3928  return {0/*3*/, T::CC_JP_A};
3929  } else {
3930  return {3, T::CC_JP_B};
3931  }
3932 }
3933 
3934 // JR e
3935 template<class T> template<typename COND> II CPUCore<T>::jr(COND cond) {
3936  int8_t ofst = RDMEM_OPCODE<1>(T::CC_JR_1);
3937  if (cond(getF())) {
3938  if (((getPC() + 2) & 0xFF) == 0) {
3939  // On R800, when this instruction is located in the
3940  // last two byte of a page (a page is a 256-byte
3941  // (aligned) memory block) and even if we jump back,
3942  // thus fetching the next opcode byte does not cause a
3943  // page-break, there still is one cycle overhead. It's
3944  // as-if there is a page-break.
3945  //
3946  // This could be explained by some (very limited)
3947  // pipeline behaviour in R800: it seems that the
3948  // decision to cause a page-break on the next
3949  // instruction is already made before the jump
3950  // destination address for the current instruction is
3951  // calculated (though a destination address in another
3952  // page is also a reason for a page-break).
3953  //
3954  // It's likely all instructions behave like this, but I
3955  // think we can get away with only explicitly emulating
3956  // this behaviour in the djnz and the jr (conditional
3957  // or not) instructions: all other instructions that
3958  // cause the PC to change in a non-incremental way do
3959  // already force a pagebreak for another reason, so
3960  // this effect is masked. Examples of such instructions
3961  // are: JP, RET, CALL, RST, all repeated block
3962  // instructions, accepting an IRQ, (are there more
3963  // instructions or events that change PC?)
3964  //
3965  // See doc/r800-djnz.txt for more details.
3966  T::R800ForcePageBreak();
3967  }
3968  setPC((getPC() + 2 + ofst) & 0xFFFF);
3969  T::setMemPtr(getPC());
3970  return {0/*2*/, T::CC_JR_A};
3971  } else {
3972  return {2, T::CC_JR_B};
3973  }
3974 }
3975 
3976 // DJNZ e
3977 template<class T> II CPUCore<T>::djnz() {
3978  byte b = getB() - 1;
3979  setB(b);
3980  int8_t ofst = RDMEM_OPCODE<1>(T::CC_JR_1 + T::EE_DJNZ);
3981  if (b) {
3982  if (((getPC() + 2) & 0xFF) == 0) {
3983  // See comment in jr()
3984  T::R800ForcePageBreak();
3985  }
3986  setPC((getPC() + 2 + ofst) & 0xFFFF);
3987  T::setMemPtr(getPC());
3988  return {0/*2*/, T::CC_JR_A + T::EE_DJNZ};
3989  } else {
3990  return {2, T::CC_JR_B + T::EE_DJNZ};
3991  }
3992 }
3993 
3994 // EX (SP),ss
3995 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ex_xsp_SS() {
3996  unsigned res = RD_WORD_impl<true, false>(getSP(), T::CC_EX_SP_HL_1 + EE);
3997  T::setMemPtr(res);
3998  WR_WORD_rev<false, true>(getSP(), get16<REG>(), T::CC_EX_SP_HL_2 + EE);
3999  set16<REG>(res);
4000  return {1, T::CC_EX_SP_HL + EE};
4001 }
4002 
4003 // IN r,(c)
4004 template<class T> template<Reg8 REG> II CPUCore<T>::in_R_c() {
4005  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_R_C_1);
4006  T::setMemPtr(getBC() + 1);
4007  byte res = READ_PORT(getBC(), T::CC_IN_R_C_1);
4008  byte f = 0;
4009  if (T::isR800()) {
4010  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4011  f |= table.ZSP[res];
4012  } else {
4013  f |= getF() & C_FLAG;
4014  f |= table.ZSPXY[res];
4015  }
4016  setF(f);
4017  set8<REG>(res);
4018  return {1, T::CC_IN_R_C};
4019 }
4020 
4021 // IN a,(n)
4022 template<class T> II CPUCore<T>::in_a_byte() {
4023  unsigned y = RDMEM_OPCODE<1>(T::CC_IN_A_N_1) + 256 * getA();
4024  T::setMemPtr(y + 1);
4025  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_A_N_2);
4026  setA(READ_PORT(y, T::CC_IN_A_N_2));
4027  return {2, T::CC_IN_A_N};
4028 }
4029 
4030 // OUT (c),r
4031 template<class T> template<Reg8 REG> II CPUCore<T>::out_c_R() {
4032  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4033  T::setMemPtr(getBC() + 1);
4034  WRITE_PORT(getBC(), get8<REG>(), T::CC_OUT_C_R_1);
4035  return {1, T::CC_OUT_C_R};
4036 }
4037 template<class T> II CPUCore<T>::out_c_0() {
4038  // TODO not on R800
4039  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4040  T::setMemPtr(getBC() + 1);
4041  byte out_c_x = isTurboR ? 255 : 0;
4042  WRITE_PORT(getBC(), out_c_x, T::CC_OUT_C_R_1);
4043  return {1, T::CC_OUT_C_R};
4044 }
4045 
4046 // OUT (n),a
4047 template<class T> II CPUCore<T>::out_byte_a() {
4048  byte port = RDMEM_OPCODE<1>(T::CC_OUT_N_A_1);
4049  unsigned y = (getA() << 8) | port;
4050  T::setMemPtr((getA() << 8) | ((port + 1) & 255));
4051  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_N_A_2);
4052  WRITE_PORT(y, getA(), T::CC_OUT_N_A_2);
4053  return {2, T::CC_OUT_N_A};
4054 }
4055 
4056 
4057 // block CP
4058 template<class T> inline II CPUCore<T>::BLOCK_CP(int increase, bool repeat) {
4059  T::setMemPtr(T::getMemPtr() + increase);
4060  byte val = RDMEM(getHL(), T::CC_CPI_1);
4061  byte res = getA() - val;
4062  setHL(getHL() + increase);
4063  setBC(getBC() - 1);
4064  byte f = ((getA() ^ val ^ res) & H_FLAG) |
4065  table.ZS[res] |
4066  N_FLAG |
4067  (getBC() ? V_FLAG : 0);
4068  if (T::isR800()) {
4069  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4070  } else {
4071  f |= getF() & C_FLAG;
4072  unsigned k = res - ((f & H_FLAG) >> 4);
4073  f |= (k << 4) & Y_FLAG; // bit 1 -> flag 5
4074  f |= k & X_FLAG; // bit 3 -> flag 3
4075  }
4076  setF(f);
4077  if (repeat && getBC() && res) {
4078  //setPC(getPC() - 2);
4079  T::setMemPtr(getPC() + 1);
4080  return {-1/*1*/, T::CC_CPIR};
4081  } else {
4082  return {1, T::CC_CPI};
4083  }
4084 }
4085 template<class T> II CPUCore<T>::cpd() { return BLOCK_CP(-1, false); }
4086 template<class T> II CPUCore<T>::cpi() { return BLOCK_CP( 1, false); }
4087 template<class T> II CPUCore<T>::cpdr() { return BLOCK_CP(-1, true ); }
4088 template<class T> II CPUCore<T>::cpir() { return BLOCK_CP( 1, true ); }
4089 
4090 
4091 // block LD
4092 template<class T> inline II CPUCore<T>::BLOCK_LD(int increase, bool repeat) {
4093  byte val = RDMEM(getHL(), T::CC_LDI_1);
4094  WRMEM(getDE(), val, T::CC_LDI_2);
4095  setHL(getHL() + increase);
4096  setDE(getDE() + increase);
4097  setBC(getBC() - 1);
4098  byte f = getBC() ? V_FLAG : 0;
4099  if (T::isR800()) {
4100  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG | X_FLAG | Y_FLAG);
4101  } else {
4102  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG);
4103  f |= ((getA() + val) << 4) & Y_FLAG; // bit 1 -> flag 5
4104  f |= (getA() + val) & X_FLAG; // bit 3 -> flag 3
4105  }
4106  setF(f);
4107  if (repeat && getBC()) {
4108  //setPC(getPC() - 2);
4109  T::setMemPtr(getPC() + 1);
4110  return {-1/*1*/, T::CC_LDIR};
4111  } else {
4112  return {1, T::CC_LDI};
4113  }
4114 }
4115 template<class T> II CPUCore<T>::ldd() { return BLOCK_LD(-1, false); }
4116 template<class T> II CPUCore<T>::ldi() { return BLOCK_LD( 1, false); }
4117 template<class T> II CPUCore<T>::lddr() { return BLOCK_LD(-1, true ); }
4118 template<class T> II CPUCore<T>::ldir() { return BLOCK_LD( 1, true ); }
4119 
4120 
4121 // block IN
4122 template<class T> inline II CPUCore<T>::BLOCK_IN(int increase, bool repeat) {
4123  // TODO R800 flags
4124  if (T::isR800()) T::waitForEvenCycle(T::CC_INI_1);
4125  T::setMemPtr(getBC() + increase);
4126  setBC(getBC() - 0x100); // decr before use
4127  byte val = READ_PORT(getBC(), T::CC_INI_1);
4128  WRMEM(getHL(), val, T::CC_INI_2);
4129  setHL(getHL() + increase);
4130  unsigned k = val + ((getC() + increase) & 0xFF);
4131  byte b = getB();
4132  setF(((val & S_FLAG) >> 6) | // N_FLAG
4133  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4134  table.ZSXY[b] |
4135  (table.ZSPXY[(k & 0x07) ^ b] & P_FLAG));
4136  if (repeat && b) {
4137  //setPC(getPC() - 2);
4138  return {-1/*1*/, T::CC_INIR};
4139  } else {
4140  return {1, T::CC_INI};
4141  }
4142 }
4143 template<class T> II CPUCore<T>::ind() { return BLOCK_IN(-1, false); }
4144 template<class T> II CPUCore<T>::ini() { return BLOCK_IN( 1, false); }
4145 template<class T> II CPUCore<T>::indr() { return BLOCK_IN(-1, true ); }
4146 template<class T> II CPUCore<T>::inir() { return BLOCK_IN( 1, true ); }
4147 
4148 
4149 // block OUT
4150 template<class T> inline II CPUCore<T>::BLOCK_OUT(int increase, bool repeat) {
4151  // TODO R800 flags
4152  byte val = RDMEM(getHL(), T::CC_OUTI_1);
4153  setHL(getHL() + increase);
4154  if (T::isR800()) T::waitForEvenCycle(T::CC_OUTI_2);
4155  WRITE_PORT(getBC(), val, T::CC_OUTI_2);
4156  setBC(getBC() - 0x100); // decr after use
4157  T::setMemPtr(getBC() + increase);
4158  unsigned k = val + getL();
4159  byte b = getB();
4160  setF(((val & S_FLAG) >> 6) | // N_FLAG
4161  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4162  table.ZSXY[b] |
4163  (table.ZSPXY[(k & 0x07) ^ b] & P_FLAG));
4164  if (repeat && b) {
4165  //setPC(getPC() - 2);
4166  return {-1/*1*/, T::CC_OTIR};
4167  } else {
4168  return {1, T::CC_OUTI};
4169  }
4170 }
4171 template<class T> II CPUCore<T>::outd() { return BLOCK_OUT(-1, false); }
4172 template<class T> II CPUCore<T>::outi() { return BLOCK_OUT( 1, false); }
4173 template<class T> II CPUCore<T>::otdr() { return BLOCK_OUT(-1, true ); }
4174 template<class T> II CPUCore<T>::otir() { return BLOCK_OUT( 1, true ); }
4175 
4176 
4177 // various
4178 template<class T> II CPUCore<T>::nop() { return {1, T::CC_NOP}; }
4179 template<class T> II CPUCore<T>::ccf() {
4180  byte f = 0;
4181  if (T::isR800()) {
4182  // H flag is different from Z80 (and as always XY flags as well)
4183  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | X_FLAG | Y_FLAG | H_FLAG);
4184  } else {
4185  f |= (getF() & C_FLAG) << 4; // H_FLAG
4186  // only set X(Y) flag (don't reset if already set)
4187  if (isTurboR) {
4188  // Y flag is not changed on a turboR-Z80
4189  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | Y_FLAG);
4190  f |= (getF() | getA()) & X_FLAG;
4191  } else {
4192  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4193  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4194  }
4195  }
4196  f ^= C_FLAG;
4197  setF(f);
4198  return {1, T::CC_CCF};
4199 }
4200 template<class T> II CPUCore<T>::cpl() {
4201  setA(getA() ^ 0xFF);
4202  byte f = H_FLAG | N_FLAG;
4203  if (T::isR800()) {
4204  f |= getF();
4205  } else {
4206  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4207  f |= getA() & (X_FLAG | Y_FLAG);
4208  }
4209  setF(f);
4210  return {1, T::CC_CPL};
4211 }
4212 template<class T> II CPUCore<T>::daa() {
4213  byte a = getA();
4214  byte f = getF();
4215  byte adjust = 0;
4216  if ((f & H_FLAG) || ((getA() & 0xf) > 9)) adjust += 6;
4217  if ((f & C_FLAG) || (getA() > 0x99)) adjust += 0x60;
4218  if (f & N_FLAG) a -= adjust; else a += adjust;
4219  if (T::isR800()) {
4220  f &= C_FLAG | N_FLAG | X_FLAG | Y_FLAG;
4221  f |= table.ZSP[a];
4222  } else {
4223  f &= C_FLAG | N_FLAG;
4224  f |= table.ZSPXY[a];
4225  }
4226  f |= (getA() > 0x99) | ((getA() ^ a) & H_FLAG);
4227  setA(a);
4228  setF(f);
4229  return {1, T::CC_DAA};
4230 }
4231 template<class T> II CPUCore<T>::neg() {
4232  // alternative: LUT word negTable[256]
4233  unsigned a = getA();
4234  unsigned res = -signed(a);
4235  byte f = ((res & 0x100) ? C_FLAG : 0) |
4236  N_FLAG |
4237  ((res ^ a) & H_FLAG) |
4238  ((a & res & 0x80) >> 5); // V_FLAG
4239  if (T::isR800()) {
4240  f |= table.ZS[res & 0xFF];
4241  f |= getF() & (X_FLAG | Y_FLAG);
4242  } else {
4243  f |= table.ZSXY[res & 0xFF];
4244  }
4245  setF(f);
4246  setA(res);
4247  return {1, T::CC_NEG};
4248 }
4249 template<class T> II CPUCore<T>::scf() {
4250  byte f = C_FLAG;
4251  if (T::isR800()) {
4252  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
4253  } else {
4254  // only set X(Y) flag (don't reset if already set)
4255  if (isTurboR) {
4256  // Y flag is not changed on a turboR-Z80
4257  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | Y_FLAG);
4258  f |= (getF() | getA()) & X_FLAG;
4259  } else {
4260  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
4261  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4262  }
4263  }
4264  setF(f);
4265  return {1, T::CC_SCF};
4266 }
4267 
4268 template<class T> II CPUCore<T>::ex_af_af() {
4269  unsigned t = getAF2(); setAF2(getAF()); setAF(t);
4270  return {1, T::CC_EX};
4271 }
4272 template<class T> II CPUCore<T>::ex_de_hl() {
4273  unsigned t = getDE(); setDE(getHL()); setHL(t);
4274  return {1, T::CC_EX};
4275 }
4276 template<class T> II CPUCore<T>::exx() {
4277  unsigned t1 = getBC2(); setBC2(getBC()); setBC(t1);
4278  unsigned t2 = getDE2(); setDE2(getDE()); setDE(t2);
4279  unsigned t3 = getHL2(); setHL2(getHL()); setHL(t3);
4280  return {1, T::CC_EX};
4281 }
4282 
4283 template<class T> II CPUCore<T>::di() {
4284  setIFF1(false);
4285  setIFF2(false);
4286  return {1, T::CC_DI};
4287 }
4288 template<class T> II CPUCore<T>::ei() {
4289  setIFF1(true);
4290  setIFF2(true);
4291  setCurrentEI(); // no ints directly after this instr
4292  setSlowInstructions();
4293  return {1, T::CC_EI};
4294 }
4295 template<class T> II CPUCore<T>::halt() {
4296  setHALT(true);
4297  setSlowInstructions();
4298 
4299  if (!(getIFF1() || getIFF2())) {
4300  diHaltCallback.execute();
4301  }
4302  return {1, T::CC_HALT};
4303 }
4304 template<class T> template<unsigned N> II CPUCore<T>::im_N() {
4305  setIM(N); return {1, T::CC_IM};
4306 }
4307 
4308 // LD A,I/R
4309 template<class T> template<Reg8 REG> II CPUCore<T>::ld_a_IR() {
4310  setA(get8<REG>());
4311  byte f = getIFF2() ? V_FLAG : 0;
4312  if (T::isR800()) {
4313  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4314  f |= table.ZS[getA()];
4315  } else {
4316  f |= getF() & C_FLAG;
4317  f |= table.ZSXY[getA()];
4318  // see comment in the IRQ acceptance part of executeSlow().
4319  setCurrentLDAI(); // only Z80 (not R800) has this quirk
4320  setSlowInstructions();
4321  }
4322  setF(f);
4323  return {1, T::CC_LD_A_I};
4324 }
4325 
4326 // LD I/R,A
4327 template<class T> II CPUCore<T>::ld_r_a() {
4328  // This code sequence:
4329  // XOR A / LD R,A / LD A,R
4330  // gives A=2 for Z80, but A=1 for R800. The difference can possibly be
4331  // explained by a difference in the relative time between writing the
4332  // new value to the R register and increasing the R register per M1
4333  // cycle. Here we implemented the R800 behaviour by storing 'A-1' into
4334  // R, that's good enough for now.
4335  byte val = getA();
4336  if (T::isR800()) val -= 1;
4337  setR(val);
4338  return {1, T::CC_LD_A_I};
4339 }
4340 template<class T> II CPUCore<T>::ld_i_a() {
4341  setI(getA());
4342  return {1, T::CC_LD_A_I};
4343 }
4344 
4345 // MULUB A,r
4346 template<class T> template<Reg8 REG> II CPUCore<T>::mulub_a_R() {
4347  assert(T::isR800()); // this instruction is R800-only
4348  // Verified on real R800:
4349  // YHXN flags are unchanged
4350  // SV flags are reset
4351  // Z flag is set when result is zero
4352  // C flag is set when result doesn't fit in 8-bit
4353  setHL(unsigned(getA()) * get8<REG>());
4354  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4355  0 | // S_FLAG V_FLAG
4356  (getHL() ? 0 : Z_FLAG) |
4357  ((getHL() & 0xFF00) ? C_FLAG : 0));
4358  return {1, T::CC_MULUB};
4359 }
4360 
4361 // MULUW HL,ss
4362 template<class T> template<Reg16 REG> II CPUCore<T>::muluw_hl_SS() {
4363  assert(T::isR800()); // this instruction is R800-only
4364  // Verified on real R800:
4365  // YHXN flags are unchanged
4366  // SV flags are reset
4367  // Z flag is set when result is zero
4368  // C flag is set when result doesn't fit in 16-bit
4369  unsigned res = unsigned(getHL()) * get16<REG>();
4370  setDE(res >> 16);
4371  setHL(res & 0xffff);
4372  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4373  0 | // S_FLAG V_FLAG
4374  (res ? 0 : Z_FLAG) |
4375  ((res & 0xFFFF0000) ? C_FLAG : 0));
4376  return {1, T::CC_MULUW};
4377 }
4378 
4379 
4380 // versions:
4381 // 1 -> initial version
4382 // 2 -> moved memptr from here to Z80TYPE (and not to R800TYPE)
4383 // 3 -> timing of the emulation changed (no changes in serialization)
4384 // 4 -> timing of the emulation changed again (see doc/internal/r800-call.txt)
4385 // 5 -> added serialization of nmiEdge
4386 template<class T> template<typename Archive>
4387 void CPUCore<T>::serialize(Archive& ar, unsigned version)
4388 {
4389  T::serialize(ar, version);
4390  ar.serialize("regs", static_cast<CPURegs&>(*this));
4391  if (ar.versionBelow(version, 2)) {
4392  unsigned mptr = 0; // dummy value (avoid warning)
4393  ar.serialize("memptr", mptr);
4394  T::setMemPtr(mptr);
4395  }
4396 
4397  if (ar.versionBelow(version, 5)) {
4398  // NMI is unused on MSX and even on systems where it is used nmiEdge
4399  // is true only between the moment the NMI request comes in and the
4400  // moment the Z80 jumps to the NMI handler, so defaulting to false
4401  // is pretty safe.
4402  nmiEdge = false;
4403  } else {
4404  // CPU is deserialized after devices, so nmiEdge is restored to the
4405  // saved version even if IRQHelpers set it on deserialization.
4406  ar.serialize("nmiEdge", nmiEdge);
4407  }
4408 
4409  if (ar.isLoader()) {
4410  invalidateMemCache(0x0000, 0x10000);
4411  }
4412 
4413  // Don't serialize:
4414  // - IRQStatus, NMIStatus:
4415  // the IRQHelper deserialization makes sure these get the right value
4416  // - slowInstructions, exitLoop:
4417  // serialization happens outside the CPU emulation loop
4418 
4419  if (T::isR800() && ar.versionBelow(version, 4)) {
4420  motherboard.getMSXCliComm().printWarning(
4421  "Loading an old savestate: the timing of the R800 "
4422  "emulation has changed. This may cause synchronization "
4423  "problems in replay.");
4424  }
4425 }
4426 
4427 // Force template instantiation
4428 template class CPUCore<Z80TYPE>;
4429 template class CPUCore<R800TYPE>;
4430 
4433 
4434 } // namespace openmsx
#define CASE(X)
static const int CLOCK_FREQ
Definition: R800.hh:33
#define NEVER_INLINE
Definition: inline.hh:17
#define ALWAYS_INLINE
Definition: inline.hh:16
#define unlikely(x)
Definition: likely.hh:15
Definition: span.hh:34
uint8_t byte
8 bit unsigned integer
Definition: openmsx.hh:26
unsigned dasm(const MSXCPUInterface &interf, word pc, byte buf[4], std::string &dest, EmuTime::param time)
Disassemble.
Definition: Dasm.cc:18
CPUCore(MSXMotherBoard &motherboard, const std::string &name, const BooleanSetting &traceSetting, TclCallback &diHaltCallback, EmuTime::param time)
Definition: CPUCore.cc:299
bool operator()(byte f) const
Definition: CPUCore.cc:289
byte ZS[256]
Definition: CPUCore.cc:237
bool operator()(byte f) const
Definition: CPUCore.cc:290
#define NEXT
#define NEXT_STOP
int cycles
Definition: CPUCore.hh:39
byte ZSPH[256]
Definition: CPUCore.cc:241
bool operator()(byte) const
Definition: CPUCore.cc:297
Thanks to enen for testing this on a real cartridge:
Definition: Autofire.cc:5
bool operator()(byte f) const
Definition: CPUCore.cc:296
static const int CLOCK_FREQ
Definition: Z80.hh:17
uint16_t word
16 bit unsigned integer
Definition: openmsx.hh:29
void addListElement(T t)
Definition: TclObject.hh:121
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
Definition: serialize.hh:840
bool operator()(byte f) const
Definition: CPUCore.cc:293
bool operator()(byte f) const
Definition: CPUCore.cc:295
bool operator()(byte f) const
Definition: CPUCore.cc:291
byte ZSP[256]
Definition: CPUCore.cc:239
#define NEXT_EI
#define likely(x)
Definition: likely.hh:14
std::string strCat(Ts &&...ts)
Definition: strCat.hh:577
bool operator()(byte f) const
Definition: CPUCore.cc:294
byte ZSXY[256]
Definition: CPUCore.cc:238
constexpr auto size(const C &c) -> decltype(c.size())
Definition: span.hh:62
bool operator()(byte f) const
Definition: CPUCore.cc:292
byte ZSPXY[256]
Definition: CPUCore.cc:240
TclObject t
void serialize(Archive &ar, T &t, unsigned version)
bool isMainThread()
Returns true when called from the main thread.
Definition: Thread.cc:16
#define UNREACHABLE
Definition: unreachable.hh:38