openMSX
CPUCore.cc
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1 // MEMORY EMULATION
2 // ----------------
3 //
4 // Memory access emulation is a very important part of the CPU emulation.
5 // Because they happen so frequently they really need to be executed as fast as
6 // possible otherwise they will completely bring down the speed of the CPU
7 // emulation.
8 //
9 // A very fast way to emulate memory accesses is by simply reading/writing to a
10 // 64kb array (for a 16-bit address space). Unfortunately this doesn't allow
11 // for memory mapped IO (MMIO). These are memory regions where read/writes
12 // trigger side effects, so where we need to execute device-specific code on
13 // read or writes. An alternative that does work with MMIO is for every access
14 // execute a virtual method call, (this is the approach taken by most current
15 // MSX emulators). Unfortunately this is also a lot slower.
16 //
17 // It is possible to combine the speed of array accesses with the flexibility
18 // of virtual methods. In openMSX it's implemened as follows: the 64kb address
19 // space is divided in 256 regions of 256 bytes (called cacheLines in the code
20 // below). For each such region we store a pointer, if this pointer is nullptr
21 // then we have to use the slow way (=virtual method call). If it is not nullptr,
22 // the pointer points to a block of memory that can be directly accessed. In
23 // some contexts accesses via the pointer are known as backdoor accesses while
24 // the accesses directly to the device are known as frontdoor accesses.
25 //
26 // We keep different pointers for read and write accesses. This allows to also
27 // implement ROMs efficiently: read is handled as regular RAM, but writes end
28 // up in some dummy memory region. This region is called 'unmappedWrite' in the
29 // code. There is also a special region 'unmappedRead', this region is filled
30 // with 0xFF and can be used to model (parts of) a device that don't react to
31 // reads (so reads return 0xFF).
32 //
33 // Because of bankswitching (the MSX slot select mechanism, but also e.g.
34 // MegaROM backswitching) the memory map as seen by the Z80 is not static. This
35 // means that the cacheLine pointers also need to change during runtime. To
36 // solve this we made the bankswitch code also responsible for invalidating the
37 // cacheLines of the switched region. These pointers are filled-in again in a
38 // lazy way: the first read or write to a cache line will first get this
39 // pointer (see getReadCacheLine() and getWriteCacheLine() in the code below),
40 // from then on this pointer is used for all further accesses to this region,
41 // until the cache is invalidated again.
42 //
43 //
44 // INSTRUCTION EMULATION
45 // ---------------------
46 //
47 // UPDATE: the 'threaded interpreter model' is not enabled by default
48 // main reason is the huge memory requirement while compiling
49 // and that it doesn't work on non-gcc compilers
50 //
51 // The current implementation is based on a 'threaded interpreter model'. In
52 // the text below I'll call the older implementation the 'traditional
53 // interpreter model'. From a very high level these two models look like this:
54 //
55 // Traditional model:
56 // while (!needExit()) {
57 // byte opcode = fetch(PC++);
58 // switch (opcode) {
59 // case 0x00: nop(); break;
60 // case 0x01: ld_bc_nn(); break;
61 // ...
62 // }
63 // }
64 //
65 // Threaded model:
66 // byte opcode = fetch(PC++); //
67 // goto *(table[opcode]); // fetch-and-dispatch
68 // // note: the goto * syntax is a gcc extension called computed-gotos
69 //
70 // op00: nop(); if (!needExit()) [fetch-and-dispatch];
71 // op01: ld_bc_nn(); if (!needExit()) [fetch-and-dispatch];
72 // ...
73 //
74 // In the first model there is a central place in the code that fetches (the
75 // first byte of) the instruction and based on this byte jumps to the
76 // appropriate routine. In the second model, this fetch-and-dispatch logic is
77 // duplicated at the end of each instruction.
78 //
79 // Typically the 'dispatch' part in above paragraph is implemented (either by
80 // the compiler or manually using computed goto's) via a jump table. Thus on
81 // assembler level via an indirect jump. For the host CPU it's hard to predict
82 // the destination address of such an indirect jump, certainly if there's only
83 // one such jump for all dispatching (the traditional model). If each
84 // instruction has its own indirect jump instruction (the threaded model), it
85 // becomes a bit easier, because often one particular z80 instructions is
86 // followed by a specific other z80 instruction (or one from a small subset).
87 // For example a z80 'cp' instruction is most likely followed by a 'conditional
88 // jump' z80 instruction. Modern CPUs are quite sensitive to
89 // branch-(mis)predictions, so the above optimization helps quite a lot. I
90 // measured a speedup of more than 10%!
91 //
92 // There is another advantage to the threaded model. Because also the
93 // needExit() test is duplicated for each instruction, it becomes possible to
94 // tweak it for individual instructions. But first let me explain this
95 // exit-test in more detail.
96 //
97 // These are the main reasons why the emulator should stop emulating CPU
98 // instructions:
99 // 1) When other devices than the CPU must be emulated (e.g. video frame
100 // rendering). In openMSX this is handled by the Scheduler class and
101 // actually we don't exit the CPU loop (anymore) for this. Instead we
102 // simply execute the device code as a subroutine. Each time right before
103 // we access an IO port or do a frontdoor memory access, there is a check
104 // whether we should emulate device code (search for schedule() in the code
105 // below).
106 // 2) To keep the inner CPU loop as fast as possible we don't check for IRQ,
107 // NMI or HALT status in this loop. Instead this condition is checked only
108 // once at the beginning outside of the loop (if there wasn't a pending IRQ
109 // on the first instruction there also won't be one on the second
110 // instruction, if all we did was emulating cpu instructions). Now when one
111 // of these conditions changes, we must exit the inner loop and re-evaluate
112 // them. For example after an EI instruction we must check the IRQ status
113 // again.
114 // 3) Various reasons like:
115 // * Z80/R800 switch
116 // * executing a Tcl command (could be a cpu-register debug read)
117 // * exit the emulator
118 // 4) 'once-in-a-while': To avoid threading problems and race conditions,
119 // several threads in openMSX only 'schedule' work that will later be
120 // executed by the main emulation thread. The main thread checks for such
121 // task outside of the cpu emulation loop. So once-in-a-while we need to
122 // exit the loop. The exact timing doesn't matter here because anyway the
123 // relative timing between threads is undefined.
124 // So for 1) we don't need to do anything (we don't actually exit). For 2) and
125 // 3) we need the exit the loop as soon as possible (right after the current
126 // instruction is finished). For 4) it's OK to exit 'eventually' (a few hundred
127 // z80 instructions late is still OK).
128 //
129 // Condition 2) is implemented with the 'slowInstructions' mechanism. Condition
130 // 3) via exitCPULoopSync() (may only get called by the main emulation thread)
131 // and condition 4) is implemented via exitCPULoopAsync() (can be called from
132 // any thread).
133 //
134 // Now back to the exit-test optimization: in the threaded model each
135 // instruction ends with:
136 //
137 // if (needExit()) return
138 // byte opcode = fetch(PC++);
139 // goto *(table[opcode]);
140 //
141 // And if we look in more detail at fetch():
142 //
143 // if (canDoBackdoor(addr)) {
144 // doBackdoorAccess(addr);
145 // } else {
146 // doFrontdoorAccess(addr);
147 // }
148 //
149 // So there are in fact two checks per instruction. This can be reduced to only
150 // one check with the following trick:
151 //
152 // !!!WRONG!!!
153 // In the past we optimized this to only check canDoBackdoor() (and make sure
154 // canDoBackdoor() returned false when needExit() would return true). This
155 // worked rather well, except for one case: when we exit the CPU loop we also
156 // check for pending Syncronization points. It is possible such a SyncPoint
157 // raises the IRQ line. So it is important to check for exit after every
158 // instruction, otherwise we would enter the IRQ routine a couple of
159 // instructions too late.
160 
161 #include "CPUCore.hh"
162 #include "MSXCPUInterface.hh"
163 #include "Scheduler.hh"
164 #include "MSXMotherBoard.hh"
165 #include "CliComm.hh"
166 #include "TclCallback.hh"
167 #include "Dasm.hh"
168 #include "Z80.hh"
169 #include "R800.hh"
170 #include "Thread.hh"
171 #include "cstd.hh"
172 #include "endian.hh"
173 #include "likely.hh"
174 #include "inline.hh"
175 #include "unreachable.hh"
176 #include <iomanip>
177 #include <iostream>
178 #include <type_traits>
179 #include <cassert>
180 #include <cstring>
181 
182 
183 //
184 // #define USE_COMPUTED_GOTO
185 //
186 // Computed goto's are not enabled by default:
187 // - Computed goto's are a gcc extension, it's not part of the official c++
188 // standard. So this will only work if you use gcc as your compiler (it
189 // won't work with visual c++ for example)
190 // - This is only beneficial on CPUs with branch prediction for indirect jumps
191 // and a reasonable amout of cache. For example it is very benefical for a
192 // intel core2 cpu (10% faster), but not for a ARM920 (a few percent slower)
193 // - Compiling src/cpu/CPUCore.cc with computed goto's enabled is very demanding
194 // on the compiler. On older gcc versions it requires up to 1.5GB of memory.
195 // But even on more recent gcc versions it still requires around 700MB.
196 //
197 // Probably the easiest way to enable this, is to pass the -DUSE_COMPUTED_GOTO
198 // flag to the compiler. This is for example done in the super-opt flavour.
199 // See build/flavour-super-opt.mk
200 
201 
202 using std::string;
203 
204 namespace openmsx {
205 
206 // This actually belongs in Z80.cc and R800.cc (these files don't exist yet).
207 // As a quick hack I put these two lines here because I found it overkill to
208 // create two files each containing only a single line.
209 // Technically these two lines _are_ required according to the c++ standard.
210 // Though usually it works just find without them, but during experiments I did
211 // get a link error when these lines were missing (it only happened during a
212 // debug build with some specific compiler version and only with some
213 // combination of other code changes, but again when strictly following the
214 // language rules, these lines should be here).
215 // ... But visual studio is not fully standard compliant, see also comment
216 // in SectorAccesibleDisk.cc
217 #ifndef _MSC_VER
218 const int Z80TYPE ::CLOCK_FREQ;
219 const int R800TYPE::CLOCK_FREQ;
220 #endif
221 
222 enum Reg8 : int { A, F, B, C, D, E, H, L, IXH, IXL, IYH, IYL, REG_I, REG_R, DUMMY };
223 enum Reg16 : int { AF, BC, DE, HL, IX, IY, SP };
224 
225 // flag positions
226 static const byte S_FLAG = 0x80;
227 static const byte Z_FLAG = 0x40;
228 static const byte Y_FLAG = 0x20;
229 static const byte H_FLAG = 0x10;
230 static const byte X_FLAG = 0x08;
231 static const byte V_FLAG = 0x04;
232 static const byte P_FLAG = V_FLAG;
233 static const byte N_FLAG = 0x02;
234 static const byte C_FLAG = 0x01;
235 
236 // flag-register lookup tables
237 struct Table {
238  byte ZS [256];
239  byte ZSXY [256];
240  byte ZSP [256];
241  byte ZSPXY[256];
242  byte ZSPH [256];
243 };
244 
245 static const byte ZS0 = Z_FLAG;
246 static const byte ZSXY0 = Z_FLAG;
247 static const byte ZSP0 = Z_FLAG | V_FLAG;
248 static const byte ZSPXY0 = Z_FLAG | V_FLAG;
249 static const byte ZS255 = S_FLAG;
250 static const byte ZSXY255 = S_FLAG | X_FLAG | Y_FLAG;
251 
252 static CONSTEXPR Table initTables()
253 {
254  Table table = {};
255 
256  for (int i = 0; i < 256; ++i) {
257  byte zFlag = (i == 0) ? Z_FLAG : 0;
258  byte sFlag = i & S_FLAG;
259  byte xFlag = i & X_FLAG;
260  byte yFlag = i & Y_FLAG;
261  byte vFlag = V_FLAG;
262  for (int v = 128; v != 0; v >>= 1) {
263  if (i & v) vFlag ^= V_FLAG;
264  }
265  table.ZS [i] = zFlag | sFlag;
266  table.ZSXY [i] = zFlag | sFlag | xFlag | yFlag;
267  table.ZSP [i] = zFlag | sFlag | vFlag;
268  table.ZSPXY[i] = zFlag | sFlag | xFlag | yFlag | vFlag;
269  table.ZSPH [i] = zFlag | sFlag | vFlag | H_FLAG;
270  }
271  assert(table.ZS [ 0] == ZS0);
272  assert(table.ZSXY [ 0] == ZSXY0);
273  assert(table.ZSP [ 0] == ZSP0);
274  assert(table.ZSPXY[ 0] == ZSPXY0);
275  assert(table.ZS [255] == ZS255);
276  assert(table.ZSXY [255] == ZSXY255);
277 
278  return table;
279 }
280 
281 static CONSTEXPR Table table = initTables();
282 
283 // Global variable, because it should be shared between Z80 and R800.
284 // It must not be shared between the CPUs of different MSX machines, but
285 // the (logical) lifetime of this variable cannot overlap between execution
286 // of two MSX machines.
287 static word start_pc;
288 
289 // conditions
290 struct CondC { bool operator()(byte f) const { return (f & C_FLAG) != 0; } };
291 struct CondNC { bool operator()(byte f) const { return !(f & C_FLAG); } };
292 struct CondZ { bool operator()(byte f) const { return (f & Z_FLAG) != 0; } };
293 struct CondNZ { bool operator()(byte f) const { return !(f & Z_FLAG); } };
294 struct CondM { bool operator()(byte f) const { return (f & S_FLAG) != 0; } };
295 struct CondP { bool operator()(byte f) const { return !(f & S_FLAG); } };
296 struct CondPE { bool operator()(byte f) const { return (f & V_FLAG) != 0; } };
297 struct CondPO { bool operator()(byte f) const { return !(f & V_FLAG); } };
298 struct CondTrue { bool operator()(byte) const { return true; } };
299 
300 template<class T> CPUCore<T>::CPUCore(
301  MSXMotherBoard& motherboard_, const string& name,
302  const BooleanSetting& traceSetting_,
303  TclCallback& diHaltCallback_, EmuTime::param time)
304  : CPURegs(T::isR800())
305  , T(time, motherboard_.getScheduler())
306  , motherboard(motherboard_)
307  , scheduler(motherboard.getScheduler())
308  , interface(nullptr)
309  , traceSetting(traceSetting_)
310  , diHaltCallback(diHaltCallback_)
311  , IRQStatus(motherboard.getDebugger(), name + ".pendingIRQ",
312  "Non-zero if there are pending IRQs (thus CPU would enter "
313  "interrupt routine in EI mode).",
314  0)
315  , IRQAccept(motherboard.getDebugger(), name + ".acceptIRQ",
316  "This probe is only useful to set a breakpoint on (the value "
317  "return by read is meaningless). The breakpoint gets triggered "
318  "right after the CPU accepted an IRQ.")
319  , freqLocked(
320  motherboard.getCommandController(), name + "_freq_locked",
321  "real (locked) or custom (unlocked) " + name + " frequency",
322  true)
323  , freqValue(
324  motherboard.getCommandController(), name + "_freq",
325  "custom " + name + " frequency (only valid when unlocked)",
326  T::CLOCK_FREQ, 1000000, 1000000000)
327  , freq(T::CLOCK_FREQ)
328  , NMIStatus(0)
329  , nmiEdge(false)
330  , exitLoop(false)
331  , tracingEnabled(traceSetting.getBoolean())
332  , isTurboR(motherboard.isTurboR())
333 {
334  static_assert(!std::is_polymorphic<CPUCore<T>>::value,
335  "keep CPUCore non-virtual to keep PC at offset 0");
336  doSetFreq();
337  doReset(time);
338 }
339 
340 template<class T> void CPUCore<T>::warp(EmuTime::param time)
341 {
342  assert(T::getTimeFast() <= time);
343  T::setTime(time);
344 }
345 
346 template<class T> EmuTime::param CPUCore<T>::getCurrentTime() const
347 {
348  return T::getTime();
349 }
350 
351 template<class T> void CPUCore<T>::invalidateMemCache(unsigned start, unsigned size)
352 {
353  unsigned first = start / CacheLine::SIZE;
354  unsigned num = (size + CacheLine::SIZE - 1) / CacheLine::SIZE;
355  memset(&readCacheLine [first], 0, num * sizeof(byte*)); // nullptr
356  memset(&writeCacheLine [first], 0, num * sizeof(byte*)); //
357  memset(&readCacheTried [first], 0, num * sizeof(bool)); // FALSE
358  memset(&writeCacheTried[first], 0, num * sizeof(bool)); //
359 }
360 
361 template<class T> void CPUCore<T>::doReset(EmuTime::param time)
362 {
363  // AF and SP are 0xFFFF
364  // PC, R, IFF1, IFF2, HALT and IM are 0x0
365  // all others are random
366  setAF(0xFFFF);
367  setBC(0xFFFF);
368  setDE(0xFFFF);
369  setHL(0xFFFF);
370  setIX(0xFFFF);
371  setIY(0xFFFF);
372  setPC(0x0000);
373  setSP(0xFFFF);
374  setAF2(0xFFFF);
375  setBC2(0xFFFF);
376  setDE2(0xFFFF);
377  setHL2(0xFFFF);
378  setIFF1(false);
379  setIFF2(false);
380  setHALT(false);
381  setExtHALT(false);
382  setIM(0);
383  setI(0x00);
384  setR(0x00);
385  T::setMemPtr(0xFFFF);
386  clearPrevious();
387  invalidateMemCache(0x0000, 0x10000);
388 
389  // We expect this assert to be valid
390  // assert(T::getTimeFast() <= time); // time shouldn't go backwards
391  // But it's disabled for the following reason:
392  // 'motion' (IRC nickname) managed to create a replay file that
393  // contains a reset command that falls in the middle of a Z80
394  // instruction. Replayed commands go via the Scheduler, and are
395  // (typically) executed right after a complete CPU instruction. So
396  // the CPU is (slightly) ahead in time of the about to be executed
397  // reset command.
398  // Normally this situation should never occur: console commands,
399  // hotkeys, commands over clicomm, ... are all handled via the global
400  // event mechanism. Such global events are scheduled between CPU
401  // instructions, so also in a replay they should fall between CPU
402  // instructions.
403  // However if for some reason the timing of the emulation changed
404  // (improved emulation accuracy or a bug so that emulation isn't
405  // deterministic or the replay file was edited, ...), then the above
406  // reasoning no longer holds and the assert can trigger.
407  // We need to be robust against loading older replays (when emulation
408  // timing has changed). So in that respect disabling the assert is
409  // good. Though in the example above (motion's replay) it's not clear
410  // whether the assert is really triggered by mixing an old replay
411  // with a newer openMSX version. In any case so far we haven't been
412  // able to reproduce this assert by recording and replaying using a
413  // single openMSX version.
414  T::setTime(time);
415 
416  assert(NMIStatus == 0); // other devices must reset their NMI source
417  assert(IRQStatus == 0); // other devices must reset their IRQ source
418 }
419 
420 // I believe the following two methods are thread safe even without any
421 // locking. The worst that can happen is that we occasionally needlessly
422 // exit the CPU loop, but that's harmless
423 // TODO thread issues are always tricky, can someone confirm this really
424 // is thread safe
425 template<class T> void CPUCore<T>::exitCPULoopAsync()
426 {
427  // can get called from non-main threads
428  exitLoop = true;
429 }
430 template<class T> void CPUCore<T>::exitCPULoopSync()
431 {
432  assert(Thread::isMainThread());
433  exitLoop = true;
434  T::disableLimit();
435 }
436 template<class T> inline bool CPUCore<T>::needExitCPULoop()
437 {
438  // always executed in main thread
439  if (unlikely(exitLoop)) {
440  // Note: The test-and-set is _not_ atomic! But that's fine.
441  // An atomic implementation is trivial (see below), but
442  // this version (at least on x86) avoids the more expensive
443  // instructions on the likely path.
444  exitLoop = false;
445  return true;
446  }
447  return false;
448 
449  // Alternative implementation:
450  // atomically set to false and return the old value
451  //return exitLoop.exchange(false);
452 }
453 
454 template<class T> void CPUCore<T>::setSlowInstructions()
455 {
456  slowInstructions = 2;
457  T::disableLimit();
458 }
459 
460 template<class T> void CPUCore<T>::raiseIRQ()
461 {
462  assert(IRQStatus >= 0);
463  if (IRQStatus == 0) {
464  setSlowInstructions();
465  }
466  IRQStatus = IRQStatus + 1;
467 }
468 
469 template<class T> void CPUCore<T>::lowerIRQ()
470 {
471  IRQStatus = IRQStatus - 1;
472  assert(IRQStatus >= 0);
473 }
474 
475 template<class T> void CPUCore<T>::raiseNMI()
476 {
477  assert(NMIStatus >= 0);
478  if (NMIStatus == 0) {
479  nmiEdge = true;
480  setSlowInstructions();
481  }
482  NMIStatus++;
483 }
484 
485 template<class T> void CPUCore<T>::lowerNMI()
486 {
487  NMIStatus--;
488  assert(NMIStatus >= 0);
489 }
490 
491 template<class T> bool CPUCore<T>::isM1Cycle(unsigned address) const
492 {
493  // This method should only be called from within a MSXDevice::readMem()
494  // method. It can be used to check whether the current read action has
495  // the M1 pin active. The 'address' parameter that is give to readMem()
496  // should be passed (unchanged) to this method.
497  //
498  // This simple implementation works because the rest of the CPUCore
499  // code is careful to only update the PC register on M1 cycles. In
500  // practice that means that the PC is (only) updated at the very end of
501  // every instruction, even if is a multi-byte instruction. Or for
502  // prefix-instructions the PC is also updated after the prefix is
503  // fetched (because such instructions activate M1 twice).
504  return address == getPC();
505 }
506 
507 template<class T> void CPUCore<T>::wait(EmuTime::param time)
508 {
509  assert(time >= getCurrentTime());
510  scheduler.schedule(time);
511  T::advanceTime(time);
512 }
513 
514 template<class T> EmuTime CPUCore<T>::waitCycles(EmuTime::param time, unsigned cycles)
515 {
516  T::add(cycles);
517  EmuTime time2 = T::calcTime(time, cycles);
518  // note: time2 is not necessarily equal to T::getTime() because of the
519  // way how WRITE_PORT() is implemented.
520  scheduler.schedule(time2);
521  return time2;
522 }
523 
524 template<class T> void CPUCore<T>::setNextSyncPoint(EmuTime::param time)
525 {
526  T::setLimit(time);
527 }
528 
529 
530 static inline char toHex(byte x)
531 {
532  return (x < 10) ? (x + '0') : (x - 10 + 'A');
533 }
534 static void toHex(byte x, char* buf)
535 {
536  buf[0] = toHex(x / 16);
537  buf[1] = toHex(x & 15);
538 }
539 
540 template<class T> void CPUCore<T>::disasmCommand(
541  Interpreter& interp, array_ref<TclObject> tokens, TclObject& result) const
542 {
543  word address = (tokens.size() < 3) ? getPC() : tokens[2].getInt(interp);
544  byte outBuf[4];
545  std::string dasmOutput;
546  unsigned len = dasm(*interface, address, outBuf, dasmOutput,
547  T::getTimeFast());
548  result.addListElement(dasmOutput);
549  char tmp[3]; tmp[2] = 0;
550  for (unsigned i = 0; i < len; ++i) {
551  toHex(outBuf[i], tmp);
552  result.addListElement(tmp);
553  }
554 }
555 
556 template<class T> void CPUCore<T>::update(const Setting& setting)
557 {
558  if (&setting == &freqLocked) {
559  doSetFreq();
560  } else if (&setting == &freqValue) {
561  doSetFreq();
562  } else if (&setting == &traceSetting) {
563  tracingEnabled = traceSetting.getBoolean();
564  }
565 }
566 
567 template<class T> void CPUCore<T>::setFreq(unsigned freq_)
568 {
569  freq = freq_;
570  doSetFreq();
571 }
572 
573 template<class T> void CPUCore<T>::doSetFreq()
574 {
575  if (freqLocked.getBoolean()) {
576  // locked, use value set via setFreq()
577  T::setFreq(freq);
578  } else {
579  // unlocked, use value set by user
580  T::setFreq(freqValue.getInt());
581  }
582 }
583 
584 
585 template<class T> inline byte CPUCore<T>::READ_PORT(unsigned port, unsigned cc)
586 {
587  EmuTime time = T::getTimeFast(cc);
588  scheduler.schedule(time);
589  byte result = interface->readIO(port, time);
590  // note: no forced page-break after IO
591  return result;
592 }
593 
594 template<class T> inline void CPUCore<T>::WRITE_PORT(unsigned port, byte value, unsigned cc)
595 {
596  EmuTime time = T::getTimeFast(cc);
597  scheduler.schedule(time);
598  interface->writeIO(port, value, time);
599  // note: no forced page-break after IO
600 }
601 
602 template<class T> template<bool PRE_PB, bool POST_PB>
603 NEVER_INLINE byte CPUCore<T>::RDMEMslow(unsigned address, unsigned cc)
604 {
605  // not cached
606  unsigned high = address >> CacheLine::BITS;
607  if (!readCacheTried[high]) {
608  // try to cache now
609  unsigned addrBase = address & CacheLine::HIGH;
610  if (const byte* line = interface->getReadCacheLine(addrBase)) {
611  // cached ok
612  T::template PRE_MEM<PRE_PB, POST_PB>(address);
613  T::template POST_MEM< POST_PB>(address);
614  readCacheLine[high] = line - addrBase;
615  return readCacheLine[high][address];
616  }
617  }
618  // uncacheable
619  readCacheTried[high] = true;
620  T::template PRE_MEM<PRE_PB, POST_PB>(address);
621  EmuTime time = T::getTimeFast(cc);
622  scheduler.schedule(time);
623  byte result = interface->readMem(address, time);
624  T::template POST_MEM<POST_PB>(address);
625  return result;
626 }
627 template<class T> template<bool PRE_PB, bool POST_PB>
628 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl2(unsigned address, unsigned cc)
629 {
630  const byte* line = readCacheLine[address >> CacheLine::BITS];
631  if (likely(line != nullptr)) {
632  // cached, fast path
633  T::template PRE_MEM<PRE_PB, POST_PB>(address);
634  T::template POST_MEM< POST_PB>(address);
635  return line[address];
636  } else {
637  return RDMEMslow<PRE_PB, POST_PB>(address, cc); // not inlined
638  }
639 }
640 template<class T> template<bool PRE_PB, bool POST_PB>
641 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl(unsigned address, unsigned cc)
642 {
643  static const bool PRE = T::template Normalize<PRE_PB >::value;
644  static const bool POST = T::template Normalize<POST_PB>::value;
645  return RDMEM_impl2<PRE, POST>(address, cc);
646 }
647 template<class T> template<unsigned PC_OFFSET> ALWAYS_INLINE byte CPUCore<T>::RDMEM_OPCODE(unsigned cc)
648 {
649  // Real Z80 would update the PC register now. In this implementation
650  // we've chosen to instead update PC only once at the end of the
651  // instruction. (Of course we made sure this difference is not
652  // noticeable by the program).
653  //
654  // See the comments in isM1Cycle() for the motivation for this
655  // deviation. Apart from that functional aspect it also turns out to be
656  // faster to only update PC once per instruction instead of after each
657  // fetch.
658  unsigned address = (getPC() + PC_OFFSET) & 0xFFFF;
659  return RDMEM_impl<false, false>(address, cc);
660 }
661 template<class T> ALWAYS_INLINE byte CPUCore<T>::RDMEM(unsigned address, unsigned cc)
662 {
663  return RDMEM_impl<true, true>(address, cc);
664 }
665 
666 template<class T> template<bool PRE_PB, bool POST_PB>
667 NEVER_INLINE unsigned CPUCore<T>::RD_WORD_slow(unsigned address, unsigned cc)
668 {
669  unsigned res = RDMEM_impl<PRE_PB, false>(address, cc);
670  res += RDMEM_impl<false, POST_PB>((address + 1) & 0xFFFF, cc + T::CC_RDMEM) << 8;
671  return res;
672 }
673 template<class T> template<bool PRE_PB, bool POST_PB>
674 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl2(unsigned address, unsigned cc)
675 {
676  const byte* line = readCacheLine[address >> CacheLine::BITS];
677  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
678  // fast path: cached and two bytes in same cache line
679  T::template PRE_WORD<PRE_PB, POST_PB>(address);
680  T::template POST_WORD< POST_PB>(address);
681  return Endian::read_UA_L16(&line[address]);
682  } else {
683  // slow path, not inline
684  return RD_WORD_slow<PRE_PB, POST_PB>(address, cc);
685  }
686 }
687 template<class T> template<bool PRE_PB, bool POST_PB>
688 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl(unsigned address, unsigned cc)
689 {
690  static const bool PRE = T::template Normalize<PRE_PB >::value;
691  static const bool POST = T::template Normalize<POST_PB>::value;
692  return RD_WORD_impl2<PRE, POST>(address, cc);
693 }
694 template<class T> template<unsigned PC_OFFSET> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_PC(unsigned cc)
695 {
696  unsigned addr = (getPC() + PC_OFFSET) & 0xFFFF;
697  return RD_WORD_impl<false, false>(addr, cc);
698 }
699 template<class T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD(
700  unsigned address, unsigned cc)
701 {
702  return RD_WORD_impl<true, true>(address, cc);
703 }
704 
705 template<class T> template<bool PRE_PB, bool POST_PB>
706 NEVER_INLINE void CPUCore<T>::WRMEMslow(unsigned address, byte value, unsigned cc)
707 {
708  // not cached
709  unsigned high = address >> CacheLine::BITS;
710  if (!writeCacheTried[high]) {
711  // try to cache now
712  unsigned addrBase = address & CacheLine::HIGH;
713  if (byte* line = interface->getWriteCacheLine(addrBase)) {
714  // cached ok
715  T::template PRE_MEM<PRE_PB, POST_PB>(address);
716  T::template POST_MEM< POST_PB>(address);
717  writeCacheLine[high] = line - addrBase;
718  writeCacheLine[high][address] = value;
719  return;
720  }
721  }
722  // uncacheable
723  writeCacheTried[high] = true;
724  T::template PRE_MEM<PRE_PB, POST_PB>(address);
725  EmuTime time = T::getTimeFast(cc);
726  scheduler.schedule(time);
727  interface->writeMem(address, value, time);
728  T::template POST_MEM<POST_PB>(address);
729 }
730 template<class T> template<bool PRE_PB, bool POST_PB>
732  unsigned address, byte value, unsigned cc)
733 {
734  byte* line = writeCacheLine[address >> CacheLine::BITS];
735  if (likely(line != nullptr)) {
736  // cached, fast path
737  T::template PRE_MEM<PRE_PB, POST_PB>(address);
738  T::template POST_MEM< POST_PB>(address);
739  line[address] = value;
740  } else {
741  WRMEMslow<PRE_PB, POST_PB>(address, value, cc); // not inlined
742  }
743 }
744 template<class T> template<bool PRE_PB, bool POST_PB>
746  unsigned address, byte value, unsigned cc)
747 {
748  static const bool PRE = T::template Normalize<PRE_PB >::value;
749  static const bool POST = T::template Normalize<POST_PB>::value;
750  WRMEM_impl2<PRE, POST>(address, value, cc);
751 }
752 template<class T> ALWAYS_INLINE void CPUCore<T>::WRMEM(
753  unsigned address, byte value, unsigned cc)
754 {
755  WRMEM_impl<true, true>(address, value, cc);
756 }
757 
758 template<class T> NEVER_INLINE void CPUCore<T>::WR_WORD_slow(
759  unsigned address, unsigned value, unsigned cc)
760 {
761  WRMEM_impl<true, false>( address, value & 255, cc);
762  WRMEM_impl<false, true>((address + 1) & 0xFFFF, value >> 8, cc + T::CC_WRMEM);
763 }
764 template<class T> ALWAYS_INLINE void CPUCore<T>::WR_WORD(
765  unsigned address, unsigned value, unsigned cc)
766 {
767  byte* line = writeCacheLine[address >> CacheLine::BITS];
768  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
769  // fast path: cached and two bytes in same cache line
770  T::template PRE_WORD<true, true>(address);
771  T::template POST_WORD< true>(address);
772  Endian::write_UA_L16(&line[address], value);
773  } else {
774  // slow path, not inline
775  WR_WORD_slow(address, value, cc);
776  }
777 }
778 
779 // same as WR_WORD, but writes high byte first
780 template<class T> template<bool PRE_PB, bool POST_PB>
782  unsigned address, unsigned value, unsigned cc)
783 {
784  WRMEM_impl<PRE_PB, false>((address + 1) & 0xFFFF, value >> 8, cc);
785  WRMEM_impl<false, POST_PB>( address, value & 255, cc + T::CC_WRMEM);
786 }
787 template<class T> template<bool PRE_PB, bool POST_PB>
789  unsigned address, unsigned value, unsigned cc)
790 {
791  byte* line = writeCacheLine[address >> CacheLine::BITS];
792  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
793  // fast path: cached and two bytes in same cache line
794  T::template PRE_WORD<PRE_PB, POST_PB>(address);
795  T::template POST_WORD< POST_PB>(address);
796  Endian::write_UA_L16(&line[address], value);
797  } else {
798  // slow path, not inline
799  WR_WORD_rev_slow<PRE_PB, POST_PB>(address, value, cc);
800  }
801 }
802 template<class T> template<bool PRE_PB, bool POST_PB>
804  unsigned address, unsigned value, unsigned cc)
805 {
806  static const bool PRE = T::template Normalize<PRE_PB >::value;
807  static const bool POST = T::template Normalize<POST_PB>::value;
808  WR_WORD_rev2<PRE, POST>(address, value, cc);
809 }
810 
811 
812 // NMI interrupt
813 template<class T> inline void CPUCore<T>::nmi()
814 {
815  incR(1);
816  setHALT(false);
817  setIFF1(false);
818  PUSH<T::EE_NMI_1>(getPC());
819  setPC(0x0066);
820  T::add(T::CC_NMI);
821 }
822 
823 // IM0 interrupt
824 template<class T> inline void CPUCore<T>::irq0()
825 {
826  // TODO current implementation only works for 1-byte instructions
827  // ok for MSX
828  assert(interface->readIRQVector() == 0xFF);
829  incR(1);
830  setHALT(false);
831  setIFF1(false);
832  setIFF2(false);
833  PUSH<T::EE_IRQ0_1>(getPC());
834  setPC(0x0038);
835  T::setMemPtr(getPC());
836  T::add(T::CC_IRQ0);
837 }
838 
839 // IM1 interrupt
840 template<class T> inline void CPUCore<T>::irq1()
841 {
842  incR(1);
843  setHALT(false);
844  setIFF1(false);
845  setIFF2(false);
846  PUSH<T::EE_IRQ1_1>(getPC());
847  setPC(0x0038);
848  T::setMemPtr(getPC());
849  T::add(T::CC_IRQ1);
850 }
851 
852 // IM2 interrupt
853 template<class T> inline void CPUCore<T>::irq2()
854 {
855  incR(1);
856  setHALT(false);
857  setIFF1(false);
858  setIFF2(false);
859  PUSH<T::EE_IRQ2_1>(getPC());
860  unsigned x = interface->readIRQVector() | (getI() << 8);
861  setPC(RD_WORD(x, T::CC_IRQ2_2));
862  T::setMemPtr(getPC());
863  T::add(T::CC_IRQ2);
864 }
865 
866 template<class T>
868 {
869  checkNoCurrentFlags();
870 #ifdef USE_COMPUTED_GOTO
871  // Addresses of all main-opcode routines,
872  // Note that 40/49/53/5B/64/6D/7F is replaced by 00 (ld r,r == nop)
873  static void* opcodeTable[256] = {
874  &&op00, &&op01, &&op02, &&op03, &&op04, &&op05, &&op06, &&op07,
875  &&op08, &&op09, &&op0A, &&op0B, &&op0C, &&op0D, &&op0E, &&op0F,
876  &&op10, &&op11, &&op12, &&op13, &&op14, &&op15, &&op16, &&op17,
877  &&op18, &&op19, &&op1A, &&op1B, &&op1C, &&op1D, &&op1E, &&op1F,
878  &&op20, &&op21, &&op22, &&op23, &&op24, &&op25, &&op26, &&op27,
879  &&op28, &&op29, &&op2A, &&op2B, &&op2C, &&op2D, &&op2E, &&op2F,
880  &&op30, &&op31, &&op32, &&op33, &&op34, &&op35, &&op36, &&op37,
881  &&op38, &&op39, &&op3A, &&op3B, &&op3C, &&op3D, &&op3E, &&op3F,
882  &&op00, &&op41, &&op42, &&op43, &&op44, &&op45, &&op46, &&op47,
883  &&op48, &&op00, &&op4A, &&op4B, &&op4C, &&op4D, &&op4E, &&op4F,
884  &&op50, &&op51, &&op00, &&op53, &&op54, &&op55, &&op56, &&op57,
885  &&op58, &&op59, &&op5A, &&op00, &&op5C, &&op5D, &&op5E, &&op5F,
886  &&op60, &&op61, &&op62, &&op63, &&op00, &&op65, &&op66, &&op67,
887  &&op68, &&op69, &&op6A, &&op6B, &&op6C, &&op00, &&op6E, &&op6F,
888  &&op70, &&op71, &&op72, &&op73, &&op74, &&op75, &&op76, &&op77,
889  &&op78, &&op79, &&op7A, &&op7B, &&op7C, &&op7D, &&op7E, &&op00,
890  &&op80, &&op81, &&op82, &&op83, &&op84, &&op85, &&op86, &&op87,
891  &&op88, &&op89, &&op8A, &&op8B, &&op8C, &&op8D, &&op8E, &&op8F,
892  &&op90, &&op91, &&op92, &&op93, &&op94, &&op95, &&op96, &&op97,
893  &&op98, &&op99, &&op9A, &&op9B, &&op9C, &&op9D, &&op9E, &&op9F,
894  &&opA0, &&opA1, &&opA2, &&opA3, &&opA4, &&opA5, &&opA6, &&opA7,
895  &&opA8, &&opA9, &&opAA, &&opAB, &&opAC, &&opAD, &&opAE, &&opAF,
896  &&opB0, &&opB1, &&opB2, &&opB3, &&opB4, &&opB5, &&opB6, &&opB7,
897  &&opB8, &&opB9, &&opBA, &&opBB, &&opBC, &&opBD, &&opBE, &&opBF,
898  &&opC0, &&opC1, &&opC2, &&opC3, &&opC4, &&opC5, &&opC6, &&opC7,
899  &&opC8, &&opC9, &&opCA, &&opCB, &&opCC, &&opCD, &&opCE, &&opCF,
900  &&opD0, &&opD1, &&opD2, &&opD3, &&opD4, &&opD5, &&opD6, &&opD7,
901  &&opD8, &&opD9, &&opDA, &&opDB, &&opDC, &&opDD, &&opDE, &&opDF,
902  &&opE0, &&opE1, &&opE2, &&opE3, &&opE4, &&opE5, &&opE6, &&opE7,
903  &&opE8, &&opE9, &&opEA, &&opEB, &&opEC, &&opED, &&opEE, &&opEF,
904  &&opF0, &&opF1, &&opF2, &&opF3, &&opF4, &&opF5, &&opF6, &&opF7,
905  &&opF8, &&opF9, &&opFA, &&opFB, &&opFC, &&opFD, &&opFE, &&opFF,
906  };
907 
908 // Check T::limitReached(). If it's OK to continue,
909 // fetch and execute next instruction.
910 #define NEXT \
911  setPC(getPC() + ii.length); \
912  T::add(ii.cycles); \
913  T::R800Refresh(*this); \
914  if (likely(!T::limitReached())) { \
915  incR(1); \
916  unsigned address = getPC(); \
917  const byte* line = readCacheLine[address >> CacheLine::BITS]; \
918  if (likely(line != nullptr)) { \
919  T::template PRE_MEM<false, false>(address); \
920  T::template POST_MEM< false>(address); \
921  byte op = line[address]; \
922  goto *(opcodeTable[op]); \
923  } else { \
924  goto fetchSlow; \
925  } \
926  } \
927  return;
928 
929 // After some instructions we must always exit the CPU loop (ei, halt, retn)
930 #define NEXT_STOP \
931  setPC(getPC() + ii.length); \
932  T::add(ii.cycles); \
933  T::R800Refresh(*this); \
934  assert(T::limitReached()); \
935  return;
936 
937 #define NEXT_EI \
938  setPC(getPC() + ii.length); \
939  T::add(ii.cycles); \
940  /* !! NO T::R800Refresh(*this); !! */ \
941  assert(T::limitReached()); \
942  return;
943 
944 // Define a label (instead of case in a switch statement)
945 #define CASE(X) op##X:
946 
947 #else // USE_COMPUTED_GOTO
948 
949 #define NEXT \
950  setPC(getPC() + ii.length); \
951  T::add(ii.cycles); \
952  T::R800Refresh(*this); \
953  if (likely(!T::limitReached())) { \
954  goto start; \
955  } \
956  return;
957 
958 #define NEXT_STOP \
959  setPC(getPC() + ii.length); \
960  T::add(ii.cycles); \
961  T::R800Refresh(*this); \
962  assert(T::limitReached()); \
963  return;
964 
965 #define NEXT_EI \
966  setPC(getPC() + ii.length); \
967  T::add(ii.cycles); \
968  /* !! NO T::R800Refresh(*this); !! */ \
969  assert(T::limitReached()); \
970  return;
971 
972 #define CASE(X) case 0x##X:
973 
974 #endif // USE_COMPUTED_GOTO
975 
976 #ifndef USE_COMPUTED_GOTO
977 start:
978 #endif
979  unsigned ixy; // for dd_cb/fd_cb
980  byte opcodeMain = RDMEM_OPCODE<0>(T::CC_MAIN);
981  incR(1);
982 #ifdef USE_COMPUTED_GOTO
983  goto *(opcodeTable[opcodeMain]);
984 
985 fetchSlow: {
986  unsigned address = getPC();
987  byte opcodeSlow = RDMEMslow<false, false>(address, T::CC_MAIN);
988  goto *(opcodeTable[opcodeSlow]);
989 }
990 #endif
991 
992 #ifndef USE_COMPUTED_GOTO
993 switchopcode:
994  switch (opcodeMain) {
995 CASE(40) // ld b,b
996 CASE(49) // ld c,c
997 CASE(52) // ld d,d
998 CASE(5B) // ld e,e
999 CASE(64) // ld h,h
1000 CASE(6D) // ld l,l
1001 CASE(7F) // ld a,a
1002 #endif
1003 CASE(00) { II ii = nop(); NEXT; }
1004 CASE(07) { II ii = rlca(); NEXT; }
1005 CASE(0F) { II ii = rrca(); NEXT; }
1006 CASE(17) { II ii = rla(); NEXT; }
1007 CASE(1F) { II ii = rra(); NEXT; }
1008 CASE(08) { II ii = ex_af_af(); NEXT; }
1009 CASE(27) { II ii = daa(); NEXT; }
1010 CASE(2F) { II ii = cpl(); NEXT; }
1011 CASE(37) { II ii = scf(); NEXT; }
1012 CASE(3F) { II ii = ccf(); NEXT; }
1013 CASE(20) { II ii = jr(CondNZ()); NEXT; }
1014 CASE(28) { II ii = jr(CondZ ()); NEXT; }
1015 CASE(30) { II ii = jr(CondNC()); NEXT; }
1016 CASE(38) { II ii = jr(CondC ()); NEXT; }
1017 CASE(18) { II ii = jr(CondTrue()); NEXT; }
1018 CASE(10) { II ii = djnz(); NEXT; }
1019 CASE(32) { II ii = ld_xbyte_a(); NEXT; }
1020 CASE(3A) { II ii = ld_a_xbyte(); NEXT; }
1021 CASE(22) { II ii = ld_xword_SS<HL,0>(); NEXT; }
1022 CASE(2A) { II ii = ld_SS_xword<HL,0>(); NEXT; }
1023 CASE(02) { II ii = ld_SS_a<BC>(); NEXT; }
1024 CASE(12) { II ii = ld_SS_a<DE>(); NEXT; }
1025 CASE(1A) { II ii = ld_a_SS<DE>(); NEXT; }
1026 CASE(0A) { II ii = ld_a_SS<BC>(); NEXT; }
1027 CASE(03) { II ii = inc_SS<BC,0>(); NEXT; }
1028 CASE(13) { II ii = inc_SS<DE,0>(); NEXT; }
1029 CASE(23) { II ii = inc_SS<HL,0>(); NEXT; }
1030 CASE(33) { II ii = inc_SS<SP,0>(); NEXT; }
1031 CASE(0B) { II ii = dec_SS<BC,0>(); NEXT; }
1032 CASE(1B) { II ii = dec_SS<DE,0>(); NEXT; }
1033 CASE(2B) { II ii = dec_SS<HL,0>(); NEXT; }
1034 CASE(3B) { II ii = dec_SS<SP,0>(); NEXT; }
1035 CASE(09) { II ii = add_SS_TT<HL,BC,0>(); NEXT; }
1036 CASE(19) { II ii = add_SS_TT<HL,DE,0>(); NEXT; }
1037 CASE(29) { II ii = add_SS_SS<HL ,0>(); NEXT; }
1038 CASE(39) { II ii = add_SS_TT<HL,SP,0>(); NEXT; }
1039 CASE(01) { II ii = ld_SS_word<BC,0>(); NEXT; }
1040 CASE(11) { II ii = ld_SS_word<DE,0>(); NEXT; }
1041 CASE(21) { II ii = ld_SS_word<HL,0>(); NEXT; }
1042 CASE(31) { II ii = ld_SS_word<SP,0>(); NEXT; }
1043 CASE(04) { II ii = inc_R<B,0>(); NEXT; }
1044 CASE(0C) { II ii = inc_R<C,0>(); NEXT; }
1045 CASE(14) { II ii = inc_R<D,0>(); NEXT; }
1046 CASE(1C) { II ii = inc_R<E,0>(); NEXT; }
1047 CASE(24) { II ii = inc_R<H,0>(); NEXT; }
1048 CASE(2C) { II ii = inc_R<L,0>(); NEXT; }
1049 CASE(3C) { II ii = inc_R<A,0>(); NEXT; }
1050 CASE(34) { II ii = inc_xhl(); NEXT; }
1051 CASE(05) { II ii = dec_R<B,0>(); NEXT; }
1052 CASE(0D) { II ii = dec_R<C,0>(); NEXT; }
1053 CASE(15) { II ii = dec_R<D,0>(); NEXT; }
1054 CASE(1D) { II ii = dec_R<E,0>(); NEXT; }
1055 CASE(25) { II ii = dec_R<H,0>(); NEXT; }
1056 CASE(2D) { II ii = dec_R<L,0>(); NEXT; }
1057 CASE(3D) { II ii = dec_R<A,0>(); NEXT; }
1058 CASE(35) { II ii = dec_xhl(); NEXT; }
1059 CASE(06) { II ii = ld_R_byte<B,0>(); NEXT; }
1060 CASE(0E) { II ii = ld_R_byte<C,0>(); NEXT; }
1061 CASE(16) { II ii = ld_R_byte<D,0>(); NEXT; }
1062 CASE(1E) { II ii = ld_R_byte<E,0>(); NEXT; }
1063 CASE(26) { II ii = ld_R_byte<H,0>(); NEXT; }
1064 CASE(2E) { II ii = ld_R_byte<L,0>(); NEXT; }
1065 CASE(3E) { II ii = ld_R_byte<A,0>(); NEXT; }
1066 CASE(36) { II ii = ld_xhl_byte(); NEXT; }
1067 
1068 CASE(41) { II ii = ld_R_R<B,C,0>(); NEXT; }
1069 CASE(42) { II ii = ld_R_R<B,D,0>(); NEXT; }
1070 CASE(43) { II ii = ld_R_R<B,E,0>(); NEXT; }
1071 CASE(44) { II ii = ld_R_R<B,H,0>(); NEXT; }
1072 CASE(45) { II ii = ld_R_R<B,L,0>(); NEXT; }
1073 CASE(47) { II ii = ld_R_R<B,A,0>(); NEXT; }
1074 CASE(48) { II ii = ld_R_R<C,B,0>(); NEXT; }
1075 CASE(4A) { II ii = ld_R_R<C,D,0>(); NEXT; }
1076 CASE(4B) { II ii = ld_R_R<C,E,0>(); NEXT; }
1077 CASE(4C) { II ii = ld_R_R<C,H,0>(); NEXT; }
1078 CASE(4D) { II ii = ld_R_R<C,L,0>(); NEXT; }
1079 CASE(4F) { II ii = ld_R_R<C,A,0>(); NEXT; }
1080 CASE(50) { II ii = ld_R_R<D,B,0>(); NEXT; }
1081 CASE(51) { II ii = ld_R_R<D,C,0>(); NEXT; }
1082 CASE(53) { II ii = ld_R_R<D,E,0>(); NEXT; }
1083 CASE(54) { II ii = ld_R_R<D,H,0>(); NEXT; }
1084 CASE(55) { II ii = ld_R_R<D,L,0>(); NEXT; }
1085 CASE(57) { II ii = ld_R_R<D,A,0>(); NEXT; }
1086 CASE(58) { II ii = ld_R_R<E,B,0>(); NEXT; }
1087 CASE(59) { II ii = ld_R_R<E,C,0>(); NEXT; }
1088 CASE(5A) { II ii = ld_R_R<E,D,0>(); NEXT; }
1089 CASE(5C) { II ii = ld_R_R<E,H,0>(); NEXT; }
1090 CASE(5D) { II ii = ld_R_R<E,L,0>(); NEXT; }
1091 CASE(5F) { II ii = ld_R_R<E,A,0>(); NEXT; }
1092 CASE(60) { II ii = ld_R_R<H,B,0>(); NEXT; }
1093 CASE(61) { II ii = ld_R_R<H,C,0>(); NEXT; }
1094 CASE(62) { II ii = ld_R_R<H,D,0>(); NEXT; }
1095 CASE(63) { II ii = ld_R_R<H,E,0>(); NEXT; }
1096 CASE(65) { II ii = ld_R_R<H,L,0>(); NEXT; }
1097 CASE(67) { II ii = ld_R_R<H,A,0>(); NEXT; }
1098 CASE(68) { II ii = ld_R_R<L,B,0>(); NEXT; }
1099 CASE(69) { II ii = ld_R_R<L,C,0>(); NEXT; }
1100 CASE(6A) { II ii = ld_R_R<L,D,0>(); NEXT; }
1101 CASE(6B) { II ii = ld_R_R<L,E,0>(); NEXT; }
1102 CASE(6C) { II ii = ld_R_R<L,H,0>(); NEXT; }
1103 CASE(6F) { II ii = ld_R_R<L,A,0>(); NEXT; }
1104 CASE(78) { II ii = ld_R_R<A,B,0>(); NEXT; }
1105 CASE(79) { II ii = ld_R_R<A,C,0>(); NEXT; }
1106 CASE(7A) { II ii = ld_R_R<A,D,0>(); NEXT; }
1107 CASE(7B) { II ii = ld_R_R<A,E,0>(); NEXT; }
1108 CASE(7C) { II ii = ld_R_R<A,H,0>(); NEXT; }
1109 CASE(7D) { II ii = ld_R_R<A,L,0>(); NEXT; }
1110 CASE(70) { II ii = ld_xhl_R<B>(); NEXT; }
1111 CASE(71) { II ii = ld_xhl_R<C>(); NEXT; }
1112 CASE(72) { II ii = ld_xhl_R<D>(); NEXT; }
1113 CASE(73) { II ii = ld_xhl_R<E>(); NEXT; }
1114 CASE(74) { II ii = ld_xhl_R<H>(); NEXT; }
1115 CASE(75) { II ii = ld_xhl_R<L>(); NEXT; }
1116 CASE(77) { II ii = ld_xhl_R<A>(); NEXT; }
1117 CASE(46) { II ii = ld_R_xhl<B>(); NEXT; }
1118 CASE(4E) { II ii = ld_R_xhl<C>(); NEXT; }
1119 CASE(56) { II ii = ld_R_xhl<D>(); NEXT; }
1120 CASE(5E) { II ii = ld_R_xhl<E>(); NEXT; }
1121 CASE(66) { II ii = ld_R_xhl<H>(); NEXT; }
1122 CASE(6E) { II ii = ld_R_xhl<L>(); NEXT; }
1123 CASE(7E) { II ii = ld_R_xhl<A>(); NEXT; }
1124 CASE(76) { II ii = halt(); NEXT_STOP; }
1125 
1126 CASE(80) { II ii = add_a_R<B,0>(); NEXT; }
1127 CASE(81) { II ii = add_a_R<C,0>(); NEXT; }
1128 CASE(82) { II ii = add_a_R<D,0>(); NEXT; }
1129 CASE(83) { II ii = add_a_R<E,0>(); NEXT; }
1130 CASE(84) { II ii = add_a_R<H,0>(); NEXT; }
1131 CASE(85) { II ii = add_a_R<L,0>(); NEXT; }
1132 CASE(86) { II ii = add_a_xhl(); NEXT; }
1133 CASE(87) { II ii = add_a_a(); NEXT; }
1134 CASE(88) { II ii = adc_a_R<B,0>(); NEXT; }
1135 CASE(89) { II ii = adc_a_R<C,0>(); NEXT; }
1136 CASE(8A) { II ii = adc_a_R<D,0>(); NEXT; }
1137 CASE(8B) { II ii = adc_a_R<E,0>(); NEXT; }
1138 CASE(8C) { II ii = adc_a_R<H,0>(); NEXT; }
1139 CASE(8D) { II ii = adc_a_R<L,0>(); NEXT; }
1140 CASE(8E) { II ii = adc_a_xhl(); NEXT; }
1141 CASE(8F) { II ii = adc_a_a(); NEXT; }
1142 CASE(90) { II ii = sub_R<B,0>(); NEXT; }
1143 CASE(91) { II ii = sub_R<C,0>(); NEXT; }
1144 CASE(92) { II ii = sub_R<D,0>(); NEXT; }
1145 CASE(93) { II ii = sub_R<E,0>(); NEXT; }
1146 CASE(94) { II ii = sub_R<H,0>(); NEXT; }
1147 CASE(95) { II ii = sub_R<L,0>(); NEXT; }
1148 CASE(96) { II ii = sub_xhl(); NEXT; }
1149 CASE(97) { II ii = sub_a(); NEXT; }
1150 CASE(98) { II ii = sbc_a_R<B,0>(); NEXT; }
1151 CASE(99) { II ii = sbc_a_R<C,0>(); NEXT; }
1152 CASE(9A) { II ii = sbc_a_R<D,0>(); NEXT; }
1153 CASE(9B) { II ii = sbc_a_R<E,0>(); NEXT; }
1154 CASE(9C) { II ii = sbc_a_R<H,0>(); NEXT; }
1155 CASE(9D) { II ii = sbc_a_R<L,0>(); NEXT; }
1156 CASE(9E) { II ii = sbc_a_xhl(); NEXT; }
1157 CASE(9F) { II ii = sbc_a_a(); NEXT; }
1158 CASE(A0) { II ii = and_R<B,0>(); NEXT; }
1159 CASE(A1) { II ii = and_R<C,0>(); NEXT; }
1160 CASE(A2) { II ii = and_R<D,0>(); NEXT; }
1161 CASE(A3) { II ii = and_R<E,0>(); NEXT; }
1162 CASE(A4) { II ii = and_R<H,0>(); NEXT; }
1163 CASE(A5) { II ii = and_R<L,0>(); NEXT; }
1164 CASE(A6) { II ii = and_xhl(); NEXT; }
1165 CASE(A7) { II ii = and_a(); NEXT; }
1166 CASE(A8) { II ii = xor_R<B,0>(); NEXT; }
1167 CASE(A9) { II ii = xor_R<C,0>(); NEXT; }
1168 CASE(AA) { II ii = xor_R<D,0>(); NEXT; }
1169 CASE(AB) { II ii = xor_R<E,0>(); NEXT; }
1170 CASE(AC) { II ii = xor_R<H,0>(); NEXT; }
1171 CASE(AD) { II ii = xor_R<L,0>(); NEXT; }
1172 CASE(AE) { II ii = xor_xhl(); NEXT; }
1173 CASE(AF) { II ii = xor_a(); NEXT; }
1174 CASE(B0) { II ii = or_R<B,0>(); NEXT; }
1175 CASE(B1) { II ii = or_R<C,0>(); NEXT; }
1176 CASE(B2) { II ii = or_R<D,0>(); NEXT; }
1177 CASE(B3) { II ii = or_R<E,0>(); NEXT; }
1178 CASE(B4) { II ii = or_R<H,0>(); NEXT; }
1179 CASE(B5) { II ii = or_R<L,0>(); NEXT; }
1180 CASE(B6) { II ii = or_xhl(); NEXT; }
1181 CASE(B7) { II ii = or_a(); NEXT; }
1182 CASE(B8) { II ii = cp_R<B,0>(); NEXT; }
1183 CASE(B9) { II ii = cp_R<C,0>(); NEXT; }
1184 CASE(BA) { II ii = cp_R<D,0>(); NEXT; }
1185 CASE(BB) { II ii = cp_R<E,0>(); NEXT; }
1186 CASE(BC) { II ii = cp_R<H,0>(); NEXT; }
1187 CASE(BD) { II ii = cp_R<L,0>(); NEXT; }
1188 CASE(BE) { II ii = cp_xhl(); NEXT; }
1189 CASE(BF) { II ii = cp_a(); NEXT; }
1190 
1191 CASE(D3) { II ii = out_byte_a(); NEXT; }
1192 CASE(DB) { II ii = in_a_byte(); NEXT; }
1193 CASE(D9) { II ii = exx(); NEXT; }
1194 CASE(E3) { II ii = ex_xsp_SS<HL,0>(); NEXT; }
1195 CASE(EB) { II ii = ex_de_hl(); NEXT; }
1196 CASE(E9) { II ii = jp_SS<HL,0>(); NEXT; }
1197 CASE(F9) { II ii = ld_sp_SS<HL,0>(); NEXT; }
1198 CASE(F3) { II ii = di(); NEXT; }
1199 CASE(FB) { II ii = ei(); NEXT_EI; }
1200 CASE(C6) { II ii = add_a_byte(); NEXT; }
1201 CASE(CE) { II ii = adc_a_byte(); NEXT; }
1202 CASE(D6) { II ii = sub_byte(); NEXT; }
1203 CASE(DE) { II ii = sbc_a_byte(); NEXT; }
1204 CASE(E6) { II ii = and_byte(); NEXT; }
1205 CASE(EE) { II ii = xor_byte(); NEXT; }
1206 CASE(F6) { II ii = or_byte(); NEXT; }
1207 CASE(FE) { II ii = cp_byte(); NEXT; }
1208 CASE(C0) { II ii = ret(CondNZ()); NEXT; }
1209 CASE(C8) { II ii = ret(CondZ ()); NEXT; }
1210 CASE(D0) { II ii = ret(CondNC()); NEXT; }
1211 CASE(D8) { II ii = ret(CondC ()); NEXT; }
1212 CASE(E0) { II ii = ret(CondPO()); NEXT; }
1213 CASE(E8) { II ii = ret(CondPE()); NEXT; }
1214 CASE(F0) { II ii = ret(CondP ()); NEXT; }
1215 CASE(F8) { II ii = ret(CondM ()); NEXT; }
1216 CASE(C9) { II ii = ret(); NEXT; }
1217 CASE(C2) { II ii = jp(CondNZ()); NEXT; }
1218 CASE(CA) { II ii = jp(CondZ ()); NEXT; }
1219 CASE(D2) { II ii = jp(CondNC()); NEXT; }
1220 CASE(DA) { II ii = jp(CondC ()); NEXT; }
1221 CASE(E2) { II ii = jp(CondPO()); NEXT; }
1222 CASE(EA) { II ii = jp(CondPE()); NEXT; }
1223 CASE(F2) { II ii = jp(CondP ()); NEXT; }
1224 CASE(FA) { II ii = jp(CondM ()); NEXT; }
1225 CASE(C3) { II ii = jp(CondTrue()); NEXT; }
1226 CASE(C4) { II ii = call(CondNZ()); NEXT; }
1227 CASE(CC) { II ii = call(CondZ ()); NEXT; }
1228 CASE(D4) { II ii = call(CondNC()); NEXT; }
1229 CASE(DC) { II ii = call(CondC ()); NEXT; }
1230 CASE(E4) { II ii = call(CondPO()); NEXT; }
1231 CASE(EC) { II ii = call(CondPE()); NEXT; }
1232 CASE(F4) { II ii = call(CondP ()); NEXT; }
1233 CASE(FC) { II ii = call(CondM ()); NEXT; }
1234 CASE(CD) { II ii = call(CondTrue()); NEXT; }
1235 CASE(C1) { II ii = pop_SS <BC,0>(); NEXT; }
1236 CASE(D1) { II ii = pop_SS <DE,0>(); NEXT; }
1237 CASE(E1) { II ii = pop_SS <HL,0>(); NEXT; }
1238 CASE(F1) { II ii = pop_SS <AF,0>(); NEXT; }
1239 CASE(C5) { II ii = push_SS<BC,0>(); NEXT; }
1240 CASE(D5) { II ii = push_SS<DE,0>(); NEXT; }
1241 CASE(E5) { II ii = push_SS<HL,0>(); NEXT; }
1242 CASE(F5) { II ii = push_SS<AF,0>(); NEXT; }
1243 CASE(C7) { II ii = rst<0x00>(); NEXT; }
1244 CASE(CF) { II ii = rst<0x08>(); NEXT; }
1245 CASE(D7) { II ii = rst<0x10>(); NEXT; }
1246 CASE(DF) { II ii = rst<0x18>(); NEXT; }
1247 CASE(E7) { II ii = rst<0x20>(); NEXT; }
1248 CASE(EF) { II ii = rst<0x28>(); NEXT; }
1249 CASE(F7) { II ii = rst<0x30>(); NEXT; }
1250 CASE(FF) { II ii = rst<0x38>(); NEXT; }
1251 CASE(CB) {
1252  setPC(getPC() + 1); // M1 cycle at this point
1253  byte cb_opcode = RDMEM_OPCODE<0>(T::CC_PREFIX);
1254  incR(1);
1255  switch (cb_opcode) {
1256  case 0x00: { II ii = rlc_R<B>(); NEXT; }
1257  case 0x01: { II ii = rlc_R<C>(); NEXT; }
1258  case 0x02: { II ii = rlc_R<D>(); NEXT; }
1259  case 0x03: { II ii = rlc_R<E>(); NEXT; }
1260  case 0x04: { II ii = rlc_R<H>(); NEXT; }
1261  case 0x05: { II ii = rlc_R<L>(); NEXT; }
1262  case 0x07: { II ii = rlc_R<A>(); NEXT; }
1263  case 0x06: { II ii = rlc_xhl(); NEXT; }
1264  case 0x08: { II ii = rrc_R<B>(); NEXT; }
1265  case 0x09: { II ii = rrc_R<C>(); NEXT; }
1266  case 0x0a: { II ii = rrc_R<D>(); NEXT; }
1267  case 0x0b: { II ii = rrc_R<E>(); NEXT; }
1268  case 0x0c: { II ii = rrc_R<H>(); NEXT; }
1269  case 0x0d: { II ii = rrc_R<L>(); NEXT; }
1270  case 0x0f: { II ii = rrc_R<A>(); NEXT; }
1271  case 0x0e: { II ii = rrc_xhl(); NEXT; }
1272  case 0x10: { II ii = rl_R<B>(); NEXT; }
1273  case 0x11: { II ii = rl_R<C>(); NEXT; }
1274  case 0x12: { II ii = rl_R<D>(); NEXT; }
1275  case 0x13: { II ii = rl_R<E>(); NEXT; }
1276  case 0x14: { II ii = rl_R<H>(); NEXT; }
1277  case 0x15: { II ii = rl_R<L>(); NEXT; }
1278  case 0x17: { II ii = rl_R<A>(); NEXT; }
1279  case 0x16: { II ii = rl_xhl(); NEXT; }
1280  case 0x18: { II ii = rr_R<B>(); NEXT; }
1281  case 0x19: { II ii = rr_R<C>(); NEXT; }
1282  case 0x1a: { II ii = rr_R<D>(); NEXT; }
1283  case 0x1b: { II ii = rr_R<E>(); NEXT; }
1284  case 0x1c: { II ii = rr_R<H>(); NEXT; }
1285  case 0x1d: { II ii = rr_R<L>(); NEXT; }
1286  case 0x1f: { II ii = rr_R<A>(); NEXT; }
1287  case 0x1e: { II ii = rr_xhl(); NEXT; }
1288  case 0x20: { II ii = sla_R<B>(); NEXT; }
1289  case 0x21: { II ii = sla_R<C>(); NEXT; }
1290  case 0x22: { II ii = sla_R<D>(); NEXT; }
1291  case 0x23: { II ii = sla_R<E>(); NEXT; }
1292  case 0x24: { II ii = sla_R<H>(); NEXT; }
1293  case 0x25: { II ii = sla_R<L>(); NEXT; }
1294  case 0x27: { II ii = sla_R<A>(); NEXT; }
1295  case 0x26: { II ii = sla_xhl(); NEXT; }
1296  case 0x28: { II ii = sra_R<B>(); NEXT; }
1297  case 0x29: { II ii = sra_R<C>(); NEXT; }
1298  case 0x2a: { II ii = sra_R<D>(); NEXT; }
1299  case 0x2b: { II ii = sra_R<E>(); NEXT; }
1300  case 0x2c: { II ii = sra_R<H>(); NEXT; }
1301  case 0x2d: { II ii = sra_R<L>(); NEXT; }
1302  case 0x2f: { II ii = sra_R<A>(); NEXT; }
1303  case 0x2e: { II ii = sra_xhl(); NEXT; }
1304  case 0x30: { II ii = T::isR800() ? sla_R<B>() : sll_R<B>(); NEXT; }
1305  case 0x31: { II ii = T::isR800() ? sla_R<C>() : sll_R<C>(); NEXT; }
1306  case 0x32: { II ii = T::isR800() ? sla_R<D>() : sll_R<D>(); NEXT; }
1307  case 0x33: { II ii = T::isR800() ? sla_R<E>() : sll_R<E>(); NEXT; }
1308  case 0x34: { II ii = T::isR800() ? sla_R<H>() : sll_R<H>(); NEXT; }
1309  case 0x35: { II ii = T::isR800() ? sla_R<L>() : sll_R<L>(); NEXT; }
1310  case 0x37: { II ii = T::isR800() ? sla_R<A>() : sll_R<A>(); NEXT; }
1311  case 0x36: { II ii = T::isR800() ? sla_xhl() : sll_xhl(); NEXT; }
1312  case 0x38: { II ii = srl_R<B>(); NEXT; }
1313  case 0x39: { II ii = srl_R<C>(); NEXT; }
1314  case 0x3a: { II ii = srl_R<D>(); NEXT; }
1315  case 0x3b: { II ii = srl_R<E>(); NEXT; }
1316  case 0x3c: { II ii = srl_R<H>(); NEXT; }
1317  case 0x3d: { II ii = srl_R<L>(); NEXT; }
1318  case 0x3f: { II ii = srl_R<A>(); NEXT; }
1319  case 0x3e: { II ii = srl_xhl(); NEXT; }
1320 
1321  case 0x40: { II ii = bit_N_R<0,B>(); NEXT; }
1322  case 0x41: { II ii = bit_N_R<0,C>(); NEXT; }
1323  case 0x42: { II ii = bit_N_R<0,D>(); NEXT; }
1324  case 0x43: { II ii = bit_N_R<0,E>(); NEXT; }
1325  case 0x44: { II ii = bit_N_R<0,H>(); NEXT; }
1326  case 0x45: { II ii = bit_N_R<0,L>(); NEXT; }
1327  case 0x47: { II ii = bit_N_R<0,A>(); NEXT; }
1328  case 0x48: { II ii = bit_N_R<1,B>(); NEXT; }
1329  case 0x49: { II ii = bit_N_R<1,C>(); NEXT; }
1330  case 0x4a: { II ii = bit_N_R<1,D>(); NEXT; }
1331  case 0x4b: { II ii = bit_N_R<1,E>(); NEXT; }
1332  case 0x4c: { II ii = bit_N_R<1,H>(); NEXT; }
1333  case 0x4d: { II ii = bit_N_R<1,L>(); NEXT; }
1334  case 0x4f: { II ii = bit_N_R<1,A>(); NEXT; }
1335  case 0x50: { II ii = bit_N_R<2,B>(); NEXT; }
1336  case 0x51: { II ii = bit_N_R<2,C>(); NEXT; }
1337  case 0x52: { II ii = bit_N_R<2,D>(); NEXT; }
1338  case 0x53: { II ii = bit_N_R<2,E>(); NEXT; }
1339  case 0x54: { II ii = bit_N_R<2,H>(); NEXT; }
1340  case 0x55: { II ii = bit_N_R<2,L>(); NEXT; }
1341  case 0x57: { II ii = bit_N_R<2,A>(); NEXT; }
1342  case 0x58: { II ii = bit_N_R<3,B>(); NEXT; }
1343  case 0x59: { II ii = bit_N_R<3,C>(); NEXT; }
1344  case 0x5a: { II ii = bit_N_R<3,D>(); NEXT; }
1345  case 0x5b: { II ii = bit_N_R<3,E>(); NEXT; }
1346  case 0x5c: { II ii = bit_N_R<3,H>(); NEXT; }
1347  case 0x5d: { II ii = bit_N_R<3,L>(); NEXT; }
1348  case 0x5f: { II ii = bit_N_R<3,A>(); NEXT; }
1349  case 0x60: { II ii = bit_N_R<4,B>(); NEXT; }
1350  case 0x61: { II ii = bit_N_R<4,C>(); NEXT; }
1351  case 0x62: { II ii = bit_N_R<4,D>(); NEXT; }
1352  case 0x63: { II ii = bit_N_R<4,E>(); NEXT; }
1353  case 0x64: { II ii = bit_N_R<4,H>(); NEXT; }
1354  case 0x65: { II ii = bit_N_R<4,L>(); NEXT; }
1355  case 0x67: { II ii = bit_N_R<4,A>(); NEXT; }
1356  case 0x68: { II ii = bit_N_R<5,B>(); NEXT; }
1357  case 0x69: { II ii = bit_N_R<5,C>(); NEXT; }
1358  case 0x6a: { II ii = bit_N_R<5,D>(); NEXT; }
1359  case 0x6b: { II ii = bit_N_R<5,E>(); NEXT; }
1360  case 0x6c: { II ii = bit_N_R<5,H>(); NEXT; }
1361  case 0x6d: { II ii = bit_N_R<5,L>(); NEXT; }
1362  case 0x6f: { II ii = bit_N_R<5,A>(); NEXT; }
1363  case 0x70: { II ii = bit_N_R<6,B>(); NEXT; }
1364  case 0x71: { II ii = bit_N_R<6,C>(); NEXT; }
1365  case 0x72: { II ii = bit_N_R<6,D>(); NEXT; }
1366  case 0x73: { II ii = bit_N_R<6,E>(); NEXT; }
1367  case 0x74: { II ii = bit_N_R<6,H>(); NEXT; }
1368  case 0x75: { II ii = bit_N_R<6,L>(); NEXT; }
1369  case 0x77: { II ii = bit_N_R<6,A>(); NEXT; }
1370  case 0x78: { II ii = bit_N_R<7,B>(); NEXT; }
1371  case 0x79: { II ii = bit_N_R<7,C>(); NEXT; }
1372  case 0x7a: { II ii = bit_N_R<7,D>(); NEXT; }
1373  case 0x7b: { II ii = bit_N_R<7,E>(); NEXT; }
1374  case 0x7c: { II ii = bit_N_R<7,H>(); NEXT; }
1375  case 0x7d: { II ii = bit_N_R<7,L>(); NEXT; }
1376  case 0x7f: { II ii = bit_N_R<7,A>(); NEXT; }
1377  case 0x46: { II ii = bit_N_xhl<0>(); NEXT; }
1378  case 0x4e: { II ii = bit_N_xhl<1>(); NEXT; }
1379  case 0x56: { II ii = bit_N_xhl<2>(); NEXT; }
1380  case 0x5e: { II ii = bit_N_xhl<3>(); NEXT; }
1381  case 0x66: { II ii = bit_N_xhl<4>(); NEXT; }
1382  case 0x6e: { II ii = bit_N_xhl<5>(); NEXT; }
1383  case 0x76: { II ii = bit_N_xhl<6>(); NEXT; }
1384  case 0x7e: { II ii = bit_N_xhl<7>(); NEXT; }
1385 
1386  case 0x80: { II ii = res_N_R<0,B>(); NEXT; }
1387  case 0x81: { II ii = res_N_R<0,C>(); NEXT; }
1388  case 0x82: { II ii = res_N_R<0,D>(); NEXT; }
1389  case 0x83: { II ii = res_N_R<0,E>(); NEXT; }
1390  case 0x84: { II ii = res_N_R<0,H>(); NEXT; }
1391  case 0x85: { II ii = res_N_R<0,L>(); NEXT; }
1392  case 0x87: { II ii = res_N_R<0,A>(); NEXT; }
1393  case 0x88: { II ii = res_N_R<1,B>(); NEXT; }
1394  case 0x89: { II ii = res_N_R<1,C>(); NEXT; }
1395  case 0x8a: { II ii = res_N_R<1,D>(); NEXT; }
1396  case 0x8b: { II ii = res_N_R<1,E>(); NEXT; }
1397  case 0x8c: { II ii = res_N_R<1,H>(); NEXT; }
1398  case 0x8d: { II ii = res_N_R<1,L>(); NEXT; }
1399  case 0x8f: { II ii = res_N_R<1,A>(); NEXT; }
1400  case 0x90: { II ii = res_N_R<2,B>(); NEXT; }
1401  case 0x91: { II ii = res_N_R<2,C>(); NEXT; }
1402  case 0x92: { II ii = res_N_R<2,D>(); NEXT; }
1403  case 0x93: { II ii = res_N_R<2,E>(); NEXT; }
1404  case 0x94: { II ii = res_N_R<2,H>(); NEXT; }
1405  case 0x95: { II ii = res_N_R<2,L>(); NEXT; }
1406  case 0x97: { II ii = res_N_R<2,A>(); NEXT; }
1407  case 0x98: { II ii = res_N_R<3,B>(); NEXT; }
1408  case 0x99: { II ii = res_N_R<3,C>(); NEXT; }
1409  case 0x9a: { II ii = res_N_R<3,D>(); NEXT; }
1410  case 0x9b: { II ii = res_N_R<3,E>(); NEXT; }
1411  case 0x9c: { II ii = res_N_R<3,H>(); NEXT; }
1412  case 0x9d: { II ii = res_N_R<3,L>(); NEXT; }
1413  case 0x9f: { II ii = res_N_R<3,A>(); NEXT; }
1414  case 0xa0: { II ii = res_N_R<4,B>(); NEXT; }
1415  case 0xa1: { II ii = res_N_R<4,C>(); NEXT; }
1416  case 0xa2: { II ii = res_N_R<4,D>(); NEXT; }
1417  case 0xa3: { II ii = res_N_R<4,E>(); NEXT; }
1418  case 0xa4: { II ii = res_N_R<4,H>(); NEXT; }
1419  case 0xa5: { II ii = res_N_R<4,L>(); NEXT; }
1420  case 0xa7: { II ii = res_N_R<4,A>(); NEXT; }
1421  case 0xa8: { II ii = res_N_R<5,B>(); NEXT; }
1422  case 0xa9: { II ii = res_N_R<5,C>(); NEXT; }
1423  case 0xaa: { II ii = res_N_R<5,D>(); NEXT; }
1424  case 0xab: { II ii = res_N_R<5,E>(); NEXT; }
1425  case 0xac: { II ii = res_N_R<5,H>(); NEXT; }
1426  case 0xad: { II ii = res_N_R<5,L>(); NEXT; }
1427  case 0xaf: { II ii = res_N_R<5,A>(); NEXT; }
1428  case 0xb0: { II ii = res_N_R<6,B>(); NEXT; }
1429  case 0xb1: { II ii = res_N_R<6,C>(); NEXT; }
1430  case 0xb2: { II ii = res_N_R<6,D>(); NEXT; }
1431  case 0xb3: { II ii = res_N_R<6,E>(); NEXT; }
1432  case 0xb4: { II ii = res_N_R<6,H>(); NEXT; }
1433  case 0xb5: { II ii = res_N_R<6,L>(); NEXT; }
1434  case 0xb7: { II ii = res_N_R<6,A>(); NEXT; }
1435  case 0xb8: { II ii = res_N_R<7,B>(); NEXT; }
1436  case 0xb9: { II ii = res_N_R<7,C>(); NEXT; }
1437  case 0xba: { II ii = res_N_R<7,D>(); NEXT; }
1438  case 0xbb: { II ii = res_N_R<7,E>(); NEXT; }
1439  case 0xbc: { II ii = res_N_R<7,H>(); NEXT; }
1440  case 0xbd: { II ii = res_N_R<7,L>(); NEXT; }
1441  case 0xbf: { II ii = res_N_R<7,A>(); NEXT; }
1442  case 0x86: { II ii = res_N_xhl<0>(); NEXT; }
1443  case 0x8e: { II ii = res_N_xhl<1>(); NEXT; }
1444  case 0x96: { II ii = res_N_xhl<2>(); NEXT; }
1445  case 0x9e: { II ii = res_N_xhl<3>(); NEXT; }
1446  case 0xa6: { II ii = res_N_xhl<4>(); NEXT; }
1447  case 0xae: { II ii = res_N_xhl<5>(); NEXT; }
1448  case 0xb6: { II ii = res_N_xhl<6>(); NEXT; }
1449  case 0xbe: { II ii = res_N_xhl<7>(); NEXT; }
1450 
1451  case 0xc0: { II ii = set_N_R<0,B>(); NEXT; }
1452  case 0xc1: { II ii = set_N_R<0,C>(); NEXT; }
1453  case 0xc2: { II ii = set_N_R<0,D>(); NEXT; }
1454  case 0xc3: { II ii = set_N_R<0,E>(); NEXT; }
1455  case 0xc4: { II ii = set_N_R<0,H>(); NEXT; }
1456  case 0xc5: { II ii = set_N_R<0,L>(); NEXT; }
1457  case 0xc7: { II ii = set_N_R<0,A>(); NEXT; }
1458  case 0xc8: { II ii = set_N_R<1,B>(); NEXT; }
1459  case 0xc9: { II ii = set_N_R<1,C>(); NEXT; }
1460  case 0xca: { II ii = set_N_R<1,D>(); NEXT; }
1461  case 0xcb: { II ii = set_N_R<1,E>(); NEXT; }
1462  case 0xcc: { II ii = set_N_R<1,H>(); NEXT; }
1463  case 0xcd: { II ii = set_N_R<1,L>(); NEXT; }
1464  case 0xcf: { II ii = set_N_R<1,A>(); NEXT; }
1465  case 0xd0: { II ii = set_N_R<2,B>(); NEXT; }
1466  case 0xd1: { II ii = set_N_R<2,C>(); NEXT; }
1467  case 0xd2: { II ii = set_N_R<2,D>(); NEXT; }
1468  case 0xd3: { II ii = set_N_R<2,E>(); NEXT; }
1469  case 0xd4: { II ii = set_N_R<2,H>(); NEXT; }
1470  case 0xd5: { II ii = set_N_R<2,L>(); NEXT; }
1471  case 0xd7: { II ii = set_N_R<2,A>(); NEXT; }
1472  case 0xd8: { II ii = set_N_R<3,B>(); NEXT; }
1473  case 0xd9: { II ii = set_N_R<3,C>(); NEXT; }
1474  case 0xda: { II ii = set_N_R<3,D>(); NEXT; }
1475  case 0xdb: { II ii = set_N_R<3,E>(); NEXT; }
1476  case 0xdc: { II ii = set_N_R<3,H>(); NEXT; }
1477  case 0xdd: { II ii = set_N_R<3,L>(); NEXT; }
1478  case 0xdf: { II ii = set_N_R<3,A>(); NEXT; }
1479  case 0xe0: { II ii = set_N_R<4,B>(); NEXT; }
1480  case 0xe1: { II ii = set_N_R<4,C>(); NEXT; }
1481  case 0xe2: { II ii = set_N_R<4,D>(); NEXT; }
1482  case 0xe3: { II ii = set_N_R<4,E>(); NEXT; }
1483  case 0xe4: { II ii = set_N_R<4,H>(); NEXT; }
1484  case 0xe5: { II ii = set_N_R<4,L>(); NEXT; }
1485  case 0xe7: { II ii = set_N_R<4,A>(); NEXT; }
1486  case 0xe8: { II ii = set_N_R<5,B>(); NEXT; }
1487  case 0xe9: { II ii = set_N_R<5,C>(); NEXT; }
1488  case 0xea: { II ii = set_N_R<5,D>(); NEXT; }
1489  case 0xeb: { II ii = set_N_R<5,E>(); NEXT; }
1490  case 0xec: { II ii = set_N_R<5,H>(); NEXT; }
1491  case 0xed: { II ii = set_N_R<5,L>(); NEXT; }
1492  case 0xef: { II ii = set_N_R<5,A>(); NEXT; }
1493  case 0xf0: { II ii = set_N_R<6,B>(); NEXT; }
1494  case 0xf1: { II ii = set_N_R<6,C>(); NEXT; }
1495  case 0xf2: { II ii = set_N_R<6,D>(); NEXT; }
1496  case 0xf3: { II ii = set_N_R<6,E>(); NEXT; }
1497  case 0xf4: { II ii = set_N_R<6,H>(); NEXT; }
1498  case 0xf5: { II ii = set_N_R<6,L>(); NEXT; }
1499  case 0xf7: { II ii = set_N_R<6,A>(); NEXT; }
1500  case 0xf8: { II ii = set_N_R<7,B>(); NEXT; }
1501  case 0xf9: { II ii = set_N_R<7,C>(); NEXT; }
1502  case 0xfa: { II ii = set_N_R<7,D>(); NEXT; }
1503  case 0xfb: { II ii = set_N_R<7,E>(); NEXT; }
1504  case 0xfc: { II ii = set_N_R<7,H>(); NEXT; }
1505  case 0xfd: { II ii = set_N_R<7,L>(); NEXT; }
1506  case 0xff: { II ii = set_N_R<7,A>(); NEXT; }
1507  case 0xc6: { II ii = set_N_xhl<0>(); NEXT; }
1508  case 0xce: { II ii = set_N_xhl<1>(); NEXT; }
1509  case 0xd6: { II ii = set_N_xhl<2>(); NEXT; }
1510  case 0xde: { II ii = set_N_xhl<3>(); NEXT; }
1511  case 0xe6: { II ii = set_N_xhl<4>(); NEXT; }
1512  case 0xee: { II ii = set_N_xhl<5>(); NEXT; }
1513  case 0xf6: { II ii = set_N_xhl<6>(); NEXT; }
1514  case 0xfe: { II ii = set_N_xhl<7>(); NEXT; }
1515  default: UNREACHABLE; return;
1516  }
1517 }
1518 CASE(ED) {
1519  setPC(getPC() + 1); // M1 cycle at this point
1520  byte ed_opcode = RDMEM_OPCODE<0>(T::CC_PREFIX);
1521  incR(1);
1522  switch (ed_opcode) {
1523  case 0x00: case 0x01: case 0x02: case 0x03:
1524  case 0x04: case 0x05: case 0x06: case 0x07:
1525  case 0x08: case 0x09: case 0x0a: case 0x0b:
1526  case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1527  case 0x10: case 0x11: case 0x12: case 0x13:
1528  case 0x14: case 0x15: case 0x16: case 0x17:
1529  case 0x18: case 0x19: case 0x1a: case 0x1b:
1530  case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1531  case 0x20: case 0x21: case 0x22: case 0x23:
1532  case 0x24: case 0x25: case 0x26: case 0x27:
1533  case 0x28: case 0x29: case 0x2a: case 0x2b:
1534  case 0x2c: case 0x2d: case 0x2e: case 0x2f:
1535  case 0x30: case 0x31: case 0x32: case 0x33:
1536  case 0x34: case 0x35: case 0x36: case 0x37:
1537  case 0x38: case 0x39: case 0x3a: case 0x3b:
1538  case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1539 
1540  case 0x77: case 0x7f:
1541 
1542  case 0x80: case 0x81: case 0x82: case 0x83:
1543  case 0x84: case 0x85: case 0x86: case 0x87:
1544  case 0x88: case 0x89: case 0x8a: case 0x8b:
1545  case 0x8c: case 0x8d: case 0x8e: case 0x8f:
1546  case 0x90: case 0x91: case 0x92: case 0x93:
1547  case 0x94: case 0x95: case 0x96: case 0x97:
1548  case 0x98: case 0x99: case 0x9a: case 0x9b:
1549  case 0x9c: case 0x9d: case 0x9e: case 0x9f:
1550  case 0xa4: case 0xa5: case 0xa6: case 0xa7:
1551  case 0xac: case 0xad: case 0xae: case 0xaf:
1552  case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1553  case 0xbc: case 0xbd: case 0xbe: case 0xbf:
1554 
1555  case 0xc0: case 0xc2:
1556  case 0xc4: case 0xc5: case 0xc6: case 0xc7:
1557  case 0xc8: case 0xca: case 0xcb:
1558  case 0xcc: case 0xcd: case 0xce: case 0xcf:
1559  case 0xd0: case 0xd2: case 0xd3:
1560  case 0xd4: case 0xd5: case 0xd6: case 0xd7:
1561  case 0xd8: case 0xda: case 0xdb:
1562  case 0xdc: case 0xdd: case 0xde: case 0xdf:
1563  case 0xe0: case 0xe1: case 0xe2: case 0xe3:
1564  case 0xe4: case 0xe5: case 0xe6: case 0xe7:
1565  case 0xe8: case 0xe9: case 0xea: case 0xeb:
1566  case 0xec: case 0xed: case 0xee: case 0xef:
1567  case 0xf0: case 0xf1: case 0xf2:
1568  case 0xf4: case 0xf5: case 0xf6: case 0xf7:
1569  case 0xf8: case 0xf9: case 0xfa: case 0xfb:
1570  case 0xfc: case 0xfd: case 0xfe: case 0xff:
1571  { II ii = nop(); NEXT; }
1572 
1573  case 0x40: { II ii = in_R_c<B>(); NEXT; }
1574  case 0x48: { II ii = in_R_c<C>(); NEXT; }
1575  case 0x50: { II ii = in_R_c<D>(); NEXT; }
1576  case 0x58: { II ii = in_R_c<E>(); NEXT; }
1577  case 0x60: { II ii = in_R_c<H>(); NEXT; }
1578  case 0x68: { II ii = in_R_c<L>(); NEXT; }
1579  case 0x70: { II ii = in_R_c<DUMMY>(); NEXT; }
1580  case 0x78: { II ii = in_R_c<A>(); NEXT; }
1581 
1582  case 0x41: { II ii = out_c_R<B>(); NEXT; }
1583  case 0x49: { II ii = out_c_R<C>(); NEXT; }
1584  case 0x51: { II ii = out_c_R<D>(); NEXT; }
1585  case 0x59: { II ii = out_c_R<E>(); NEXT; }
1586  case 0x61: { II ii = out_c_R<H>(); NEXT; }
1587  case 0x69: { II ii = out_c_R<L>(); NEXT; }
1588  case 0x71: { II ii = out_c_0(); NEXT; }
1589  case 0x79: { II ii = out_c_R<A>(); NEXT; }
1590 
1591  case 0x42: { II ii = sbc_hl_SS<BC>(); NEXT; }
1592  case 0x52: { II ii = sbc_hl_SS<DE>(); NEXT; }
1593  case 0x62: { II ii = sbc_hl_hl (); NEXT; }
1594  case 0x72: { II ii = sbc_hl_SS<SP>(); NEXT; }
1595 
1596  case 0x4a: { II ii = adc_hl_SS<BC>(); NEXT; }
1597  case 0x5a: { II ii = adc_hl_SS<DE>(); NEXT; }
1598  case 0x6a: { II ii = adc_hl_hl (); NEXT; }
1599  case 0x7a: { II ii = adc_hl_SS<SP>(); NEXT; }
1600 
1601  case 0x43: { II ii = ld_xword_SS_ED<BC>(); NEXT; }
1602  case 0x53: { II ii = ld_xword_SS_ED<DE>(); NEXT; }
1603  case 0x63: { II ii = ld_xword_SS_ED<HL>(); NEXT; }
1604  case 0x73: { II ii = ld_xword_SS_ED<SP>(); NEXT; }
1605 
1606  case 0x4b: { II ii = ld_SS_xword_ED<BC>(); NEXT; }
1607  case 0x5b: { II ii = ld_SS_xword_ED<DE>(); NEXT; }
1608  case 0x6b: { II ii = ld_SS_xword_ED<HL>(); NEXT; }
1609  case 0x7b: { II ii = ld_SS_xword_ED<SP>(); NEXT; }
1610 
1611  case 0x47: { II ii = ld_i_a(); NEXT; }
1612  case 0x4f: { II ii = ld_r_a(); NEXT; }
1613  case 0x57: { II ii = ld_a_IR<REG_I>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1614  case 0x5f: { II ii = ld_a_IR<REG_R>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1615 
1616  case 0x67: { II ii = rrd(); NEXT; }
1617  case 0x6f: { II ii = rld(); NEXT; }
1618 
1619  case 0x45: case 0x4d: case 0x55: case 0x5d:
1620  case 0x65: case 0x6d: case 0x75: case 0x7d:
1621  { II ii = retn(); NEXT_STOP; }
1622  case 0x46: case 0x4e: case 0x66: case 0x6e:
1623  { II ii = im_N<0>(); NEXT; }
1624  case 0x56: case 0x76:
1625  { II ii = im_N<1>(); NEXT; }
1626  case 0x5e: case 0x7e:
1627  { II ii = im_N<2>(); NEXT; }
1628  case 0x44: case 0x4c: case 0x54: case 0x5c:
1629  case 0x64: case 0x6c: case 0x74: case 0x7c:
1630  { II ii = neg(); NEXT; }
1631 
1632  case 0xa0: { II ii = ldi(); NEXT; }
1633  case 0xa1: { II ii = cpi(); NEXT; }
1634  case 0xa2: { II ii = ini(); NEXT; }
1635  case 0xa3: { II ii = outi(); NEXT; }
1636  case 0xa8: { II ii = ldd(); NEXT; }
1637  case 0xa9: { II ii = cpd(); NEXT; }
1638  case 0xaa: { II ii = ind(); NEXT; }
1639  case 0xab: { II ii = outd(); NEXT; }
1640  case 0xb0: { II ii = ldir(); NEXT; }
1641  case 0xb1: { II ii = cpir(); NEXT; }
1642  case 0xb2: { II ii = inir(); NEXT; }
1643  case 0xb3: { II ii = otir(); NEXT; }
1644  case 0xb8: { II ii = lddr(); NEXT; }
1645  case 0xb9: { II ii = cpdr(); NEXT; }
1646  case 0xba: { II ii = indr(); NEXT; }
1647  case 0xbb: { II ii = otdr(); NEXT; }
1648 
1649  case 0xc1: { II ii = T::isR800() ? mulub_a_R<B>() : nop(); NEXT; }
1650  case 0xc9: { II ii = T::isR800() ? mulub_a_R<C>() : nop(); NEXT; }
1651  case 0xd1: { II ii = T::isR800() ? mulub_a_R<D>() : nop(); NEXT; }
1652  case 0xd9: { II ii = T::isR800() ? mulub_a_R<E>() : nop(); NEXT; }
1653  case 0xc3: { II ii = T::isR800() ? muluw_hl_SS<BC>() : nop(); NEXT; }
1654  case 0xf3: { II ii = T::isR800() ? muluw_hl_SS<SP>() : nop(); NEXT; }
1655  default: UNREACHABLE; return;
1656  }
1657 }
1658 opDD_2:
1659 CASE(DD) {
1660  setPC(getPC() + 1); // M1 cycle at this point
1661  byte opcodeDD = RDMEM_OPCODE<0>(T::CC_DD + T::CC_MAIN);
1662  incR(1);
1663  switch (opcodeDD) {
1664  case 0x00: // nop();
1665  case 0x01: // ld_bc_word();
1666  case 0x02: // ld_xbc_a();
1667  case 0x03: // inc_bc();
1668  case 0x04: // inc_b();
1669  case 0x05: // dec_b();
1670  case 0x06: // ld_b_byte();
1671  case 0x07: // rlca();
1672  case 0x08: // ex_af_af();
1673  case 0x0a: // ld_a_xbc();
1674  case 0x0b: // dec_bc();
1675  case 0x0c: // inc_c();
1676  case 0x0d: // dec_c();
1677  case 0x0e: // ld_c_byte();
1678  case 0x0f: // rrca();
1679  case 0x10: // djnz();
1680  case 0x11: // ld_de_word();
1681  case 0x12: // ld_xde_a();
1682  case 0x13: // inc_de();
1683  case 0x14: // inc_d();
1684  case 0x15: // dec_d();
1685  case 0x16: // ld_d_byte();
1686  case 0x17: // rla();
1687  case 0x18: // jr();
1688  case 0x1a: // ld_a_xde();
1689  case 0x1b: // dec_de();
1690  case 0x1c: // inc_e();
1691  case 0x1d: // dec_e();
1692  case 0x1e: // ld_e_byte();
1693  case 0x1f: // rra();
1694  case 0x20: // jr_nz();
1695  case 0x27: // daa();
1696  case 0x28: // jr_z();
1697  case 0x2f: // cpl();
1698  case 0x30: // jr_nc();
1699  case 0x31: // ld_sp_word();
1700  case 0x32: // ld_xbyte_a();
1701  case 0x33: // inc_sp();
1702  case 0x37: // scf();
1703  case 0x38: // jr_c();
1704  case 0x3a: // ld_a_xbyte();
1705  case 0x3b: // dec_sp();
1706  case 0x3c: // inc_a();
1707  case 0x3d: // dec_a();
1708  case 0x3e: // ld_a_byte();
1709  case 0x3f: // ccf();
1710 
1711  case 0x40: // ld_b_b();
1712  case 0x41: // ld_b_c();
1713  case 0x42: // ld_b_d();
1714  case 0x43: // ld_b_e();
1715  case 0x47: // ld_b_a();
1716  case 0x48: // ld_c_b();
1717  case 0x49: // ld_c_c();
1718  case 0x4a: // ld_c_d();
1719  case 0x4b: // ld_c_e();
1720  case 0x4f: // ld_c_a();
1721  case 0x50: // ld_d_b();
1722  case 0x51: // ld_d_c();
1723  case 0x52: // ld_d_d();
1724  case 0x53: // ld_d_e();
1725  case 0x57: // ld_d_a();
1726  case 0x58: // ld_e_b();
1727  case 0x59: // ld_e_c();
1728  case 0x5a: // ld_e_d();
1729  case 0x5b: // ld_e_e();
1730  case 0x5f: // ld_e_a();
1731  case 0x64: // ld_ixh_ixh(); == nop
1732  case 0x6d: // ld_ixl_ixl(); == nop
1733  case 0x76: // halt();
1734  case 0x78: // ld_a_b();
1735  case 0x79: // ld_a_c();
1736  case 0x7a: // ld_a_d();
1737  case 0x7b: // ld_a_e();
1738  case 0x7f: // ld_a_a();
1739 
1740  case 0x80: // add_a_b();
1741  case 0x81: // add_a_c();
1742  case 0x82: // add_a_d();
1743  case 0x83: // add_a_e();
1744  case 0x87: // add_a_a();
1745  case 0x88: // adc_a_b();
1746  case 0x89: // adc_a_c();
1747  case 0x8a: // adc_a_d();
1748  case 0x8b: // adc_a_e();
1749  case 0x8f: // adc_a_a();
1750  case 0x90: // sub_b();
1751  case 0x91: // sub_c();
1752  case 0x92: // sub_d();
1753  case 0x93: // sub_e();
1754  case 0x97: // sub_a();
1755  case 0x98: // sbc_a_b();
1756  case 0x99: // sbc_a_c();
1757  case 0x9a: // sbc_a_d();
1758  case 0x9b: // sbc_a_e();
1759  case 0x9f: // sbc_a_a();
1760  case 0xa0: // and_b();
1761  case 0xa1: // and_c();
1762  case 0xa2: // and_d();
1763  case 0xa3: // and_e();
1764  case 0xa7: // and_a();
1765  case 0xa8: // xor_b();
1766  case 0xa9: // xor_c();
1767  case 0xaa: // xor_d();
1768  case 0xab: // xor_e();
1769  case 0xaf: // xor_a();
1770  case 0xb0: // or_b();
1771  case 0xb1: // or_c();
1772  case 0xb2: // or_d();
1773  case 0xb3: // or_e();
1774  case 0xb7: // or_a();
1775  case 0xb8: // cp_b();
1776  case 0xb9: // cp_c();
1777  case 0xba: // cp_d();
1778  case 0xbb: // cp_e();
1779  case 0xbf: // cp_a();
1780 
1781  case 0xc0: // ret_nz();
1782  case 0xc1: // pop_bc();
1783  case 0xc2: // jp_nz();
1784  case 0xc3: // jp();
1785  case 0xc4: // call_nz();
1786  case 0xc5: // push_bc();
1787  case 0xc6: // add_a_byte();
1788  case 0xc7: // rst_00();
1789  case 0xc8: // ret_z();
1790  case 0xc9: // ret();
1791  case 0xca: // jp_z();
1792  case 0xcc: // call_z();
1793  case 0xcd: // call();
1794  case 0xce: // adc_a_byte();
1795  case 0xcf: // rst_08();
1796  case 0xd0: // ret_nc();
1797  case 0xd1: // pop_de();
1798  case 0xd2: // jp_nc();
1799  case 0xd3: // out_byte_a();
1800  case 0xd4: // call_nc();
1801  case 0xd5: // push_de();
1802  case 0xd6: // sub_byte();
1803  case 0xd7: // rst_10();
1804  case 0xd8: // ret_c();
1805  case 0xd9: // exx();
1806  case 0xda: // jp_c();
1807  case 0xdb: // in_a_byte();
1808  case 0xdc: // call_c();
1809  case 0xde: // sbc_a_byte();
1810  case 0xdf: // rst_18();
1811  case 0xe0: // ret_po();
1812  case 0xe2: // jp_po();
1813  case 0xe4: // call_po();
1814  case 0xe6: // and_byte();
1815  case 0xe7: // rst_20();
1816  case 0xe8: // ret_pe();
1817  case 0xea: // jp_pe();
1818  case 0xeb: // ex_de_hl();
1819  case 0xec: // call_pe();
1820  case 0xed: // ed();
1821  case 0xee: // xor_byte();
1822  case 0xef: // rst_28();
1823  case 0xf0: // ret_p();
1824  case 0xf1: // pop_af();
1825  case 0xf2: // jp_p();
1826  case 0xf3: // di();
1827  case 0xf4: // call_p();
1828  case 0xf5: // push_af();
1829  case 0xf6: // or_byte();
1830  case 0xf7: // rst_30();
1831  case 0xf8: // ret_m();
1832  case 0xfa: // jp_m();
1833  case 0xfb: // ei();
1834  case 0xfc: // call_m();
1835  case 0xfe: // cp_byte();
1836  case 0xff: // rst_38();
1837  if (T::isR800()) {
1838  II ii = nop();
1839  ii.cycles += T::CC_DD;
1840  NEXT;
1841  } else {
1842  T::add(T::CC_DD);
1843  #ifdef USE_COMPUTED_GOTO
1844  goto *(opcodeTable[opcodeDD]);
1845  #else
1846  opcodeMain = opcodeDD;
1847  goto switchopcode;
1848  #endif
1849  }
1850 
1851  case 0x09: { II ii = add_SS_TT<IX,BC,T::CC_DD>(); NEXT; }
1852  case 0x19: { II ii = add_SS_TT<IX,DE,T::CC_DD>(); NEXT; }
1853  case 0x29: { II ii = add_SS_SS<IX ,T::CC_DD>(); NEXT; }
1854  case 0x39: { II ii = add_SS_TT<IX,SP,T::CC_DD>(); NEXT; }
1855  case 0x21: { II ii = ld_SS_word<IX,T::CC_DD>(); NEXT; }
1856  case 0x22: { II ii = ld_xword_SS<IX,T::CC_DD>(); NEXT; }
1857  case 0x2a: { II ii = ld_SS_xword<IX,T::CC_DD>(); NEXT; }
1858  case 0x23: { II ii = inc_SS<IX,T::CC_DD>(); NEXT; }
1859  case 0x2b: { II ii = dec_SS<IX,T::CC_DD>(); NEXT; }
1860  case 0x24: { II ii = inc_R<IXH,T::CC_DD>(); NEXT; }
1861  case 0x2c: { II ii = inc_R<IXL,T::CC_DD>(); NEXT; }
1862  case 0x25: { II ii = dec_R<IXH,T::CC_DD>(); NEXT; }
1863  case 0x2d: { II ii = dec_R<IXL,T::CC_DD>(); NEXT; }
1864  case 0x26: { II ii = ld_R_byte<IXH,T::CC_DD>(); NEXT; }
1865  case 0x2e: { II ii = ld_R_byte<IXL,T::CC_DD>(); NEXT; }
1866  case 0x34: { II ii = inc_xix<IX>(); NEXT; }
1867  case 0x35: { II ii = dec_xix<IX>(); NEXT; }
1868  case 0x36: { II ii = ld_xix_byte<IX>(); NEXT; }
1869 
1870  case 0x44: { II ii = ld_R_R<B,IXH,T::CC_DD>(); NEXT; }
1871  case 0x45: { II ii = ld_R_R<B,IXL,T::CC_DD>(); NEXT; }
1872  case 0x4c: { II ii = ld_R_R<C,IXH,T::CC_DD>(); NEXT; }
1873  case 0x4d: { II ii = ld_R_R<C,IXL,T::CC_DD>(); NEXT; }
1874  case 0x54: { II ii = ld_R_R<D,IXH,T::CC_DD>(); NEXT; }
1875  case 0x55: { II ii = ld_R_R<D,IXL,T::CC_DD>(); NEXT; }
1876  case 0x5c: { II ii = ld_R_R<E,IXH,T::CC_DD>(); NEXT; }
1877  case 0x5d: { II ii = ld_R_R<E,IXL,T::CC_DD>(); NEXT; }
1878  case 0x7c: { II ii = ld_R_R<A,IXH,T::CC_DD>(); NEXT; }
1879  case 0x7d: { II ii = ld_R_R<A,IXL,T::CC_DD>(); NEXT; }
1880  case 0x60: { II ii = ld_R_R<IXH,B,T::CC_DD>(); NEXT; }
1881  case 0x61: { II ii = ld_R_R<IXH,C,T::CC_DD>(); NEXT; }
1882  case 0x62: { II ii = ld_R_R<IXH,D,T::CC_DD>(); NEXT; }
1883  case 0x63: { II ii = ld_R_R<IXH,E,T::CC_DD>(); NEXT; }
1884  case 0x65: { II ii = ld_R_R<IXH,IXL,T::CC_DD>(); NEXT; }
1885  case 0x67: { II ii = ld_R_R<IXH,A,T::CC_DD>(); NEXT; }
1886  case 0x68: { II ii = ld_R_R<IXL,B,T::CC_DD>(); NEXT; }
1887  case 0x69: { II ii = ld_R_R<IXL,C,T::CC_DD>(); NEXT; }
1888  case 0x6a: { II ii = ld_R_R<IXL,D,T::CC_DD>(); NEXT; }
1889  case 0x6b: { II ii = ld_R_R<IXL,E,T::CC_DD>(); NEXT; }
1890  case 0x6c: { II ii = ld_R_R<IXL,IXH,T::CC_DD>(); NEXT; }
1891  case 0x6f: { II ii = ld_R_R<IXL,A,T::CC_DD>(); NEXT; }
1892  case 0x70: { II ii = ld_xix_R<IX,B>(); NEXT; }
1893  case 0x71: { II ii = ld_xix_R<IX,C>(); NEXT; }
1894  case 0x72: { II ii = ld_xix_R<IX,D>(); NEXT; }
1895  case 0x73: { II ii = ld_xix_R<IX,E>(); NEXT; }
1896  case 0x74: { II ii = ld_xix_R<IX,H>(); NEXT; }
1897  case 0x75: { II ii = ld_xix_R<IX,L>(); NEXT; }
1898  case 0x77: { II ii = ld_xix_R<IX,A>(); NEXT; }
1899  case 0x46: { II ii = ld_R_xix<B,IX>(); NEXT; }
1900  case 0x4e: { II ii = ld_R_xix<C,IX>(); NEXT; }
1901  case 0x56: { II ii = ld_R_xix<D,IX>(); NEXT; }
1902  case 0x5e: { II ii = ld_R_xix<E,IX>(); NEXT; }
1903  case 0x66: { II ii = ld_R_xix<H,IX>(); NEXT; }
1904  case 0x6e: { II ii = ld_R_xix<L,IX>(); NEXT; }
1905  case 0x7e: { II ii = ld_R_xix<A,IX>(); NEXT; }
1906 
1907  case 0x84: { II ii = add_a_R<IXH,T::CC_DD>(); NEXT; }
1908  case 0x85: { II ii = add_a_R<IXL,T::CC_DD>(); NEXT; }
1909  case 0x86: { II ii = add_a_xix<IX>(); NEXT; }
1910  case 0x8c: { II ii = adc_a_R<IXH,T::CC_DD>(); NEXT; }
1911  case 0x8d: { II ii = adc_a_R<IXL,T::CC_DD>(); NEXT; }
1912  case 0x8e: { II ii = adc_a_xix<IX>(); NEXT; }
1913  case 0x94: { II ii = sub_R<IXH,T::CC_DD>(); NEXT; }
1914  case 0x95: { II ii = sub_R<IXL,T::CC_DD>(); NEXT; }
1915  case 0x96: { II ii = sub_xix<IX>(); NEXT; }
1916  case 0x9c: { II ii = sbc_a_R<IXH,T::CC_DD>(); NEXT; }
1917  case 0x9d: { II ii = sbc_a_R<IXL,T::CC_DD>(); NEXT; }
1918  case 0x9e: { II ii = sbc_a_xix<IX>(); NEXT; }
1919  case 0xa4: { II ii = and_R<IXH,T::CC_DD>(); NEXT; }
1920  case 0xa5: { II ii = and_R<IXL,T::CC_DD>(); NEXT; }
1921  case 0xa6: { II ii = and_xix<IX>(); NEXT; }
1922  case 0xac: { II ii = xor_R<IXH,T::CC_DD>(); NEXT; }
1923  case 0xad: { II ii = xor_R<IXL,T::CC_DD>(); NEXT; }
1924  case 0xae: { II ii = xor_xix<IX>(); NEXT; }
1925  case 0xb4: { II ii = or_R<IXH,T::CC_DD>(); NEXT; }
1926  case 0xb5: { II ii = or_R<IXL,T::CC_DD>(); NEXT; }
1927  case 0xb6: { II ii = or_xix<IX>(); NEXT; }
1928  case 0xbc: { II ii = cp_R<IXH,T::CC_DD>(); NEXT; }
1929  case 0xbd: { II ii = cp_R<IXL,T::CC_DD>(); NEXT; }
1930  case 0xbe: { II ii = cp_xix<IX>(); NEXT; }
1931 
1932  case 0xe1: { II ii = pop_SS <IX,T::CC_DD>(); NEXT; }
1933  case 0xe5: { II ii = push_SS<IX,T::CC_DD>(); NEXT; }
1934  case 0xe3: { II ii = ex_xsp_SS<IX,T::CC_DD>(); NEXT; }
1935  case 0xe9: { II ii = jp_SS<IX,T::CC_DD>(); NEXT; }
1936  case 0xf9: { II ii = ld_sp_SS<IX,T::CC_DD>(); NEXT; }
1937  case 0xcb: ixy = getIX(); goto xx_cb;
1938  case 0xdd: T::add(T::CC_DD); goto opDD_2;
1939  case 0xfd: T::add(T::CC_DD); goto opFD_2;
1940  default: UNREACHABLE; return;
1941  }
1942 }
1943 opFD_2:
1944 CASE(FD) {
1945  setPC(getPC() + 1); // M1 cycle at this point
1946  byte opcodeFD = RDMEM_OPCODE<0>(T::CC_DD + T::CC_MAIN);
1947  incR(1);
1948  switch (opcodeFD) {
1949  case 0x00: // nop();
1950  case 0x01: // ld_bc_word();
1951  case 0x02: // ld_xbc_a();
1952  case 0x03: // inc_bc();
1953  case 0x04: // inc_b();
1954  case 0x05: // dec_b();
1955  case 0x06: // ld_b_byte();
1956  case 0x07: // rlca();
1957  case 0x08: // ex_af_af();
1958  case 0x0a: // ld_a_xbc();
1959  case 0x0b: // dec_bc();
1960  case 0x0c: // inc_c();
1961  case 0x0d: // dec_c();
1962  case 0x0e: // ld_c_byte();
1963  case 0x0f: // rrca();
1964  case 0x10: // djnz();
1965  case 0x11: // ld_de_word();
1966  case 0x12: // ld_xde_a();
1967  case 0x13: // inc_de();
1968  case 0x14: // inc_d();
1969  case 0x15: // dec_d();
1970  case 0x16: // ld_d_byte();
1971  case 0x17: // rla();
1972  case 0x18: // jr();
1973  case 0x1a: // ld_a_xde();
1974  case 0x1b: // dec_de();
1975  case 0x1c: // inc_e();
1976  case 0x1d: // dec_e();
1977  case 0x1e: // ld_e_byte();
1978  case 0x1f: // rra();
1979  case 0x20: // jr_nz();
1980  case 0x27: // daa();
1981  case 0x28: // jr_z();
1982  case 0x2f: // cpl();
1983  case 0x30: // jr_nc();
1984  case 0x31: // ld_sp_word();
1985  case 0x32: // ld_xbyte_a();
1986  case 0x33: // inc_sp();
1987  case 0x37: // scf();
1988  case 0x38: // jr_c();
1989  case 0x3a: // ld_a_xbyte();
1990  case 0x3b: // dec_sp();
1991  case 0x3c: // inc_a();
1992  case 0x3d: // dec_a();
1993  case 0x3e: // ld_a_byte();
1994  case 0x3f: // ccf();
1995 
1996  case 0x40: // ld_b_b();
1997  case 0x41: // ld_b_c();
1998  case 0x42: // ld_b_d();
1999  case 0x43: // ld_b_e();
2000  case 0x47: // ld_b_a();
2001  case 0x48: // ld_c_b();
2002  case 0x49: // ld_c_c();
2003  case 0x4a: // ld_c_d();
2004  case 0x4b: // ld_c_e();
2005  case 0x4f: // ld_c_a();
2006  case 0x50: // ld_d_b();
2007  case 0x51: // ld_d_c();
2008  case 0x52: // ld_d_d();
2009  case 0x53: // ld_d_e();
2010  case 0x57: // ld_d_a();
2011  case 0x58: // ld_e_b();
2012  case 0x59: // ld_e_c();
2013  case 0x5a: // ld_e_d();
2014  case 0x5b: // ld_e_e();
2015  case 0x5f: // ld_e_a();
2016  case 0x64: // ld_ixh_ixh(); == nop
2017  case 0x6d: // ld_ixl_ixl(); == nop
2018  case 0x76: // halt();
2019  case 0x78: // ld_a_b();
2020  case 0x79: // ld_a_c();
2021  case 0x7a: // ld_a_d();
2022  case 0x7b: // ld_a_e();
2023  case 0x7f: // ld_a_a();
2024 
2025  case 0x80: // add_a_b();
2026  case 0x81: // add_a_c();
2027  case 0x82: // add_a_d();
2028  case 0x83: // add_a_e();
2029  case 0x87: // add_a_a();
2030  case 0x88: // adc_a_b();
2031  case 0x89: // adc_a_c();
2032  case 0x8a: // adc_a_d();
2033  case 0x8b: // adc_a_e();
2034  case 0x8f: // adc_a_a();
2035  case 0x90: // sub_b();
2036  case 0x91: // sub_c();
2037  case 0x92: // sub_d();
2038  case 0x93: // sub_e();
2039  case 0x97: // sub_a();
2040  case 0x98: // sbc_a_b();
2041  case 0x99: // sbc_a_c();
2042  case 0x9a: // sbc_a_d();
2043  case 0x9b: // sbc_a_e();
2044  case 0x9f: // sbc_a_a();
2045  case 0xa0: // and_b();
2046  case 0xa1: // and_c();
2047  case 0xa2: // and_d();
2048  case 0xa3: // and_e();
2049  case 0xa7: // and_a();
2050  case 0xa8: // xor_b();
2051  case 0xa9: // xor_c();
2052  case 0xaa: // xor_d();
2053  case 0xab: // xor_e();
2054  case 0xaf: // xor_a();
2055  case 0xb0: // or_b();
2056  case 0xb1: // or_c();
2057  case 0xb2: // or_d();
2058  case 0xb3: // or_e();
2059  case 0xb7: // or_a();
2060  case 0xb8: // cp_b();
2061  case 0xb9: // cp_c();
2062  case 0xba: // cp_d();
2063  case 0xbb: // cp_e();
2064  case 0xbf: // cp_a();
2065 
2066  case 0xc0: // ret_nz();
2067  case 0xc1: // pop_bc();
2068  case 0xc2: // jp_nz();
2069  case 0xc3: // jp();
2070  case 0xc4: // call_nz();
2071  case 0xc5: // push_bc();
2072  case 0xc6: // add_a_byte();
2073  case 0xc7: // rst_00();
2074  case 0xc8: // ret_z();
2075  case 0xc9: // ret();
2076  case 0xca: // jp_z();
2077  case 0xcc: // call_z();
2078  case 0xcd: // call();
2079  case 0xce: // adc_a_byte();
2080  case 0xcf: // rst_08();
2081  case 0xd0: // ret_nc();
2082  case 0xd1: // pop_de();
2083  case 0xd2: // jp_nc();
2084  case 0xd3: // out_byte_a();
2085  case 0xd4: // call_nc();
2086  case 0xd5: // push_de();
2087  case 0xd6: // sub_byte();
2088  case 0xd7: // rst_10();
2089  case 0xd8: // ret_c();
2090  case 0xd9: // exx();
2091  case 0xda: // jp_c();
2092  case 0xdb: // in_a_byte();
2093  case 0xdc: // call_c();
2094  case 0xde: // sbc_a_byte();
2095  case 0xdf: // rst_18();
2096  case 0xe0: // ret_po();
2097  case 0xe2: // jp_po();
2098  case 0xe4: // call_po();
2099  case 0xe6: // and_byte();
2100  case 0xe7: // rst_20();
2101  case 0xe8: // ret_pe();
2102  case 0xea: // jp_pe();
2103  case 0xeb: // ex_de_hl();
2104  case 0xec: // call_pe();
2105  case 0xed: // ed();
2106  case 0xee: // xor_byte();
2107  case 0xef: // rst_28();
2108  case 0xf0: // ret_p();
2109  case 0xf1: // pop_af();
2110  case 0xf2: // jp_p();
2111  case 0xf3: // di();
2112  case 0xf4: // call_p();
2113  case 0xf5: // push_af();
2114  case 0xf6: // or_byte();
2115  case 0xf7: // rst_30();
2116  case 0xf8: // ret_m();
2117  case 0xfa: // jp_m();
2118  case 0xfb: // ei();
2119  case 0xfc: // call_m();
2120  case 0xfe: // cp_byte();
2121  case 0xff: // rst_38();
2122  if (T::isR800()) {
2123  II ii = nop();
2124  ii.cycles += T::CC_DD;
2125  NEXT;
2126  } else {
2127  T::add(T::CC_DD);
2128  #ifdef USE_COMPUTED_GOTO
2129  goto *(opcodeTable[opcodeFD]);
2130  #else
2131  opcodeMain = opcodeFD;
2132  goto switchopcode;
2133  #endif
2134  }
2135 
2136  case 0x09: { II ii = add_SS_TT<IY,BC,T::CC_DD>(); NEXT; }
2137  case 0x19: { II ii = add_SS_TT<IY,DE,T::CC_DD>(); NEXT; }
2138  case 0x29: { II ii = add_SS_SS<IY ,T::CC_DD>(); NEXT; }
2139  case 0x39: { II ii = add_SS_TT<IY,SP,T::CC_DD>(); NEXT; }
2140  case 0x21: { II ii = ld_SS_word<IY,T::CC_DD>(); NEXT; }
2141  case 0x22: { II ii = ld_xword_SS<IY,T::CC_DD>(); NEXT; }
2142  case 0x2a: { II ii = ld_SS_xword<IY,T::CC_DD>(); NEXT; }
2143  case 0x23: { II ii = inc_SS<IY,T::CC_DD>(); NEXT; }
2144  case 0x2b: { II ii = dec_SS<IY,T::CC_DD>(); NEXT; }
2145  case 0x24: { II ii = inc_R<IYH,T::CC_DD>(); NEXT; }
2146  case 0x2c: { II ii = inc_R<IYL,T::CC_DD>(); NEXT; }
2147  case 0x25: { II ii = dec_R<IYH,T::CC_DD>(); NEXT; }
2148  case 0x2d: { II ii = dec_R<IYL,T::CC_DD>(); NEXT; }
2149  case 0x26: { II ii = ld_R_byte<IYH,T::CC_DD>(); NEXT; }
2150  case 0x2e: { II ii = ld_R_byte<IYL,T::CC_DD>(); NEXT; }
2151  case 0x34: { II ii = inc_xix<IY>(); NEXT; }
2152  case 0x35: { II ii = dec_xix<IY>(); NEXT; }
2153  case 0x36: { II ii = ld_xix_byte<IY>(); NEXT; }
2154 
2155  case 0x44: { II ii = ld_R_R<B,IYH,T::CC_DD>(); NEXT; }
2156  case 0x45: { II ii = ld_R_R<B,IYL,T::CC_DD>(); NEXT; }
2157  case 0x4c: { II ii = ld_R_R<C,IYH,T::CC_DD>(); NEXT; }
2158  case 0x4d: { II ii = ld_R_R<C,IYL,T::CC_DD>(); NEXT; }
2159  case 0x54: { II ii = ld_R_R<D,IYH,T::CC_DD>(); NEXT; }
2160  case 0x55: { II ii = ld_R_R<D,IYL,T::CC_DD>(); NEXT; }
2161  case 0x5c: { II ii = ld_R_R<E,IYH,T::CC_DD>(); NEXT; }
2162  case 0x5d: { II ii = ld_R_R<E,IYL,T::CC_DD>(); NEXT; }
2163  case 0x7c: { II ii = ld_R_R<A,IYH,T::CC_DD>(); NEXT; }
2164  case 0x7d: { II ii = ld_R_R<A,IYL,T::CC_DD>(); NEXT; }
2165  case 0x60: { II ii = ld_R_R<IYH,B,T::CC_DD>(); NEXT; }
2166  case 0x61: { II ii = ld_R_R<IYH,C,T::CC_DD>(); NEXT; }
2167  case 0x62: { II ii = ld_R_R<IYH,D,T::CC_DD>(); NEXT; }
2168  case 0x63: { II ii = ld_R_R<IYH,E,T::CC_DD>(); NEXT; }
2169  case 0x65: { II ii = ld_R_R<IYH,IYL,T::CC_DD>(); NEXT; }
2170  case 0x67: { II ii = ld_R_R<IYH,A,T::CC_DD>(); NEXT; }
2171  case 0x68: { II ii = ld_R_R<IYL,B,T::CC_DD>(); NEXT; }
2172  case 0x69: { II ii = ld_R_R<IYL,C,T::CC_DD>(); NEXT; }
2173  case 0x6a: { II ii = ld_R_R<IYL,D,T::CC_DD>(); NEXT; }
2174  case 0x6b: { II ii = ld_R_R<IYL,E,T::CC_DD>(); NEXT; }
2175  case 0x6c: { II ii = ld_R_R<IYL,IYH,T::CC_DD>(); NEXT; }
2176  case 0x6f: { II ii = ld_R_R<IYL,A,T::CC_DD>(); NEXT; }
2177  case 0x70: { II ii = ld_xix_R<IY,B>(); NEXT; }
2178  case 0x71: { II ii = ld_xix_R<IY,C>(); NEXT; }
2179  case 0x72: { II ii = ld_xix_R<IY,D>(); NEXT; }
2180  case 0x73: { II ii = ld_xix_R<IY,E>(); NEXT; }
2181  case 0x74: { II ii = ld_xix_R<IY,H>(); NEXT; }
2182  case 0x75: { II ii = ld_xix_R<IY,L>(); NEXT; }
2183  case 0x77: { II ii = ld_xix_R<IY,A>(); NEXT; }
2184  case 0x46: { II ii = ld_R_xix<B,IY>(); NEXT; }
2185  case 0x4e: { II ii = ld_R_xix<C,IY>(); NEXT; }
2186  case 0x56: { II ii = ld_R_xix<D,IY>(); NEXT; }
2187  case 0x5e: { II ii = ld_R_xix<E,IY>(); NEXT; }
2188  case 0x66: { II ii = ld_R_xix<H,IY>(); NEXT; }
2189  case 0x6e: { II ii = ld_R_xix<L,IY>(); NEXT; }
2190  case 0x7e: { II ii = ld_R_xix<A,IY>(); NEXT; }
2191 
2192  case 0x84: { II ii = add_a_R<IYH,T::CC_DD>(); NEXT; }
2193  case 0x85: { II ii = add_a_R<IYL,T::CC_DD>(); NEXT; }
2194  case 0x86: { II ii = add_a_xix<IY>(); NEXT; }
2195  case 0x8c: { II ii = adc_a_R<IYH,T::CC_DD>(); NEXT; }
2196  case 0x8d: { II ii = adc_a_R<IYL,T::CC_DD>(); NEXT; }
2197  case 0x8e: { II ii = adc_a_xix<IY>(); NEXT; }
2198  case 0x94: { II ii = sub_R<IYH,T::CC_DD>(); NEXT; }
2199  case 0x95: { II ii = sub_R<IYL,T::CC_DD>(); NEXT; }
2200  case 0x96: { II ii = sub_xix<IY>(); NEXT; }
2201  case 0x9c: { II ii = sbc_a_R<IYH,T::CC_DD>(); NEXT; }
2202  case 0x9d: { II ii = sbc_a_R<IYL,T::CC_DD>(); NEXT; }
2203  case 0x9e: { II ii = sbc_a_xix<IY>(); NEXT; }
2204  case 0xa4: { II ii = and_R<IYH,T::CC_DD>(); NEXT; }
2205  case 0xa5: { II ii = and_R<IYL,T::CC_DD>(); NEXT; }
2206  case 0xa6: { II ii = and_xix<IY>(); NEXT; }
2207  case 0xac: { II ii = xor_R<IYH,T::CC_DD>(); NEXT; }
2208  case 0xad: { II ii = xor_R<IYL,T::CC_DD>(); NEXT; }
2209  case 0xae: { II ii = xor_xix<IY>(); NEXT; }
2210  case 0xb4: { II ii = or_R<IYH,T::CC_DD>(); NEXT; }
2211  case 0xb5: { II ii = or_R<IYL,T::CC_DD>(); NEXT; }
2212  case 0xb6: { II ii = or_xix<IY>(); NEXT; }
2213  case 0xbc: { II ii = cp_R<IYH,T::CC_DD>(); NEXT; }
2214  case 0xbd: { II ii = cp_R<IYL,T::CC_DD>(); NEXT; }
2215  case 0xbe: { II ii = cp_xix<IY>(); NEXT; }
2216 
2217  case 0xe1: { II ii = pop_SS <IY,T::CC_DD>(); NEXT; }
2218  case 0xe5: { II ii = push_SS<IY,T::CC_DD>(); NEXT; }
2219  case 0xe3: { II ii = ex_xsp_SS<IY,T::CC_DD>(); NEXT; }
2220  case 0xe9: { II ii = jp_SS<IY,T::CC_DD>(); NEXT; }
2221  case 0xf9: { II ii = ld_sp_SS<IY,T::CC_DD>(); NEXT; }
2222  case 0xcb: ixy = getIY(); goto xx_cb;
2223  case 0xdd: T::add(T::CC_DD); goto opDD_2;
2224  case 0xfd: T::add(T::CC_DD); goto opFD_2;
2225  default: UNREACHABLE; return;
2226  }
2227 }
2228 #ifndef USE_COMPUTED_GOTO
2229  default: UNREACHABLE; return;
2230 }
2231 #endif
2232 
2233 xx_cb: {
2234  unsigned tmp = RD_WORD_PC<1>(T::CC_DD + T::CC_DD_CB);
2235  int8_t ofst = tmp & 0xFF;
2236  unsigned addr = (ixy + ofst) & 0xFFFF;
2237  byte xxcb_opcode = tmp >> 8;
2238  switch (xxcb_opcode) {
2239  case 0x00: { II ii = rlc_xix_R<B>(addr); NEXT; }
2240  case 0x01: { II ii = rlc_xix_R<C>(addr); NEXT; }
2241  case 0x02: { II ii = rlc_xix_R<D>(addr); NEXT; }
2242  case 0x03: { II ii = rlc_xix_R<E>(addr); NEXT; }
2243  case 0x04: { II ii = rlc_xix_R<H>(addr); NEXT; }
2244  case 0x05: { II ii = rlc_xix_R<L>(addr); NEXT; }
2245  case 0x06: { II ii = rlc_xix_R<DUMMY>(addr); NEXT; }
2246  case 0x07: { II ii = rlc_xix_R<A>(addr); NEXT; }
2247  case 0x08: { II ii = rrc_xix_R<B>(addr); NEXT; }
2248  case 0x09: { II ii = rrc_xix_R<C>(addr); NEXT; }
2249  case 0x0a: { II ii = rrc_xix_R<D>(addr); NEXT; }
2250  case 0x0b: { II ii = rrc_xix_R<E>(addr); NEXT; }
2251  case 0x0c: { II ii = rrc_xix_R<H>(addr); NEXT; }
2252  case 0x0d: { II ii = rrc_xix_R<L>(addr); NEXT; }
2253  case 0x0e: { II ii = rrc_xix_R<DUMMY>(addr); NEXT; }
2254  case 0x0f: { II ii = rrc_xix_R<A>(addr); NEXT; }
2255  case 0x10: { II ii = rl_xix_R<B>(addr); NEXT; }
2256  case 0x11: { II ii = rl_xix_R<C>(addr); NEXT; }
2257  case 0x12: { II ii = rl_xix_R<D>(addr); NEXT; }
2258  case 0x13: { II ii = rl_xix_R<E>(addr); NEXT; }
2259  case 0x14: { II ii = rl_xix_R<H>(addr); NEXT; }
2260  case 0x15: { II ii = rl_xix_R<L>(addr); NEXT; }
2261  case 0x16: { II ii = rl_xix_R<DUMMY>(addr); NEXT; }
2262  case 0x17: { II ii = rl_xix_R<A>(addr); NEXT; }
2263  case 0x18: { II ii = rr_xix_R<B>(addr); NEXT; }
2264  case 0x19: { II ii = rr_xix_R<C>(addr); NEXT; }
2265  case 0x1a: { II ii = rr_xix_R<D>(addr); NEXT; }
2266  case 0x1b: { II ii = rr_xix_R<E>(addr); NEXT; }
2267  case 0x1c: { II ii = rr_xix_R<H>(addr); NEXT; }
2268  case 0x1d: { II ii = rr_xix_R<L>(addr); NEXT; }
2269  case 0x1e: { II ii = rr_xix_R<DUMMY>(addr); NEXT; }
2270  case 0x1f: { II ii = rr_xix_R<A>(addr); NEXT; }
2271  case 0x20: { II ii = sla_xix_R<B>(addr); NEXT; }
2272  case 0x21: { II ii = sla_xix_R<C>(addr); NEXT; }
2273  case 0x22: { II ii = sla_xix_R<D>(addr); NEXT; }
2274  case 0x23: { II ii = sla_xix_R<E>(addr); NEXT; }
2275  case 0x24: { II ii = sla_xix_R<H>(addr); NEXT; }
2276  case 0x25: { II ii = sla_xix_R<L>(addr); NEXT; }
2277  case 0x26: { II ii = sla_xix_R<DUMMY>(addr); NEXT; }
2278  case 0x27: { II ii = sla_xix_R<A>(addr); NEXT; }
2279  case 0x28: { II ii = sra_xix_R<B>(addr); NEXT; }
2280  case 0x29: { II ii = sra_xix_R<C>(addr); NEXT; }
2281  case 0x2a: { II ii = sra_xix_R<D>(addr); NEXT; }
2282  case 0x2b: { II ii = sra_xix_R<E>(addr); NEXT; }
2283  case 0x2c: { II ii = sra_xix_R<H>(addr); NEXT; }
2284  case 0x2d: { II ii = sra_xix_R<L>(addr); NEXT; }
2285  case 0x2e: { II ii = sra_xix_R<DUMMY>(addr); NEXT; }
2286  case 0x2f: { II ii = sra_xix_R<A>(addr); NEXT; }
2287  case 0x30: { II ii = T::isR800() ? sll2() : sll_xix_R<B>(addr); NEXT; }
2288  case 0x31: { II ii = T::isR800() ? sll2() : sll_xix_R<C>(addr); NEXT; }
2289  case 0x32: { II ii = T::isR800() ? sll2() : sll_xix_R<D>(addr); NEXT; }
2290  case 0x33: { II ii = T::isR800() ? sll2() : sll_xix_R<E>(addr); NEXT; }
2291  case 0x34: { II ii = T::isR800() ? sll2() : sll_xix_R<H>(addr); NEXT; }
2292  case 0x35: { II ii = T::isR800() ? sll2() : sll_xix_R<L>(addr); NEXT; }
2293  case 0x36: { II ii = T::isR800() ? sll2() : sll_xix_R<DUMMY>(addr); NEXT; }
2294  case 0x37: { II ii = T::isR800() ? sll2() : sll_xix_R<A>(addr); NEXT; }
2295  case 0x38: { II ii = srl_xix_R<B>(addr); NEXT; }
2296  case 0x39: { II ii = srl_xix_R<C>(addr); NEXT; }
2297  case 0x3a: { II ii = srl_xix_R<D>(addr); NEXT; }
2298  case 0x3b: { II ii = srl_xix_R<E>(addr); NEXT; }
2299  case 0x3c: { II ii = srl_xix_R<H>(addr); NEXT; }
2300  case 0x3d: { II ii = srl_xix_R<L>(addr); NEXT; }
2301  case 0x3e: { II ii = srl_xix_R<DUMMY>(addr); NEXT; }
2302  case 0x3f: { II ii = srl_xix_R<A>(addr); NEXT; }
2303 
2304  case 0x40: case 0x41: case 0x42: case 0x43:
2305  case 0x44: case 0x45: case 0x46: case 0x47:
2306  { II ii = bit_N_xix<0>(addr); NEXT; }
2307  case 0x48: case 0x49: case 0x4a: case 0x4b:
2308  case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2309  { II ii = bit_N_xix<1>(addr); NEXT; }
2310  case 0x50: case 0x51: case 0x52: case 0x53:
2311  case 0x54: case 0x55: case 0x56: case 0x57:
2312  { II ii = bit_N_xix<2>(addr); NEXT; }
2313  case 0x58: case 0x59: case 0x5a: case 0x5b:
2314  case 0x5c: case 0x5d: case 0x5e: case 0x5f:
2315  { II ii = bit_N_xix<3>(addr); NEXT; }
2316  case 0x60: case 0x61: case 0x62: case 0x63:
2317  case 0x64: case 0x65: case 0x66: case 0x67:
2318  { II ii = bit_N_xix<4>(addr); NEXT; }
2319  case 0x68: case 0x69: case 0x6a: case 0x6b:
2320  case 0x6c: case 0x6d: case 0x6e: case 0x6f:
2321  { II ii = bit_N_xix<5>(addr); NEXT; }
2322  case 0x70: case 0x71: case 0x72: case 0x73:
2323  case 0x74: case 0x75: case 0x76: case 0x77:
2324  { II ii = bit_N_xix<6>(addr); NEXT; }
2325  case 0x78: case 0x79: case 0x7a: case 0x7b:
2326  case 0x7c: case 0x7d: case 0x7e: case 0x7f:
2327  { II ii = bit_N_xix<7>(addr); NEXT; }
2328 
2329  case 0x80: { II ii = res_N_xix_R<0,B>(addr); NEXT; }
2330  case 0x81: { II ii = res_N_xix_R<0,C>(addr); NEXT; }
2331  case 0x82: { II ii = res_N_xix_R<0,D>(addr); NEXT; }
2332  case 0x83: { II ii = res_N_xix_R<0,E>(addr); NEXT; }
2333  case 0x84: { II ii = res_N_xix_R<0,H>(addr); NEXT; }
2334  case 0x85: { II ii = res_N_xix_R<0,L>(addr); NEXT; }
2335  case 0x87: { II ii = res_N_xix_R<0,A>(addr); NEXT; }
2336  case 0x88: { II ii = res_N_xix_R<1,B>(addr); NEXT; }
2337  case 0x89: { II ii = res_N_xix_R<1,C>(addr); NEXT; }
2338  case 0x8a: { II ii = res_N_xix_R<1,D>(addr); NEXT; }
2339  case 0x8b: { II ii = res_N_xix_R<1,E>(addr); NEXT; }
2340  case 0x8c: { II ii = res_N_xix_R<1,H>(addr); NEXT; }
2341  case 0x8d: { II ii = res_N_xix_R<1,L>(addr); NEXT; }
2342  case 0x8f: { II ii = res_N_xix_R<1,A>(addr); NEXT; }
2343  case 0x90: { II ii = res_N_xix_R<2,B>(addr); NEXT; }
2344  case 0x91: { II ii = res_N_xix_R<2,C>(addr); NEXT; }
2345  case 0x92: { II ii = res_N_xix_R<2,D>(addr); NEXT; }
2346  case 0x93: { II ii = res_N_xix_R<2,E>(addr); NEXT; }
2347  case 0x94: { II ii = res_N_xix_R<2,H>(addr); NEXT; }
2348  case 0x95: { II ii = res_N_xix_R<2,L>(addr); NEXT; }
2349  case 0x97: { II ii = res_N_xix_R<2,A>(addr); NEXT; }
2350  case 0x98: { II ii = res_N_xix_R<3,B>(addr); NEXT; }
2351  case 0x99: { II ii = res_N_xix_R<3,C>(addr); NEXT; }
2352  case 0x9a: { II ii = res_N_xix_R<3,D>(addr); NEXT; }
2353  case 0x9b: { II ii = res_N_xix_R<3,E>(addr); NEXT; }
2354  case 0x9c: { II ii = res_N_xix_R<3,H>(addr); NEXT; }
2355  case 0x9d: { II ii = res_N_xix_R<3,L>(addr); NEXT; }
2356  case 0x9f: { II ii = res_N_xix_R<3,A>(addr); NEXT; }
2357  case 0xa0: { II ii = res_N_xix_R<4,B>(addr); NEXT; }
2358  case 0xa1: { II ii = res_N_xix_R<4,C>(addr); NEXT; }
2359  case 0xa2: { II ii = res_N_xix_R<4,D>(addr); NEXT; }
2360  case 0xa3: { II ii = res_N_xix_R<4,E>(addr); NEXT; }
2361  case 0xa4: { II ii = res_N_xix_R<4,H>(addr); NEXT; }
2362  case 0xa5: { II ii = res_N_xix_R<4,L>(addr); NEXT; }
2363  case 0xa7: { II ii = res_N_xix_R<4,A>(addr); NEXT; }
2364  case 0xa8: { II ii = res_N_xix_R<5,B>(addr); NEXT; }
2365  case 0xa9: { II ii = res_N_xix_R<5,C>(addr); NEXT; }
2366  case 0xaa: { II ii = res_N_xix_R<5,D>(addr); NEXT; }
2367  case 0xab: { II ii = res_N_xix_R<5,E>(addr); NEXT; }
2368  case 0xac: { II ii = res_N_xix_R<5,H>(addr); NEXT; }
2369  case 0xad: { II ii = res_N_xix_R<5,L>(addr); NEXT; }
2370  case 0xaf: { II ii = res_N_xix_R<5,A>(addr); NEXT; }
2371  case 0xb0: { II ii = res_N_xix_R<6,B>(addr); NEXT; }
2372  case 0xb1: { II ii = res_N_xix_R<6,C>(addr); NEXT; }
2373  case 0xb2: { II ii = res_N_xix_R<6,D>(addr); NEXT; }
2374  case 0xb3: { II ii = res_N_xix_R<6,E>(addr); NEXT; }
2375  case 0xb4: { II ii = res_N_xix_R<6,H>(addr); NEXT; }
2376  case 0xb5: { II ii = res_N_xix_R<6,L>(addr); NEXT; }
2377  case 0xb7: { II ii = res_N_xix_R<6,A>(addr); NEXT; }
2378  case 0xb8: { II ii = res_N_xix_R<7,B>(addr); NEXT; }
2379  case 0xb9: { II ii = res_N_xix_R<7,C>(addr); NEXT; }
2380  case 0xba: { II ii = res_N_xix_R<7,D>(addr); NEXT; }
2381  case 0xbb: { II ii = res_N_xix_R<7,E>(addr); NEXT; }
2382  case 0xbc: { II ii = res_N_xix_R<7,H>(addr); NEXT; }
2383  case 0xbd: { II ii = res_N_xix_R<7,L>(addr); NEXT; }
2384  case 0xbf: { II ii = res_N_xix_R<7,A>(addr); NEXT; }
2385  case 0x86: { II ii = res_N_xix_R<0,DUMMY>(addr); NEXT; }
2386  case 0x8e: { II ii = res_N_xix_R<1,DUMMY>(addr); NEXT; }
2387  case 0x96: { II ii = res_N_xix_R<2,DUMMY>(addr); NEXT; }
2388  case 0x9e: { II ii = res_N_xix_R<3,DUMMY>(addr); NEXT; }
2389  case 0xa6: { II ii = res_N_xix_R<4,DUMMY>(addr); NEXT; }
2390  case 0xae: { II ii = res_N_xix_R<5,DUMMY>(addr); NEXT; }
2391  case 0xb6: { II ii = res_N_xix_R<6,DUMMY>(addr); NEXT; }
2392  case 0xbe: { II ii = res_N_xix_R<7,DUMMY>(addr); NEXT; }
2393 
2394  case 0xc0: { II ii = set_N_xix_R<0,B>(addr); NEXT; }
2395  case 0xc1: { II ii = set_N_xix_R<0,C>(addr); NEXT; }
2396  case 0xc2: { II ii = set_N_xix_R<0,D>(addr); NEXT; }
2397  case 0xc3: { II ii = set_N_xix_R<0,E>(addr); NEXT; }
2398  case 0xc4: { II ii = set_N_xix_R<0,H>(addr); NEXT; }
2399  case 0xc5: { II ii = set_N_xix_R<0,L>(addr); NEXT; }
2400  case 0xc7: { II ii = set_N_xix_R<0,A>(addr); NEXT; }
2401  case 0xc8: { II ii = set_N_xix_R<1,B>(addr); NEXT; }
2402  case 0xc9: { II ii = set_N_xix_R<1,C>(addr); NEXT; }
2403  case 0xca: { II ii = set_N_xix_R<1,D>(addr); NEXT; }
2404  case 0xcb: { II ii = set_N_xix_R<1,E>(addr); NEXT; }
2405  case 0xcc: { II ii = set_N_xix_R<1,H>(addr); NEXT; }
2406  case 0xcd: { II ii = set_N_xix_R<1,L>(addr); NEXT; }
2407  case 0xcf: { II ii = set_N_xix_R<1,A>(addr); NEXT; }
2408  case 0xd0: { II ii = set_N_xix_R<2,B>(addr); NEXT; }
2409  case 0xd1: { II ii = set_N_xix_R<2,C>(addr); NEXT; }
2410  case 0xd2: { II ii = set_N_xix_R<2,D>(addr); NEXT; }
2411  case 0xd3: { II ii = set_N_xix_R<2,E>(addr); NEXT; }
2412  case 0xd4: { II ii = set_N_xix_R<2,H>(addr); NEXT; }
2413  case 0xd5: { II ii = set_N_xix_R<2,L>(addr); NEXT; }
2414  case 0xd7: { II ii = set_N_xix_R<2,A>(addr); NEXT; }
2415  case 0xd8: { II ii = set_N_xix_R<3,B>(addr); NEXT; }
2416  case 0xd9: { II ii = set_N_xix_R<3,C>(addr); NEXT; }
2417  case 0xda: { II ii = set_N_xix_R<3,D>(addr); NEXT; }
2418  case 0xdb: { II ii = set_N_xix_R<3,E>(addr); NEXT; }
2419  case 0xdc: { II ii = set_N_xix_R<3,H>(addr); NEXT; }
2420  case 0xdd: { II ii = set_N_xix_R<3,L>(addr); NEXT; }
2421  case 0xdf: { II ii = set_N_xix_R<3,A>(addr); NEXT; }
2422  case 0xe0: { II ii = set_N_xix_R<4,B>(addr); NEXT; }
2423  case 0xe1: { II ii = set_N_xix_R<4,C>(addr); NEXT; }
2424  case 0xe2: { II ii = set_N_xix_R<4,D>(addr); NEXT; }
2425  case 0xe3: { II ii = set_N_xix_R<4,E>(addr); NEXT; }
2426  case 0xe4: { II ii = set_N_xix_R<4,H>(addr); NEXT; }
2427  case 0xe5: { II ii = set_N_xix_R<4,L>(addr); NEXT; }
2428  case 0xe7: { II ii = set_N_xix_R<4,A>(addr); NEXT; }
2429  case 0xe8: { II ii = set_N_xix_R<5,B>(addr); NEXT; }
2430  case 0xe9: { II ii = set_N_xix_R<5,C>(addr); NEXT; }
2431  case 0xea: { II ii = set_N_xix_R<5,D>(addr); NEXT; }
2432  case 0xeb: { II ii = set_N_xix_R<5,E>(addr); NEXT; }
2433  case 0xec: { II ii = set_N_xix_R<5,H>(addr); NEXT; }
2434  case 0xed: { II ii = set_N_xix_R<5,L>(addr); NEXT; }
2435  case 0xef: { II ii = set_N_xix_R<5,A>(addr); NEXT; }
2436  case 0xf0: { II ii = set_N_xix_R<6,B>(addr); NEXT; }
2437  case 0xf1: { II ii = set_N_xix_R<6,C>(addr); NEXT; }
2438  case 0xf2: { II ii = set_N_xix_R<6,D>(addr); NEXT; }
2439  case 0xf3: { II ii = set_N_xix_R<6,E>(addr); NEXT; }
2440  case 0xf4: { II ii = set_N_xix_R<6,H>(addr); NEXT; }
2441  case 0xf5: { II ii = set_N_xix_R<6,L>(addr); NEXT; }
2442  case 0xf7: { II ii = set_N_xix_R<6,A>(addr); NEXT; }
2443  case 0xf8: { II ii = set_N_xix_R<7,B>(addr); NEXT; }
2444  case 0xf9: { II ii = set_N_xix_R<7,C>(addr); NEXT; }
2445  case 0xfa: { II ii = set_N_xix_R<7,D>(addr); NEXT; }
2446  case 0xfb: { II ii = set_N_xix_R<7,E>(addr); NEXT; }
2447  case 0xfc: { II ii = set_N_xix_R<7,H>(addr); NEXT; }
2448  case 0xfd: { II ii = set_N_xix_R<7,L>(addr); NEXT; }
2449  case 0xff: { II ii = set_N_xix_R<7,A>(addr); NEXT; }
2450  case 0xc6: { II ii = set_N_xix_R<0,DUMMY>(addr); NEXT; }
2451  case 0xce: { II ii = set_N_xix_R<1,DUMMY>(addr); NEXT; }
2452  case 0xd6: { II ii = set_N_xix_R<2,DUMMY>(addr); NEXT; }
2453  case 0xde: { II ii = set_N_xix_R<3,DUMMY>(addr); NEXT; }
2454  case 0xe6: { II ii = set_N_xix_R<4,DUMMY>(addr); NEXT; }
2455  case 0xee: { II ii = set_N_xix_R<5,DUMMY>(addr); NEXT; }
2456  case 0xf6: { II ii = set_N_xix_R<6,DUMMY>(addr); NEXT; }
2457  case 0xfe: { II ii = set_N_xix_R<7,DUMMY>(addr); NEXT; }
2458  default: UNREACHABLE;
2459  }
2460  }
2461 }
2462 
2463 template<class T> inline void CPUCore<T>::cpuTracePre()
2464 {
2465  start_pc = getPC();
2466 }
2467 template<class T> inline void CPUCore<T>::cpuTracePost()
2468 {
2469  if (unlikely(tracingEnabled)) {
2470  cpuTracePost_slow();
2471  }
2472 }
2473 template<class T> void CPUCore<T>::cpuTracePost_slow()
2474 {
2475  byte opbuf[4];
2476  string dasmOutput;
2477  dasm(*interface, start_pc, opbuf, dasmOutput, T::getTimeFast());
2478  std::cout << std::setfill('0') << std::hex << std::setw(4) << start_pc
2479  << " : " << dasmOutput
2480  << " AF=" << std::setw(4) << getAF()
2481  << " BC=" << std::setw(4) << getBC()
2482  << " DE=" << std::setw(4) << getDE()
2483  << " HL=" << std::setw(4) << getHL()
2484  << " IX=" << std::setw(4) << getIX()
2485  << " IY=" << std::setw(4) << getIY()
2486  << " SP=" << std::setw(4) << getSP()
2487  << std::endl << std::dec;
2488 }
2489 
2490 template<class T> void CPUCore<T>::executeSlow()
2491 {
2492  if (unlikely(nmiEdge)) {
2493  nmiEdge = false;
2494  nmi(); // NMI occured
2495  } else if (unlikely(IRQStatus && getIFF1() && !prevWasEI())) {
2496  // normal interrupt
2497  if (unlikely(prevWasLDAI())) {
2498  // HACK!!!
2499  // The 'ld a,i' or 'ld a,r' instruction copies the IFF2
2500  // bit to the V flag. Though when the Z80 accepts an
2501  // IRQ directly after this instruction, the V flag is 0
2502  // (instead of the expected value 1). This can probably
2503  // be explained if you look at the pipeline of the Z80.
2504  // But for speed reasons we implement it here as a
2505  // fix-up (a hack) in the IRQ routine. This behaviour
2506  // is actually a bug in the Z80.
2507  // Thanks to n_n for reporting this behaviour. I think
2508  // this was discovered by GuyveR800. Also thanks to
2509  // n_n for writing a test program that demonstrates
2510  // this quirk.
2511  // I also wrote a test program that demonstrates this
2512  // behaviour is the same whether 'ld a,i' is preceded
2513  // by a 'ei' instruction or not (so it's not caused by
2514  // the 'delayed IRQ acceptance of ei').
2515  assert(getF() & V_FLAG);
2516  setF(getF() & ~V_FLAG);
2517  }
2518  IRQAccept.signal();
2519  switch (getIM()) {
2520  case 0: irq0();
2521  break;
2522  case 1: irq1();
2523  break;
2524  case 2: irq2();
2525  break;
2526  default:
2527  UNREACHABLE;
2528  }
2529  } else if (unlikely(getHALT())) {
2530  // in halt mode
2531  incR(T::advanceHalt(T::haltStates(), scheduler.getNext()));
2532  setSlowInstructions();
2533  } else {
2534  cpuTracePre();
2535  assert(T::limitReached()); // we want only one instruction
2536  executeInstructions();
2537  endInstruction();
2538 
2539  if (T::isR800()) {
2540  if (unlikely(prev2WasCall()) && likely(!prevWasPopRet())) {
2541  // On R800 a CALL or RST instruction not _immediately_
2542  // followed by a (single-byte) POP or RET instruction
2543  // causes an extra cycle in that following instruction.
2544  // No idea why yet. See doc/internal/r800-call.txt
2545  // for more information.
2546  //
2547  // TODO this implementation adds the extra cycle at
2548  // the end of the instruction POP/RET. It is not known
2549  // where in the instruction the real R800 adds this cycle.
2550  T::add(1);
2551  }
2552  }
2553  cpuTracePost();
2554  }
2555 }
2556 
2557 template<class T> void CPUCore<T>::execute(bool fastForward)
2558 {
2559  // In fast-forward mode, breakpoints, watchpoints or debug condtions
2560  // won't trigger. It is possible we already are in break mode, but
2561  // break is ignored in fast-forward mode.
2562  assert(fastForward || !interface->isBreaked());
2563  if (fastForward) {
2564  interface->setFastForward(true);
2565  }
2566  execute2(fastForward);
2567  interface->setFastForward(false);
2568 }
2569 
2570 template<class T> void CPUCore<T>::execute2(bool fastForward)
2571 {
2572  // note: Don't use getTimeFast() here, because 'once in a while' we
2573  // need to CPUClock::sync() to avoid overflow.
2574  // Should be done at least once per second (approx). So only
2575  // once in this method is enough.
2576  scheduler.schedule(T::getTime());
2577  setSlowInstructions();
2578 
2579  if (!fastForward && (interface->isContinue() || interface->isStep())) {
2580  // at least one instruction
2581  interface->setContinue(false);
2582  executeSlow();
2583  scheduler.schedule(T::getTimeFast());
2584  --slowInstructions;
2585  if (interface->isStep()) {
2586  interface->setStep(false);
2587  interface->doBreak();
2588  return;
2589  }
2590  }
2591 
2592  // Note: we call scheduler _after_ executing the instruction and before
2593  // deciding between executeFast() and executeSlow() (because a
2594  // SyncPoint could set an IRQ and then we must choose executeSlow())
2595  if (fastForward ||
2596  (!interface->anyBreakPoints() && !tracingEnabled)) {
2597  // fast path, no breakpoints, no tracing
2598  while (!needExitCPULoop()) {
2599  if (slowInstructions) {
2600  --slowInstructions;
2601  executeSlow();
2602  scheduler.schedule(T::getTimeFast());
2603  } else {
2604  while (slowInstructions == 0) {
2605  T::enableLimit(); // does CPUClock::sync()
2606  if (likely(!T::limitReached())) {
2607  // multiple instructions
2608  executeInstructions();
2609  // note: pipeline only shifted one
2610  // step for multiple instructions
2611  endInstruction();
2612  }
2613  scheduler.schedule(T::getTimeFast());
2614  if (needExitCPULoop()) return;
2615  }
2616  }
2617  }
2618  } else {
2619  while (!needExitCPULoop()) {
2620  if (interface->checkBreakPoints(getPC(), motherboard)) {
2621  assert(interface->isBreaked());
2622  break;
2623  }
2624  if (slowInstructions == 0) {
2625  cpuTracePre();
2626  assert(T::limitReached()); // only one instruction
2627  executeInstructions();
2628  endInstruction();
2629  cpuTracePost();
2630  } else {
2631  --slowInstructions;
2632  executeSlow();
2633  }
2634  // Don't use getTimeFast() here, we need a call to
2635  // CPUClock::sync() 'once in a while'. (During a
2636  // reverse fast-forward this wasn't always the case).
2637  scheduler.schedule(T::getTime());
2638  }
2639  }
2640 }
2641 
2642 template<class T> template<Reg8 R8> ALWAYS_INLINE byte CPUCore<T>::get8() const {
2643  if (R8 == A) { return getA(); }
2644  else if (R8 == F) { return getF(); }
2645  else if (R8 == B) { return getB(); }
2646  else if (R8 == C) { return getC(); }
2647  else if (R8 == D) { return getD(); }
2648  else if (R8 == E) { return getE(); }
2649  else if (R8 == H) { return getH(); }
2650  else if (R8 == L) { return getL(); }
2651  else if (R8 == IXH) { return getIXh(); }
2652  else if (R8 == IXL) { return getIXl(); }
2653  else if (R8 == IYH) { return getIYh(); }
2654  else if (R8 == IYL) { return getIYl(); }
2655  else if (R8 == REG_I) { return getI(); }
2656  else if (R8 == REG_R) { return getR(); }
2657  else if (R8 == DUMMY) { return 0; }
2658  else { UNREACHABLE; return 0; }
2659 }
2660 template<class T> template<Reg16 R16> ALWAYS_INLINE unsigned CPUCore<T>::get16() const {
2661  if (R16 == AF) { return getAF(); }
2662  else if (R16 == BC) { return getBC(); }
2663  else if (R16 == DE) { return getDE(); }
2664  else if (R16 == HL) { return getHL(); }
2665  else if (R16 == IX) { return getIX(); }
2666  else if (R16 == IY) { return getIY(); }
2667  else if (R16 == SP) { return getSP(); }
2668  else { UNREACHABLE; return 0; }
2669 }
2670 template<class T> template<Reg8 R8> ALWAYS_INLINE void CPUCore<T>::set8(byte x) {
2671  if (R8 == A) { setA(x); }
2672  else if (R8 == F) { setF(x); }
2673  else if (R8 == B) { setB(x); }
2674  else if (R8 == C) { setC(x); }
2675  else if (R8 == D) { setD(x); }
2676  else if (R8 == E) { setE(x); }
2677  else if (R8 == H) { setH(x); }
2678  else if (R8 == L) { setL(x); }
2679  else if (R8 == IXH) { setIXh(x); }
2680  else if (R8 == IXL) { setIXl(x); }
2681  else if (R8 == IYH) { setIYh(x); }
2682  else if (R8 == IYL) { setIYl(x); }
2683  else if (R8 == REG_I) { setI(x); }
2684  else if (R8 == REG_R) { setR(x); }
2685  else if (R8 == DUMMY) { /* nothing */ }
2686  else { UNREACHABLE; }
2687 }
2688 template<class T> template<Reg16 R16> ALWAYS_INLINE void CPUCore<T>::set16(unsigned x) {
2689  if (R16 == AF) { setAF(x); }
2690  else if (R16 == BC) { setBC(x); }
2691  else if (R16 == DE) { setDE(x); }
2692  else if (R16 == HL) { setHL(x); }
2693  else if (R16 == IX) { setIX(x); }
2694  else if (R16 == IY) { setIY(x); }
2695  else if (R16 == SP) { setSP(x); }
2696  else { UNREACHABLE; }
2697 }
2698 
2699 // LD r,r
2700 template<class T> template<Reg8 DST, Reg8 SRC, int EE> II CPUCore<T>::ld_R_R() {
2701  set8<DST>(get8<SRC>()); return {1, T::CC_LD_R_R + EE};
2702 }
2703 
2704 // LD SP,ss
2705 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ld_sp_SS() {
2706  setSP(get16<REG>()); return {1, T::CC_LD_SP_HL + EE};
2707 }
2708 
2709 // LD (ss),a
2710 template<class T> template<Reg16 REG> II CPUCore<T>::ld_SS_a() {
2711  T::setMemPtr((getA() << 8) | ((get16<REG>() + 1) & 0xFF));
2712  WRMEM(get16<REG>(), getA(), T::CC_LD_SS_A_1);
2713  return {1, T::CC_LD_SS_A};
2714 }
2715 
2716 // LD (HL),r
2717 template<class T> template<Reg8 SRC> II CPUCore<T>::ld_xhl_R() {
2718  WRMEM(getHL(), get8<SRC>(), T::CC_LD_HL_R_1);
2719  return {1, T::CC_LD_HL_R};
2720 }
2721 
2722 // LD (IXY+e),r
2723 template<class T> template<Reg16 IXY, Reg8 SRC> II CPUCore<T>::ld_xix_R() {
2724  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_LD_XIX_R_1);
2725  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2726  T::setMemPtr(addr);
2727  WRMEM(addr, get8<SRC>(), T::CC_DD + T::CC_LD_XIX_R_2);
2728  return {2, T::CC_DD + T::CC_LD_XIX_R};
2729 }
2730 
2731 // LD (HL),n
2732 template<class T> II CPUCore<T>::ld_xhl_byte() {
2733  byte val = RDMEM_OPCODE<1>(T::CC_LD_HL_N_1);
2734  WRMEM(getHL(), val, T::CC_LD_HL_N_2);
2735  return {2, T::CC_LD_HL_N};
2736 }
2737 
2738 // LD (IXY+e),n
2739 template<class T> template<Reg16 IXY> II CPUCore<T>::ld_xix_byte() {
2740  unsigned tmp = RD_WORD_PC<1>(T::CC_DD + T::CC_LD_XIX_N_1);
2741  int8_t ofst = tmp & 0xFF;
2742  byte val = tmp >> 8;
2743  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2744  T::setMemPtr(addr);
2745  WRMEM(addr, val, T::CC_DD + T::CC_LD_XIX_N_2);
2746  return {3, T::CC_DD + T::CC_LD_XIX_N};
2747 }
2748 
2749 // LD (nn),A
2750 template<class T> II CPUCore<T>::ld_xbyte_a() {
2751  unsigned x = RD_WORD_PC<1>(T::CC_LD_NN_A_1);
2752  T::setMemPtr((getA() << 8) | ((x + 1) & 0xFF));
2753  WRMEM(x, getA(), T::CC_LD_NN_A_2);
2754  return {3, T::CC_LD_NN_A};
2755 }
2756 
2757 // LD (nn),ss
2758 template<class T> template<int EE> inline II CPUCore<T>::WR_NN_Y(unsigned reg) {
2759  unsigned addr = RD_WORD_PC<1>(T::CC_LD_XX_HL_1 + EE);
2760  T::setMemPtr(addr + 1);
2761  WR_WORD(addr, reg, T::CC_LD_XX_HL_2 + EE);
2762  return {3, T::CC_LD_XX_HL + EE};
2763 }
2764 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ld_xword_SS() {
2765  return WR_NN_Y<EE >(get16<REG>());
2766 }
2767 template<class T> template<Reg16 REG> II CPUCore<T>::ld_xword_SS_ED() {
2768  return WR_NN_Y<T::EE_ED>(get16<REG>());
2769 }
2770 
2771 // LD A,(ss)
2772 template<class T> template<Reg16 REG> II CPUCore<T>::ld_a_SS() {
2773  T::setMemPtr(get16<REG>() + 1);
2774  setA(RDMEM(get16<REG>(), T::CC_LD_A_SS_1));
2775  return {1, T::CC_LD_A_SS};
2776 }
2777 
2778 // LD A,(nn)
2779 template<class T> II CPUCore<T>::ld_a_xbyte() {
2780  unsigned addr = RD_WORD_PC<1>(T::CC_LD_A_NN_1);
2781  T::setMemPtr(addr + 1);
2782  setA(RDMEM(addr, T::CC_LD_A_NN_2));
2783  return {3, T::CC_LD_A_NN};
2784 }
2785 
2786 // LD r,n
2787 template<class T> template<Reg8 DST, int EE> II CPUCore<T>::ld_R_byte() {
2788  set8<DST>(RDMEM_OPCODE<1>(T::CC_LD_R_N_1 + EE)); return {2, T::CC_LD_R_N + EE};
2789 }
2790 
2791 // LD r,(hl)
2792 template<class T> template<Reg8 DST> II CPUCore<T>::ld_R_xhl() {
2793  set8<DST>(RDMEM(getHL(), T::CC_LD_R_HL_1)); return {1, T::CC_LD_R_HL};
2794 }
2795 
2796 // LD r,(IXY+e)
2797 template<class T> template<Reg8 DST, Reg16 IXY> II CPUCore<T>::ld_R_xix() {
2798  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_LD_R_XIX_1);
2799  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2800  T::setMemPtr(addr);
2801  set8<DST>(RDMEM(addr, T::CC_DD + T::CC_LD_R_XIX_2));
2802  return {2, T::CC_DD + T::CC_LD_R_XIX};
2803 }
2804 
2805 // LD ss,(nn)
2806 template<class T> template<int EE> inline unsigned CPUCore<T>::RD_P_XX() {
2807  unsigned addr = RD_WORD_PC<1>(T::CC_LD_HL_XX_1 + EE);
2808  T::setMemPtr(addr + 1);
2809  unsigned result = RD_WORD(addr, T::CC_LD_HL_XX_2 + EE);
2810  return result;
2811 }
2812 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ld_SS_xword() {
2813  set16<REG>(RD_P_XX<EE>()); return {3, T::CC_LD_HL_XX + EE};
2814 }
2815 template<class T> template<Reg16 REG> II CPUCore<T>::ld_SS_xword_ED() {
2816  set16<REG>(RD_P_XX<T::EE_ED>()); return {3, T::CC_LD_HL_XX + T::EE_ED};
2817 }
2818 
2819 // LD ss,nn
2820 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ld_SS_word() {
2821  set16<REG>(RD_WORD_PC<1>(T::CC_LD_SS_NN_1 + EE)); return {3, T::CC_LD_SS_NN + EE};
2822 }
2823 
2824 
2825 // ADC A,r
2826 template<class T> inline void CPUCore<T>::ADC(byte reg) {
2827  unsigned res = getA() + reg + ((getF() & C_FLAG) ? 1 : 0);
2828  byte f = ((res & 0x100) ? C_FLAG : 0) |
2829  ((getA() ^ res ^ reg) & H_FLAG) |
2830  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2831  0; // N_FLAG
2832  if (T::isR800()) {
2833  f |= table.ZS[res & 0xFF];
2834  f |= getF() & (X_FLAG | Y_FLAG);
2835  } else {
2836  f |= table.ZSXY[res & 0xFF];
2837  }
2838  setF(f);
2839  setA(res);
2840 }
2841 template<class T> inline II CPUCore<T>::adc_a_a() {
2842  unsigned res = 2 * getA() + ((getF() & C_FLAG) ? 1 : 0);
2843  byte f = ((res & 0x100) ? C_FLAG : 0) |
2844  (res & H_FLAG) |
2845  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2846  0; // N_FLAG
2847  if (T::isR800()) {
2848  f |= table.ZS[res & 0xFF];
2849  f |= getF() & (X_FLAG | Y_FLAG);
2850  } else {
2851  f |= table.ZSXY[res & 0xFF];
2852  }
2853  setF(f);
2854  setA(res);
2855  return {1, T::CC_CP_R};
2856 }
2857 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::adc_a_R() {
2858  ADC(get8<SRC>()); return {1, T::CC_CP_R + EE};
2859 }
2860 template<class T> II CPUCore<T>::adc_a_byte() {
2861  ADC(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2862 }
2863 template<class T> II CPUCore<T>::adc_a_xhl() {
2864  ADC(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2865 }
2866 template<class T> template<Reg16 IXY> II CPUCore<T>::adc_a_xix() {
2867  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2868  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2869  T::setMemPtr(addr);
2870  ADC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2871  return {2, T::CC_DD + T::CC_CP_XIX};
2872 }
2873 
2874 // ADD A,r
2875 template<class T> inline void CPUCore<T>::ADD(byte reg) {
2876  unsigned res = getA() + reg;
2877  byte f = ((res & 0x100) ? C_FLAG : 0) |
2878  ((getA() ^ res ^ reg) & H_FLAG) |
2879  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2880  0; // N_FLAG
2881  if (T::isR800()) {
2882  f |= table.ZS[res & 0xFF];
2883  f |= getF() & (X_FLAG | Y_FLAG);
2884  } else {
2885  f |= table.ZSXY[res & 0xFF];
2886  }
2887  setF(f);
2888  setA(res);
2889 }
2890 template<class T> inline II CPUCore<T>::add_a_a() {
2891  unsigned res = 2 * getA();
2892  byte f = ((res & 0x100) ? C_FLAG : 0) |
2893  (res & H_FLAG) |
2894  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2895  0; // N_FLAG
2896  if (T::isR800()) {
2897  f |= table.ZS[res & 0xFF];
2898  f |= getF() & (X_FLAG | Y_FLAG);
2899  } else {
2900  f |= table.ZSXY[res & 0xFF];
2901  }
2902  setF(f);
2903  setA(res);
2904  return {1, T::CC_CP_R};
2905 }
2906 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::add_a_R() {
2907  ADD(get8<SRC>()); return {1, T::CC_CP_R + EE};
2908 }
2909 template<class T> II CPUCore<T>::add_a_byte() {
2910  ADD(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2911 }
2912 template<class T> II CPUCore<T>::add_a_xhl() {
2913  ADD(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2914 }
2915 template<class T> template<Reg16 IXY> II CPUCore<T>::add_a_xix() {
2916  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2917  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2918  T::setMemPtr(addr);
2919  ADD(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2920  return {2, T::CC_DD + T::CC_CP_XIX};
2921 }
2922 
2923 // AND r
2924 template<class T> inline void CPUCore<T>::AND(byte reg) {
2925  setA(getA() & reg);
2926  byte f = 0;
2927  if (T::isR800()) {
2928  f |= table.ZSPH[getA()];
2929  f |= getF() & (X_FLAG | Y_FLAG);
2930  } else {
2931  f |= table.ZSPXY[getA()] | H_FLAG;
2932  }
2933  setF(f);
2934 }
2935 template<class T> II CPUCore<T>::and_a() {
2936  byte f = 0;
2937  if (T::isR800()) {
2938  f |= table.ZSPH[getA()];
2939  f |= getF() & (X_FLAG | Y_FLAG);
2940  } else {
2941  f |= table.ZSPXY[getA()] | H_FLAG;
2942  }
2943  setF(f);
2944  return {1, T::CC_CP_R};
2945 }
2946 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::and_R() {
2947  AND(get8<SRC>()); return {1, T::CC_CP_R + EE};
2948 }
2949 template<class T> II CPUCore<T>::and_byte() {
2950  AND(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2951 }
2952 template<class T> II CPUCore<T>::and_xhl() {
2953  AND(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2954 }
2955 template<class T> template<Reg16 IXY> II CPUCore<T>::and_xix() {
2956  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2957  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2958  T::setMemPtr(addr);
2959  AND(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2960  return {2, T::CC_DD + T::CC_CP_XIX};
2961 }
2962 
2963 // CP r
2964 template<class T> inline void CPUCore<T>::CP(byte reg) {
2965  unsigned q = getA() - reg;
2966  byte f = table.ZS[q & 0xFF] |
2967  ((q & 0x100) ? C_FLAG : 0) |
2968  N_FLAG |
2969  ((getA() ^ q ^ reg) & H_FLAG) |
2970  (((reg ^ getA()) & (getA() ^ q) & 0x80) >> 5); // V_FLAG
2971  if (T::isR800()) {
2972  f |= getF() & (X_FLAG | Y_FLAG);
2973  } else {
2974  f |= reg & (X_FLAG | Y_FLAG); // XY from operand, not from result
2975  }
2976  setF(f);
2977 }
2978 template<class T> II CPUCore<T>::cp_a() {
2979  byte f = ZS0 | N_FLAG;
2980  if (T::isR800()) {
2981  f |= getF() & (X_FLAG | Y_FLAG);
2982  } else {
2983  f |= getA() & (X_FLAG | Y_FLAG); // XY from operand, not from result
2984  }
2985  setF(f);
2986  return {1, T::CC_CP_R};
2987 }
2988 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::cp_R() {
2989  CP(get8<SRC>()); return {1, T::CC_CP_R + EE};
2990 }
2991 template<class T> II CPUCore<T>::cp_byte() {
2992  CP(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2993 }
2994 template<class T> II CPUCore<T>::cp_xhl() {
2995  CP(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2996 }
2997 template<class T> template<Reg16 IXY> II CPUCore<T>::cp_xix() {
2998  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2999  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3000  T::setMemPtr(addr);
3001  CP(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3002  return {2, T::CC_DD + T::CC_CP_XIX};
3003 }
3004 
3005 // OR r
3006 template<class T> inline void CPUCore<T>::OR(byte reg) {
3007  setA(getA() | reg);
3008  byte f = 0;
3009  if (T::isR800()) {
3010  f |= table.ZSP[getA()];
3011  f |= getF() & (X_FLAG | Y_FLAG);
3012  } else {
3013  f |= table.ZSPXY[getA()];
3014  }
3015  setF(f);
3016 }
3017 template<class T> II CPUCore<T>::or_a() {
3018  byte f = 0;
3019  if (T::isR800()) {
3020  f |= table.ZSP[getA()];
3021  f |= getF() & (X_FLAG | Y_FLAG);
3022  } else {
3023  f |= table.ZSPXY[getA()];
3024  }
3025  setF(f);
3026  return {1, T::CC_CP_R};
3027 }
3028 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::or_R() {
3029  OR(get8<SRC>()); return {1, T::CC_CP_R + EE};
3030 }
3031 template<class T> II CPUCore<T>::or_byte() {
3032  OR(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3033 }
3034 template<class T> II CPUCore<T>::or_xhl() {
3035  OR(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3036 }
3037 template<class T> template<Reg16 IXY> II CPUCore<T>::or_xix() {
3038  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3039  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3040  T::setMemPtr(addr);
3041  OR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3042  return {2, T::CC_DD + T::CC_CP_XIX};
3043 }
3044 
3045 // SBC A,r
3046 template<class T> inline void CPUCore<T>::SBC(byte reg) {
3047  unsigned res = getA() - reg - ((getF() & C_FLAG) ? 1 : 0);
3048  byte f = ((res & 0x100) ? C_FLAG : 0) |
3049  N_FLAG |
3050  ((getA() ^ res ^ reg) & H_FLAG) |
3051  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3052  if (T::isR800()) {
3053  f |= table.ZS[res & 0xFF];
3054  f |= getF() & (X_FLAG | Y_FLAG);
3055  } else {
3056  f |= table.ZSXY[res & 0xFF];
3057  }
3058  setF(f);
3059  setA(res);
3060 }
3061 template<class T> II CPUCore<T>::sbc_a_a() {
3062  if (T::isR800()) {
3063  word t = (getF() & C_FLAG)
3064  ? (255 * 256 | ZS255 | C_FLAG | H_FLAG | N_FLAG)
3065  : ( 0 * 256 | ZS0 | N_FLAG);
3066  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3067  } else {
3068  setAF((getF() & C_FLAG) ?
3069  (255 * 256 | ZSXY255 | C_FLAG | H_FLAG | N_FLAG) :
3070  ( 0 * 256 | ZSXY0 | N_FLAG));
3071  }
3072  return {1, T::CC_CP_R};
3073 }
3074 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::sbc_a_R() {
3075  SBC(get8<SRC>()); return {1, T::CC_CP_R + EE};
3076 }
3077 template<class T> II CPUCore<T>::sbc_a_byte() {
3078  SBC(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3079 }
3080 template<class T> II CPUCore<T>::sbc_a_xhl() {
3081  SBC(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3082 }
3083 template<class T> template<Reg16 IXY> II CPUCore<T>::sbc_a_xix() {
3084  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3085  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3086  T::setMemPtr(addr);
3087  SBC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3088  return {2, T::CC_DD + T::CC_CP_XIX};
3089 }
3090 
3091 // SUB r
3092 template<class T> inline void CPUCore<T>::SUB(byte reg) {
3093  unsigned res = getA() - reg;
3094  byte f = ((res & 0x100) ? C_FLAG : 0) |
3095  N_FLAG |
3096  ((getA() ^ res ^ reg) & H_FLAG) |
3097  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3098  if (T::isR800()) {
3099  f |= table.ZS[res & 0xFF];
3100  f |= getF() & (X_FLAG | Y_FLAG);
3101  } else {
3102  f |= table.ZSXY[res & 0xFF];
3103  }
3104  setF(f);
3105  setA(res);
3106 }
3107 template<class T> II CPUCore<T>::sub_a() {
3108  if (T::isR800()) {
3109  word t = 0 * 256 | ZS0 | N_FLAG;
3110  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3111  } else {
3112  setAF(0 * 256 | ZSXY0 | N_FLAG);
3113  }
3114  return {1, T::CC_CP_R};
3115 }
3116 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::sub_R() {
3117  SUB(get8<SRC>()); return {1, T::CC_CP_R + EE};
3118 }
3119 template<class T> II CPUCore<T>::sub_byte() {
3120  SUB(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3121 }
3122 template<class T> II CPUCore<T>::sub_xhl() {
3123  SUB(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3124 }
3125 template<class T> template<Reg16 IXY> II CPUCore<T>::sub_xix() {
3126  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3127  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3128  T::setMemPtr(addr);
3129  SUB(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3130  return {2, T::CC_DD + T::CC_CP_XIX};
3131 }
3132 
3133 // XOR r
3134 template<class T> inline void CPUCore<T>::XOR(byte reg) {
3135  setA(getA() ^ reg);
3136  byte f = 0;
3137  if (T::isR800()) {
3138  f |= table.ZSP[getA()];
3139  f |= getF() & (X_FLAG | Y_FLAG);
3140  } else {
3141  f |= table.ZSPXY[getA()];
3142  }
3143  setF(f);
3144 }
3145 template<class T> II CPUCore<T>::xor_a() {
3146  if (T::isR800()) {
3147  word t = 0 * 256 + ZSP0;
3148  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3149  } else {
3150  setAF(0 * 256 + ZSPXY0);
3151  }
3152  return {1, T::CC_CP_R};
3153 }
3154 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::xor_R() {
3155  XOR(get8<SRC>()); return {1, T::CC_CP_R + EE};
3156 }
3157 template<class T> II CPUCore<T>::xor_byte() {
3158  XOR(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3159 }
3160 template<class T> II CPUCore<T>::xor_xhl() {
3161  XOR(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3162 }
3163 template<class T> template<Reg16 IXY> II CPUCore<T>::xor_xix() {
3164  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3165  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3166  T::setMemPtr(addr);
3167  XOR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3168  return {2, T::CC_DD + T::CC_CP_XIX};
3169 }
3170 
3171 
3172 // DEC r
3173 template<class T> inline byte CPUCore<T>::DEC(byte reg) {
3174  byte res = reg - 1;
3175  byte f = ((reg & ~res & 0x80) >> 5) | // V_FLAG
3176  (((res & 0x0F) + 1) & H_FLAG) |
3177  N_FLAG;
3178  if (T::isR800()) {
3179  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3180  f |= table.ZS[res];
3181  } else {
3182  f |= getF() & C_FLAG;
3183  f |= table.ZSXY[res];
3184  }
3185  setF(f);
3186  return res;
3187 }
3188 template<class T> template<Reg8 REG, int EE> II CPUCore<T>::dec_R() {
3189  set8<REG>(DEC(get8<REG>())); return {1, T::CC_INC_R + EE};
3190 }
3191 template<class T> template<int EE> inline void CPUCore<T>::DEC_X(unsigned x) {
3192  byte val = DEC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3193  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3194 }
3195 template<class T> II CPUCore<T>::dec_xhl() {
3196  DEC_X<0>(getHL());
3197  return {1, T::CC_INC_XHL};
3198 }
3199 template<class T> template<Reg16 IXY> II CPUCore<T>::dec_xix() {
3200  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_INC_XIX_1);
3201  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3202  T::setMemPtr(addr);
3203  DEC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3204  return {2, T::CC_INC_XHL + T::CC_DD + T::EE_INC_XIX};
3205 }
3206 
3207 // INC r
3208 template<class T> inline byte CPUCore<T>::INC(byte reg) {
3209  reg++;
3210  byte f = ((reg & -reg & 0x80) >> 5) | // V_FLAG
3211  (((reg & 0x0F) - 1) & H_FLAG) |
3212  0; // N_FLAG
3213  if (T::isR800()) {
3214  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3215  f |= table.ZS[reg];
3216  } else {
3217  f |= getF() & C_FLAG;
3218  f |= table.ZSXY[reg];
3219  }
3220  setF(f);
3221  return reg;
3222 }
3223 template<class T> template<Reg8 REG, int EE> II CPUCore<T>::inc_R() {
3224  set8<REG>(INC(get8<REG>())); return {1, T::CC_INC_R + EE};
3225 }
3226 template<class T> template<int EE> inline void CPUCore<T>::INC_X(unsigned x) {
3227  byte val = INC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3228  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3229 }
3230 template<class T> II CPUCore<T>::inc_xhl() {
3231  INC_X<0>(getHL());
3232  return {1, T::CC_INC_XHL};
3233 }
3234 template<class T> template<Reg16 IXY> II CPUCore<T>::inc_xix() {
3235  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_INC_XIX_1);
3236  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3237  T::setMemPtr(addr);
3238  INC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3239  return {2, T::CC_INC_XHL + T::CC_DD + T::EE_INC_XIX};
3240 }
3241 
3242 
3243 // ADC HL,ss
3244 template<class T> template<Reg16 REG> inline II CPUCore<T>::adc_hl_SS() {
3245  unsigned reg = get16<REG>();
3246  T::setMemPtr(getHL() + 1);
3247  unsigned res = getHL() + reg + ((getF() & C_FLAG) ? 1 : 0);
3248  byte f = (res >> 16) | // C_FLAG
3249  0; // N_FLAG
3250  if (T::isR800()) {
3251  f |= getF() & (X_FLAG | Y_FLAG);
3252  }
3253  if (res & 0xFFFF) {
3254  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3255  f |= 0; // Z_FLAG
3256  f |= ((getHL() ^ res) & (reg ^ res) & 0x8000) >> 13; // V_FLAG
3257  if (T::isR800()) {
3258  f |= (res >> 8) & S_FLAG;
3259  } else {
3260  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3261  }
3262  } else {
3263  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3264  f |= Z_FLAG;
3265  f |= (getHL() & reg & 0x8000) >> 13; // V_FLAG
3266  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3267  }
3268  setF(f);
3269  setHL(res);
3270  return {1, T::CC_ADC_HL_SS};
3271 }
3272 template<class T> II CPUCore<T>::adc_hl_hl() {
3273  T::setMemPtr(getHL() + 1);
3274  unsigned res = 2 * getHL() + ((getF() & C_FLAG) ? 1 : 0);
3275  byte f = (res >> 16) | // C_FLAG
3276  0; // N_FLAG
3277  if (T::isR800()) {
3278  f |= getF() & (X_FLAG | Y_FLAG);
3279  }
3280  if (res & 0xFFFF) {
3281  f |= 0; // Z_FLAG
3282  f |= ((getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3283  if (T::isR800()) {
3284  f |= (res >> 8) & (H_FLAG | S_FLAG);
3285  } else {
3286  f |= (res >> 8) & (H_FLAG | S_FLAG | X_FLAG | Y_FLAG);
3287  }
3288  } else {
3289  f |= Z_FLAG;
3290  f |= (getHL() & 0x8000) >> 13; // V_FLAG
3291  f |= 0; // H_FLAG S_FLAG (X_FLAG Y_FLAG)
3292  }
3293  setF(f);
3294  setHL(res);
3295  return {1, T::CC_ADC_HL_SS};
3296 }
3297 
3298 // ADD HL/IX/IY,ss
3299 template<class T> template<Reg16 REG1, Reg16 REG2, int EE> II CPUCore<T>::add_SS_TT() {
3300  unsigned reg1 = get16<REG1>();
3301  unsigned reg2 = get16<REG2>();
3302  T::setMemPtr(reg1 + 1);
3303  unsigned res = reg1 + reg2;
3304  byte f = (((reg1 ^ res ^ reg2) >> 8) & H_FLAG) |
3305  (res >> 16) | // C_FLAG
3306  0; // N_FLAG
3307  if (T::isR800()) {
3308  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3309  } else {
3310  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3311  f |= (res >> 8) & (X_FLAG | Y_FLAG);
3312  }
3313  setF(f);
3314  set16<REG1>(res & 0xFFFF);
3315  return {1, T::CC_ADD_HL_SS + EE};
3316 }
3317 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::add_SS_SS() {
3318  unsigned reg = get16<REG>();
3319  T::setMemPtr(reg + 1);
3320  unsigned res = 2 * reg;
3321  byte f = (res >> 16) | // C_FLAG
3322  0; // N_FLAG
3323  if (T::isR800()) {
3324  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3325  f |= (res >> 8) & H_FLAG;
3326  } else {
3327  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3328  f |= (res >> 8) & (H_FLAG | X_FLAG | Y_FLAG);
3329  }
3330  setF(f);
3331  set16<REG>(res & 0xFFFF);
3332  return {1, T::CC_ADD_HL_SS + EE};
3333 }
3334 
3335 // SBC HL,ss
3336 template<class T> template<Reg16 REG> inline II CPUCore<T>::sbc_hl_SS() {
3337  unsigned reg = get16<REG>();
3338  T::setMemPtr(getHL() + 1);
3339  unsigned res = getHL() - reg - ((getF() & C_FLAG) ? 1 : 0);
3340  byte f = ((res & 0x10000) ? C_FLAG : 0) |
3341  N_FLAG;
3342  if (T::isR800()) {
3343  f |= getF() & (X_FLAG | Y_FLAG);
3344  }
3345  if (res & 0xFFFF) {
3346  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3347  f |= 0; // Z_FLAG
3348  f |= ((reg ^ getHL()) & (getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3349  if (T::isR800()) {
3350  f |= (res >> 8) & S_FLAG;
3351  } else {
3352  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3353  }
3354  } else {
3355  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3356  f |= Z_FLAG;
3357  f |= ((reg ^ getHL()) & getHL() & 0x8000) >> 13; // V_FLAG
3358  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3359  }
3360  setF(f);
3361  setHL(res);
3362  return {1, T::CC_ADC_HL_SS};
3363 }
3364 template<class T> II CPUCore<T>::sbc_hl_hl() {
3365  T::setMemPtr(getHL() + 1);
3366  byte f = T::isR800() ? (getF() & (X_FLAG | Y_FLAG)) : 0;
3367  if (getF() & C_FLAG) {
3368  f |= C_FLAG | H_FLAG | S_FLAG | N_FLAG;
3369  if (!T::isR800()) {
3370  f |= X_FLAG | Y_FLAG;
3371  }
3372  setHL(0xFFFF);
3373  } else {
3374  f |= Z_FLAG | N_FLAG;
3375  setHL(0);
3376  }
3377  setF(f);
3378  return {1, T::CC_ADC_HL_SS};
3379 }
3380 
3381 // DEC ss
3382 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::dec_SS() {
3383  set16<REG>(get16<REG>() - 1); return {1, T::CC_INC_SS + EE};
3384 }
3385 
3386 // INC ss
3387 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::inc_SS() {
3388  set16<REG>(get16<REG>() + 1); return {1, T::CC_INC_SS + EE};
3389 }
3390 
3391 
3392 // BIT n,r
3393 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::bit_N_R() {
3394  byte reg = get8<REG>();
3395  byte f = 0; // N_FLAG
3396  if (T::isR800()) {
3397  // this is very different from Z80 (not only XY flags)
3398  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3399  f |= H_FLAG;
3400  f |= (reg & (1 << N)) ? 0 : Z_FLAG;
3401  } else {
3402  f |= table.ZSPH[reg & (1 << N)];
3403  f |= getF() & C_FLAG;
3404  f |= reg & (X_FLAG | Y_FLAG);
3405  }
3406  setF(f);
3407  return {1, T::CC_BIT_R};
3408 }
3409 template<class T> template<unsigned N> inline II CPUCore<T>::bit_N_xhl() {
3410  byte m = RDMEM(getHL(), T::CC_BIT_XHL_1) & (1 << N);
3411  byte f = 0; // N_FLAG
3412  if (T::isR800()) {
3413  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3414  f |= H_FLAG;
3415  f |= m ? 0 : Z_FLAG;
3416  } else {
3417  f |= table.ZSPH[m];
3418  f |= getF() & C_FLAG;
3419  f |= (T::getMemPtr() >> 8) & (X_FLAG | Y_FLAG);
3420  }
3421  setF(f);
3422  return {1, T::CC_BIT_XHL};
3423 }
3424 template<class T> template<unsigned N> inline II CPUCore<T>::bit_N_xix(unsigned addr) {
3425  T::setMemPtr(addr);
3426  byte m = RDMEM(addr, T::CC_DD + T::CC_BIT_XIX_1) & (1 << N);
3427  byte f = 0; // N_FLAG
3428  if (T::isR800()) {
3429  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3430  f |= H_FLAG;
3431  f |= m ? 0 : Z_FLAG;
3432  } else {
3433  f |= table.ZSPH[m];
3434  f |= getF() & C_FLAG;
3435  f |= (addr >> 8) & (X_FLAG | Y_FLAG);
3436  }
3437  setF(f);
3438  return {3, T::CC_DD + T::CC_BIT_XIX};
3439 }
3440 
3441 // RES n,r
3442 static inline byte RES(unsigned b, byte reg) {
3443  return reg & ~(1 << b);
3444 }
3445 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::res_N_R() {
3446  set8<REG>(RES(N, get8<REG>())); return {1, T::CC_SET_R};
3447 }
3448 template<class T> template<int EE> inline byte CPUCore<T>::RES_X(unsigned bit, unsigned addr) {
3449  byte res = RES(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3450  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3451  return res;
3452 }
3453 template<class T> template<unsigned N> II CPUCore<T>::res_N_xhl() {
3454  RES_X<0>(N, getHL()); return {1, T::CC_SET_XHL};
3455 }
3456 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::res_N_xix_R(unsigned a) {
3457  T::setMemPtr(a);
3458  set8<REG>(RES_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3459  return {3, T::CC_DD + T::CC_SET_XIX};
3460 }
3461 
3462 // SET n,r
3463 static inline byte SET(unsigned b, byte reg) {
3464  return reg | (1 << b);
3465 }
3466 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::set_N_R() {
3467  set8<REG>(SET(N, get8<REG>())); return {1, T::CC_SET_R};
3468 }
3469 template<class T> template<int EE> inline byte CPUCore<T>::SET_X(unsigned bit, unsigned addr) {
3470  byte res = SET(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3471  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3472  return res;
3473 }
3474 template<class T> template<unsigned N> II CPUCore<T>::set_N_xhl() {
3475  SET_X<0>(N, getHL()); return {1, T::CC_SET_XHL};
3476 }
3477 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::set_N_xix_R(unsigned a) {
3478  T::setMemPtr(a);
3479  set8<REG>(SET_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3480  return {3, T::CC_DD + T::CC_SET_XIX};
3481 }
3482 
3483 // RL r
3484 template<class T> inline byte CPUCore<T>::RL(byte reg) {
3485  byte c = reg >> 7;
3486  reg = (reg << 1) | ((getF() & C_FLAG) ? 0x01 : 0);
3487  byte f = c ? C_FLAG : 0;
3488  if (T::isR800()) {
3489  f |= table.ZSP[reg];
3490  f |= getF() & (X_FLAG | Y_FLAG);
3491  } else {
3492  f |= table.ZSPXY[reg];
3493  }
3494  setF(f);
3495  return reg;
3496 }
3497 template<class T> template<int EE> inline byte CPUCore<T>::RL_X(unsigned x) {
3498  byte res = RL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3499  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3500  return res;
3501 }
3502 template<class T> template<Reg8 REG> II CPUCore<T>::rl_R() {
3503  set8<REG>(RL(get8<REG>())); return {1, T::CC_SET_R};
3504 }
3505 template<class T> II CPUCore<T>::rl_xhl() {
3506  RL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3507 }
3508 template<class T> template<Reg8 REG> II CPUCore<T>::rl_xix_R(unsigned a) {
3509  T::setMemPtr(a);
3510  set8<REG>(RL_X<T::CC_DD + T::EE_SET_XIX>(a));
3511  return {3, T::CC_DD + T::CC_SET_XIX};
3512 }
3513 
3514 // RLC r
3515 template<class T> inline byte CPUCore<T>::RLC(byte reg) {
3516  byte c = reg >> 7;
3517  reg = (reg << 1) | c;
3518  byte f = c ? C_FLAG : 0;
3519  if (T::isR800()) {
3520  f |= table.ZSP[reg];
3521  f |= getF() & (X_FLAG | Y_FLAG);
3522  } else {
3523  f |= table.ZSPXY[reg];
3524  }
3525  setF(f);
3526  return reg;
3527 }
3528 template<class T> template<int EE> inline byte CPUCore<T>::RLC_X(unsigned x) {
3529  byte res = RLC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3530  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3531  return res;
3532 }
3533 template<class T> template<Reg8 REG> II CPUCore<T>::rlc_R() {
3534  set8<REG>(RLC(get8<REG>())); return {1, T::CC_SET_R};
3535 }
3536 template<class T> II CPUCore<T>::rlc_xhl() {
3537  RLC_X<0>(getHL()); return {1, T::CC_SET_XHL};
3538 }
3539 template<class T> template<Reg8 REG> II CPUCore<T>::rlc_xix_R(unsigned a) {
3540  T::setMemPtr(a);
3541  set8<REG>(RLC_X<T::CC_DD + T::EE_SET_XIX>(a));
3542  return {3, T::CC_DD + T::CC_SET_XIX};
3543 }
3544 
3545 // RR r
3546 template<class T> inline byte CPUCore<T>::RR(byte reg) {
3547  byte c = reg & 1;
3548  reg = (reg >> 1) | ((getF() & C_FLAG) << 7);
3549  byte f = c ? C_FLAG : 0;
3550  if (T::isR800()) {
3551  f |= table.ZSP[reg];
3552  f |= getF() & (X_FLAG | Y_FLAG);
3553  } else {
3554  f |= table.ZSPXY[reg];
3555  }
3556  setF(f);
3557  return reg;
3558 }
3559 template<class T> template<int EE> inline byte CPUCore<T>::RR_X(unsigned x) {
3560  byte res = RR(RDMEM(x, T::CC_SET_XHL_1 + EE));
3561  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3562  return res;
3563 }
3564 template<class T> template<Reg8 REG> II CPUCore<T>::rr_R() {
3565  set8<REG>(RR(get8<REG>())); return {1, T::CC_SET_R};
3566 }
3567 template<class T> II CPUCore<T>::rr_xhl() {
3568  RR_X<0>(getHL()); return {1, T::CC_SET_XHL};
3569 }
3570 template<class T> template<Reg8 REG> II CPUCore<T>::rr_xix_R(unsigned a) {
3571  T::setMemPtr(a);
3572  set8<REG>(RR_X<T::CC_DD + T::EE_SET_XIX>(a));
3573  return {3, T::CC_DD + T::CC_SET_XIX};
3574 }
3575 
3576 // RRC r
3577 template<class T> inline byte CPUCore<T>::RRC(byte reg) {
3578  byte c = reg & 1;
3579  reg = (reg >> 1) | (c << 7);
3580  byte f = c ? C_FLAG : 0;
3581  if (T::isR800()) {
3582  f |= table.ZSP[reg];
3583  f |= getF() & (X_FLAG | Y_FLAG);
3584  } else {
3585  f |= table.ZSPXY[reg];
3586  }
3587  setF(f);
3588  return reg;
3589 }
3590 template<class T> template<int EE> inline byte CPUCore<T>::RRC_X(unsigned x) {
3591  byte res = RRC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3592  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3593  return res;
3594 }
3595 template<class T> template<Reg8 REG> II CPUCore<T>::rrc_R() {
3596  set8<REG>(RRC(get8<REG>())); return {1, T::CC_SET_R};
3597 }
3598 template<class T> II CPUCore<T>::rrc_xhl() {
3599  RRC_X<0>(getHL()); return {1, T::CC_SET_XHL};
3600 }
3601 template<class T> template<Reg8 REG> II CPUCore<T>::rrc_xix_R(unsigned a) {
3602  T::setMemPtr(a);
3603  set8<REG>(RRC_X<T::CC_DD + T::EE_SET_XIX>(a));
3604  return {3, T::CC_DD + T::CC_SET_XIX};
3605 }
3606 
3607 // SLA r
3608 template<class T> inline byte CPUCore<T>::SLA(byte reg) {
3609  byte c = reg >> 7;
3610  reg <<= 1;
3611  byte f = c ? C_FLAG : 0;
3612  if (T::isR800()) {
3613  f |= table.ZSP[reg];
3614  f |= getF() & (X_FLAG | Y_FLAG);
3615  } else {
3616  f |= table.ZSPXY[reg];
3617  }
3618  setF(f);
3619  return reg;
3620 }
3621 template<class T> template<int EE> inline byte CPUCore<T>::SLA_X(unsigned x) {
3622  byte res = SLA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3623  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3624  return res;
3625 }
3626 template<class T> template<Reg8 REG> II CPUCore<T>::sla_R() {
3627  set8<REG>(SLA(get8<REG>())); return {1, T::CC_SET_R};
3628 }
3629 template<class T> II CPUCore<T>::sla_xhl() {
3630  SLA_X<0>(getHL()); return {1, T::CC_SET_XHL};
3631 }
3632 template<class T> template<Reg8 REG> II CPUCore<T>::sla_xix_R(unsigned a) {
3633  T::setMemPtr(a);
3634  set8<REG>(SLA_X<T::CC_DD + T::EE_SET_XIX>(a));
3635  return {3, T::CC_DD + T::CC_SET_XIX};
3636 }
3637 
3638 // SLL r
3639 template<class T> inline byte CPUCore<T>::SLL(byte reg) {
3640  assert(!T::isR800()); // this instruction is Z80-only
3641  byte c = reg >> 7;
3642  reg = (reg << 1) | 1;
3643  byte f = c ? C_FLAG : 0;
3644  f |= table.ZSPXY[reg];
3645  setF(f);
3646  return reg;
3647 }
3648 template<class T> template<int EE> inline byte CPUCore<T>::SLL_X(unsigned x) {
3649  byte res = SLL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3650  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3651  return res;
3652 }
3653 template<class T> template<Reg8 REG> II CPUCore<T>::sll_R() {
3654  set8<REG>(SLL(get8<REG>())); return {1, T::CC_SET_R};
3655 }
3656 template<class T> II CPUCore<T>::sll_xhl() {
3657  SLL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3658 }
3659 template<class T> template<Reg8 REG> II CPUCore<T>::sll_xix_R(unsigned a) {
3660  T::setMemPtr(a);
3661  set8<REG>(SLL_X<T::CC_DD + T::EE_SET_XIX>(a));
3662  return {3, T::CC_DD + T::CC_SET_XIX};
3663 }
3664 template<class T> II CPUCore<T>::sll2() {
3665  assert(T::isR800()); // this instruction is R800-only
3666  byte f = (getF() & (X_FLAG | Y_FLAG)) |
3667  (getA() >> 7) | // C_FLAG
3668  0; // all other flags zero
3669  setF(f);
3670  return {3, T::CC_DD + T::CC_SET_XIX}; // TODO
3671 }
3672 
3673 // SRA r
3674 template<class T> inline byte CPUCore<T>::SRA(byte reg) {
3675  byte c = reg & 1;
3676  reg = (reg >> 1) | (reg & 0x80);
3677  byte f = c ? C_FLAG : 0;
3678  if (T::isR800()) {
3679  f |= table.ZSP[reg];
3680  f |= getF() & (X_FLAG | Y_FLAG);
3681  } else {
3682  f |= table.ZSPXY[reg];
3683  }
3684  setF(f);
3685  return reg;
3686 }
3687 template<class T> template<int EE> inline byte CPUCore<T>::SRA_X(unsigned x) {
3688  byte res = SRA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3689  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3690  return res;
3691 }
3692 template<class T> template<Reg8 REG> II CPUCore<T>::sra_R() {
3693  set8<REG>(SRA(get8<REG>())); return {1, T::CC_SET_R};
3694 }
3695 template<class T> II CPUCore<T>::sra_xhl() {
3696  SRA_X<0>(getHL()); return {1, T::CC_SET_XHL};
3697 }
3698 template<class T> template<Reg8 REG> II CPUCore<T>::sra_xix_R(unsigned a) {
3699  T::setMemPtr(a);
3700  set8<REG>(SRA_X<T::CC_DD + T::EE_SET_XIX>(a));
3701  return {3, T::CC_DD + T::CC_SET_XIX};
3702 }
3703 
3704 // SRL R
3705 template<class T> inline byte CPUCore<T>::SRL(byte reg) {
3706  byte c = reg & 1;
3707  reg >>= 1;
3708  byte f = c ? C_FLAG : 0;
3709  if (T::isR800()) {
3710  f |= table.ZSP[reg];
3711  f |= getF() & (X_FLAG | Y_FLAG);
3712  } else {
3713  f |= table.ZSPXY[reg];
3714  }
3715  setF(f);
3716  return reg;
3717 }
3718 template<class T> template<int EE> inline byte CPUCore<T>::SRL_X(unsigned x) {
3719  byte res = SRL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3720  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3721  return res;
3722 }
3723 template<class T> template<Reg8 REG> II CPUCore<T>::srl_R() {
3724  set8<REG>(SRL(get8<REG>())); return {1, T::CC_SET_R};
3725 }
3726 template<class T> II CPUCore<T>::srl_xhl() {
3727  SRL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3728 }
3729 template<class T> template<Reg8 REG> II CPUCore<T>::srl_xix_R(unsigned a) {
3730  T::setMemPtr(a);
3731  set8<REG>(SRL_X<T::CC_DD + T::EE_SET_XIX>(a));
3732  return {3, T::CC_DD + T::CC_SET_XIX};
3733 }
3734 
3735 // RLA RLCA RRA RRCA
3736 template<class T> II CPUCore<T>::rla() {
3737  byte c = getF() & C_FLAG;
3738  byte f = (getA() & 0x80) ? C_FLAG : 0;
3739  if (T::isR800()) {
3740  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3741  } else {
3742  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3743  }
3744  setA((getA() << 1) | (c ? 1 : 0));
3745  if (!T::isR800()) {
3746  f |= getA() & (X_FLAG | Y_FLAG);
3747  }
3748  setF(f);
3749  return {1, T::CC_RLA};
3750 }
3751 template<class T> II CPUCore<T>::rlca() {
3752  setA((getA() << 1) | (getA() >> 7));
3753  byte f = 0;
3754  if (T::isR800()) {
3755  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3756  f |= getA() & C_FLAG;
3757  } else {
3758  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3759  f |= getA() & (Y_FLAG | X_FLAG | C_FLAG);
3760  }
3761  setF(f);
3762  return {1, T::CC_RLA};
3763 }
3764 template<class T> II CPUCore<T>::rra() {
3765  byte c = (getF() & C_FLAG) << 7;
3766  byte f = (getA() & 0x01) ? C_FLAG : 0;
3767  if (T::isR800()) {
3768  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3769  } else {
3770  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3771  }
3772  setA((getA() >> 1) | c);
3773  if (!T::isR800()) {
3774  f |= getA() & (X_FLAG | Y_FLAG);
3775  }
3776  setF(f);
3777  return {1, T::CC_RLA};
3778 }
3779 template<class T> II CPUCore<T>::rrca() {
3780  byte f = getA() & C_FLAG;
3781  if (T::isR800()) {
3782  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3783  } else {
3784  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3785  }
3786  setA((getA() >> 1) | (getA() << 7));
3787  if (!T::isR800()) {
3788  f |= getA() & (X_FLAG | Y_FLAG);
3789  }
3790  setF(f);
3791  return {1, T::CC_RLA};
3792 }
3793 
3794 
3795 // RLD
3796 template<class T> II CPUCore<T>::rld() {
3797  byte val = RDMEM(getHL(), T::CC_RLD_1);
3798  T::setMemPtr(getHL() + 1);
3799  WRMEM(getHL(), (val << 4) | (getA() & 0x0F), T::CC_RLD_2);
3800  setA((getA() & 0xF0) | (val >> 4));
3801  byte f = 0;
3802  if (T::isR800()) {
3803  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3804  f |= table.ZSP[getA()];
3805  } else {
3806  f |= getF() & C_FLAG;
3807  f |= table.ZSPXY[getA()];
3808  }
3809  setF(f);
3810  return {1, T::CC_RLD};
3811 }
3812 
3813 // RRD
3814 template<class T> II CPUCore<T>::rrd() {
3815  byte val = RDMEM(getHL(), T::CC_RLD_1);
3816  T::setMemPtr(getHL() + 1);
3817  WRMEM(getHL(), (val >> 4) | (getA() << 4), T::CC_RLD_2);
3818  setA((getA() & 0xF0) | (val & 0x0F));
3819  byte f = 0;
3820  if (T::isR800()) {
3821  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3822  f |= table.ZSP[getA()];
3823  } else {
3824  f |= getF() & C_FLAG;
3825  f |= table.ZSPXY[getA()];
3826  }
3827  setF(f);
3828  return {1, T::CC_RLD};
3829 }
3830 
3831 
3832 // PUSH ss
3833 template<class T> template<int EE> inline void CPUCore<T>::PUSH(unsigned reg) {
3834  setSP(getSP() - 2);
3835  WR_WORD_rev<true, true>(getSP(), reg, T::CC_PUSH_1 + EE);
3836 }
3837 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::push_SS() {
3838  PUSH<EE>(get16<REG>()); return {1, T::CC_PUSH + EE};
3839 }
3840 
3841 // POP ss
3842 template<class T> template<int EE> inline unsigned CPUCore<T>::POP() {
3843  unsigned addr = getSP();
3844  setSP(addr + 2);
3845  if (T::isR800()) {
3846  // handles both POP and RET instructions (RET with condition = true)
3847  if (EE == 0) { // not reti/retn, not pop ix/iy
3848  setCurrentPopRet();
3849  // No need for setSlowInstructions()
3850  // -> this only matters directly after a CALL
3851  // instruction and in that case we're still
3852  // executing slow instructions.
3853  }
3854  }
3855  return RD_WORD(addr, T::CC_POP_1 + EE);
3856 }
3857 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::pop_SS() {
3858  set16<REG>(POP<EE>()); return {1, T::CC_POP + EE};
3859 }
3860 
3861 
3862 // CALL nn / CALL cc,nn
3863 template<class T> template<typename COND> II CPUCore<T>::call(COND cond) {
3864  unsigned addr = RD_WORD_PC<1>(T::CC_CALL_1);
3865  T::setMemPtr(addr);
3866  if (cond(getF())) {
3867  PUSH<T::EE_CALL>(getPC() + 3);
3868  setPC(addr);
3869  if (T::isR800()) {
3870  setCurrentCall();
3871  setSlowInstructions();
3872  }
3873  return {0/*3*/, T::CC_CALL_A};
3874  } else {
3875  return {3, T::CC_CALL_B};
3876  }
3877 }
3878 
3879 
3880 // RST n
3881 template<class T> template<unsigned ADDR> II CPUCore<T>::rst() {
3882  PUSH<0>(getPC() + 1);
3883  T::setMemPtr(ADDR);
3884  setPC(ADDR);
3885  if (T::isR800()) {
3886  setCurrentCall();
3887  setSlowInstructions();
3888  }
3889  return {0/*1*/, T::CC_RST};
3890 }
3891 
3892 
3893 // RET
3894 template<class T> template<int EE, typename COND> inline II CPUCore<T>::RET(COND cond) {
3895  if (cond(getF())) {
3896  unsigned addr = POP<EE>();
3897  T::setMemPtr(addr);
3898  setPC(addr);
3899  return {0/*1*/, T::CC_RET_A + EE};
3900  } else {
3901  return {1, T::CC_RET_B + EE};
3902  }
3903 }
3904 template<class T> template<typename COND> II CPUCore<T>::ret(COND cond) {
3905  return RET<T::EE_RET_C>(cond);
3906 }
3907 template<class T> II CPUCore<T>::ret() {
3908  return RET<0>(CondTrue());
3909 }
3910 template<class T> II CPUCore<T>::retn() { // also reti
3911  setIFF1(getIFF2());
3912  setSlowInstructions();
3913  return RET<T::EE_RETN>(CondTrue());
3914 }
3915 
3916 
3917 // JP ss
3918 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::jp_SS() {
3919  setPC(get16<REG>()); T::R800ForcePageBreak(); return {0/*1*/, T::CC_JP_HL + EE};
3920 }
3921 
3922 // JP nn / JP cc,nn
3923 template<class T> template<typename COND> II CPUCore<T>::jp(COND cond) {
3924  unsigned addr = RD_WORD_PC<1>(T::CC_JP_1);
3925  T::setMemPtr(addr);
3926  if (cond(getF())) {
3927  setPC(addr);
3928  T::R800ForcePageBreak();
3929  return {0/*3*/, T::CC_JP_A};
3930  } else {
3931  return {3, T::CC_JP_B};
3932  }
3933 }
3934 
3935 // JR e
3936 template<class T> template<typename COND> II CPUCore<T>::jr(COND cond) {
3937  int8_t ofst = RDMEM_OPCODE<1>(T::CC_JR_1);
3938  if (cond(getF())) {
3939  if (((getPC() + 2) & 0xFF) == 0) {
3940  // On R800, when this instruction is located in the
3941  // last two byte of a page (a page is a 256-byte
3942  // (aligned) memory block) and even if we jump back,
3943  // thus fetching the next opcode byte does not cause a
3944  // page-break, there still is one cycle overhead. It's
3945  // as-if there is a page-break.
3946  //
3947  // This could be explained by some (very limited)
3948  // pipeline behaviour in R800: it seems that the
3949  // decision to cause a page-break on the next
3950  // instruction is already made before the jump
3951  // destination address for the current instruction is
3952  // calculated (though a destination address in another
3953  // page is also a reason for a page-break).
3954  //
3955  // It's likely all instructions behave like this, but I
3956  // think we can get away with only explicitly emulating
3957  // this behaviour in the djnz and the jr (conditional
3958  // or not) instructions: all other instructions that
3959  // cause the PC to change in a non-incremental way do
3960  // already force a pagebreak for another reason, so
3961  // this effect is masked. Examples of such instructions
3962  // are: JP, RET, CALL, RST, all repeated block
3963  // instructions, accepting an IRQ, (are there more
3964  // instructions or events that change PC?)
3965  //
3966  // See doc/r800-djnz.txt for more details.
3967  T::R800ForcePageBreak();
3968  }
3969  setPC((getPC() + 2 + ofst) & 0xFFFF);
3970  T::setMemPtr(getPC());
3971  return {0/*2*/, T::CC_JR_A};
3972  } else {
3973  return {2, T::CC_JR_B};
3974  }
3975 }
3976 
3977 // DJNZ e
3978 template<class T> II CPUCore<T>::djnz() {
3979  byte b = getB() - 1;
3980  setB(b);
3981  int8_t ofst = RDMEM_OPCODE<1>(T::CC_JR_1 + T::EE_DJNZ);
3982  if (b) {
3983  if (((getPC() + 2) & 0xFF) == 0) {
3984  // See comment in jr()
3985  T::R800ForcePageBreak();
3986  }
3987  setPC((getPC() + 2 + ofst) & 0xFFFF);
3988  T::setMemPtr(getPC());
3989  return {0/*2*/, T::CC_JR_A + T::EE_DJNZ};
3990  } else {
3991  return {2, T::CC_JR_B + T::EE_DJNZ};
3992  }
3993 }
3994 
3995 // EX (SP),ss
3996 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ex_xsp_SS() {
3997  unsigned res = RD_WORD_impl<true, false>(getSP(), T::CC_EX_SP_HL_1 + EE);
3998  T::setMemPtr(res);
3999  WR_WORD_rev<false, true>(getSP(), get16<REG>(), T::CC_EX_SP_HL_2 + EE);
4000  set16<REG>(res);
4001  return {1, T::CC_EX_SP_HL + EE};
4002 }
4003 
4004 // IN r,(c)
4005 template<class T> template<Reg8 REG> II CPUCore<T>::in_R_c() {
4006  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_R_C_1);
4007  T::setMemPtr(getBC() + 1);
4008  byte res = READ_PORT(getBC(), T::CC_IN_R_C_1);
4009  byte f = 0;
4010  if (T::isR800()) {
4011  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4012  f |= table.ZSP[res];
4013  } else {
4014  f |= getF() & C_FLAG;
4015  f |= table.ZSPXY[res];
4016  }
4017  setF(f);
4018  set8<REG>(res);
4019  return {1, T::CC_IN_R_C};
4020 }
4021 
4022 // IN a,(n)
4023 template<class T> II CPUCore<T>::in_a_byte() {
4024  unsigned y = RDMEM_OPCODE<1>(T::CC_IN_A_N_1) + 256 * getA();
4025  T::setMemPtr(y + 1);
4026  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_A_N_2);
4027  setA(READ_PORT(y, T::CC_IN_A_N_2));
4028  return {2, T::CC_IN_A_N};
4029 }
4030 
4031 // OUT (c),r
4032 template<class T> template<Reg8 REG> II CPUCore<T>::out_c_R() {
4033  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4034  T::setMemPtr(getBC() + 1);
4035  WRITE_PORT(getBC(), get8<REG>(), T::CC_OUT_C_R_1);
4036  return {1, T::CC_OUT_C_R};
4037 }
4038 template<class T> II CPUCore<T>::out_c_0() {
4039  // TODO not on R800
4040  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4041  T::setMemPtr(getBC() + 1);
4042  byte out_c_x = isTurboR ? 255 : 0;
4043  WRITE_PORT(getBC(), out_c_x, T::CC_OUT_C_R_1);
4044  return {1, T::CC_OUT_C_R};
4045 }
4046 
4047 // OUT (n),a
4048 template<class T> II CPUCore<T>::out_byte_a() {
4049  byte port = RDMEM_OPCODE<1>(T::CC_OUT_N_A_1);
4050  unsigned y = (getA() << 8) | port;
4051  T::setMemPtr((getA() << 8) | ((port + 1) & 255));
4052  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_N_A_2);
4053  WRITE_PORT(y, getA(), T::CC_OUT_N_A_2);
4054  return {2, T::CC_OUT_N_A};
4055 }
4056 
4057 
4058 // block CP
4059 template<class T> inline II CPUCore<T>::BLOCK_CP(int increase, bool repeat) {
4060  T::setMemPtr(T::getMemPtr() + increase);
4061  byte val = RDMEM(getHL(), T::CC_CPI_1);
4062  byte res = getA() - val;
4063  setHL(getHL() + increase);
4064  setBC(getBC() - 1);
4065  byte f = ((getA() ^ val ^ res) & H_FLAG) |
4066  table.ZS[res] |
4067  N_FLAG |
4068  (getBC() ? V_FLAG : 0);
4069  if (T::isR800()) {
4070  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4071  } else {
4072  f |= getF() & C_FLAG;
4073  unsigned k = res - ((f & H_FLAG) >> 4);
4074  f |= (k << 4) & Y_FLAG; // bit 1 -> flag 5
4075  f |= k & X_FLAG; // bit 3 -> flag 3
4076  }
4077  setF(f);
4078  if (repeat && getBC() && res) {
4079  //setPC(getPC() - 2);
4080  T::setMemPtr(getPC() + 1);
4081  return {-1/*1*/, T::CC_CPIR};
4082  } else {
4083  return {1, T::CC_CPI};
4084  }
4085 }
4086 template<class T> II CPUCore<T>::cpd() { return BLOCK_CP(-1, false); }
4087 template<class T> II CPUCore<T>::cpi() { return BLOCK_CP( 1, false); }
4088 template<class T> II CPUCore<T>::cpdr() { return BLOCK_CP(-1, true ); }
4089 template<class T> II CPUCore<T>::cpir() { return BLOCK_CP( 1, true ); }
4090 
4091 
4092 // block LD
4093 template<class T> inline II CPUCore<T>::BLOCK_LD(int increase, bool repeat) {
4094  byte val = RDMEM(getHL(), T::CC_LDI_1);
4095  WRMEM(getDE(), val, T::CC_LDI_2);
4096  setHL(getHL() + increase);
4097  setDE(getDE() + increase);
4098  setBC(getBC() - 1);
4099  byte f = getBC() ? V_FLAG : 0;
4100  if (T::isR800()) {
4101  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG | X_FLAG | Y_FLAG);
4102  } else {
4103  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG);
4104  f |= ((getA() + val) << 4) & Y_FLAG; // bit 1 -> flag 5
4105  f |= (getA() + val) & X_FLAG; // bit 3 -> flag 3
4106  }
4107  setF(f);
4108  if (repeat && getBC()) {
4109  //setPC(getPC() - 2);
4110  T::setMemPtr(getPC() + 1);
4111  return {-1/*1*/, T::CC_LDIR};
4112  } else {
4113  return {1, T::CC_LDI};
4114  }
4115 }
4116 template<class T> II CPUCore<T>::ldd() { return BLOCK_LD(-1, false); }
4117 template<class T> II CPUCore<T>::ldi() { return BLOCK_LD( 1, false); }
4118 template<class T> II CPUCore<T>::lddr() { return BLOCK_LD(-1, true ); }
4119 template<class T> II CPUCore<T>::ldir() { return BLOCK_LD( 1, true ); }
4120 
4121 
4122 // block IN
4123 template<class T> inline II CPUCore<T>::BLOCK_IN(int increase, bool repeat) {
4124  // TODO R800 flags
4125  if (T::isR800()) T::waitForEvenCycle(T::CC_INI_1);
4126  T::setMemPtr(getBC() + increase);
4127  setBC(getBC() - 0x100); // decr before use
4128  byte val = READ_PORT(getBC(), T::CC_INI_1);
4129  WRMEM(getHL(), val, T::CC_INI_2);
4130  setHL(getHL() + increase);
4131  unsigned k = val + ((getC() + increase) & 0xFF);
4132  byte b = getB();
4133  setF(((val & S_FLAG) >> 6) | // N_FLAG
4134  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4135  table.ZSXY[b] |
4136  (table.ZSPXY[(k & 0x07) ^ b] & P_FLAG));
4137  if (repeat && b) {
4138  //setPC(getPC() - 2);
4139  return {-1/*1*/, T::CC_INIR};
4140  } else {
4141  return {1, T::CC_INI};
4142  }
4143 }
4144 template<class T> II CPUCore<T>::ind() { return BLOCK_IN(-1, false); }
4145 template<class T> II CPUCore<T>::ini() { return BLOCK_IN( 1, false); }
4146 template<class T> II CPUCore<T>::indr() { return BLOCK_IN(-1, true ); }
4147 template<class T> II CPUCore<T>::inir() { return BLOCK_IN( 1, true ); }
4148 
4149 
4150 // block OUT
4151 template<class T> inline II CPUCore<T>::BLOCK_OUT(int increase, bool repeat) {
4152  // TODO R800 flags
4153  byte val = RDMEM(getHL(), T::CC_OUTI_1);
4154  setHL(getHL() + increase);
4155  if (T::isR800()) T::waitForEvenCycle(T::CC_OUTI_2);
4156  WRITE_PORT(getBC(), val, T::CC_OUTI_2);
4157  setBC(getBC() - 0x100); // decr after use
4158  T::setMemPtr(getBC() + increase);
4159  unsigned k = val + getL();
4160  byte b = getB();
4161  setF(((val & S_FLAG) >> 6) | // N_FLAG
4162  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4163  table.ZSXY[b] |
4164  (table.ZSPXY[(k & 0x07) ^ b] & P_FLAG));
4165  if (repeat && b) {
4166  //setPC(getPC() - 2);
4167  return {-1/*1*/, T::CC_OTIR};
4168  } else {
4169  return {1, T::CC_OUTI};
4170  }
4171 }
4172 template<class T> II CPUCore<T>::outd() { return BLOCK_OUT(-1, false); }
4173 template<class T> II CPUCore<T>::outi() { return BLOCK_OUT( 1, false); }
4174 template<class T> II CPUCore<T>::otdr() { return BLOCK_OUT(-1, true ); }
4175 template<class T> II CPUCore<T>::otir() { return BLOCK_OUT( 1, true ); }
4176 
4177 
4178 // various
4179 template<class T> II CPUCore<T>::nop() { return {1, T::CC_NOP}; }
4180 template<class T> II CPUCore<T>::ccf() {
4181  byte f = 0;
4182  if (T::isR800()) {
4183  // H flag is different from Z80 (and as always XY flags as well)
4184  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | X_FLAG | Y_FLAG | H_FLAG);
4185  } else {
4186  f |= (getF() & C_FLAG) << 4; // H_FLAG
4187  // only set X(Y) flag (don't reset if already set)
4188  if (isTurboR) {
4189  // Y flag is not changed on a turboR-Z80
4190  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | Y_FLAG);
4191  f |= (getF() | getA()) & X_FLAG;
4192  } else {
4193  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4194  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4195  }
4196  }
4197  f ^= C_FLAG;
4198  setF(f);
4199  return {1, T::CC_CCF};
4200 }
4201 template<class T> II CPUCore<T>::cpl() {
4202  setA(getA() ^ 0xFF);
4203  byte f = H_FLAG | N_FLAG;
4204  if (T::isR800()) {
4205  f |= getF();
4206  } else {
4207  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4208  f |= getA() & (X_FLAG | Y_FLAG);
4209  }
4210  setF(f);
4211  return {1, T::CC_CPL};
4212 }
4213 template<class T> II CPUCore<T>::daa() {
4214  byte a = getA();
4215  byte f = getF();
4216  byte adjust = 0;
4217  if ((f & H_FLAG) || ((getA() & 0xf) > 9)) adjust += 6;
4218  if ((f & C_FLAG) || (getA() > 0x99)) adjust += 0x60;
4219  if (f & N_FLAG) a -= adjust; else a += adjust;
4220  if (T::isR800()) {
4221  f &= C_FLAG | N_FLAG | X_FLAG | Y_FLAG;
4222  f |= table.ZSP[a];
4223  } else {
4224  f &= C_FLAG | N_FLAG;
4225  f |= table.ZSPXY[a];
4226  }
4227  f |= (getA() > 0x99) | ((getA() ^ a) & H_FLAG);
4228  setA(a);
4229  setF(f);
4230  return {1, T::CC_DAA};
4231 }
4232 template<class T> II CPUCore<T>::neg() {
4233  // alternative: LUT word negTable[256]
4234  unsigned a = getA();
4235  unsigned res = -signed(a);
4236  byte f = ((res & 0x100) ? C_FLAG : 0) |
4237  N_FLAG |
4238  ((res ^ a) & H_FLAG) |
4239  ((a & res & 0x80) >> 5); // V_FLAG
4240  if (T::isR800()) {
4241  f |= table.ZS[res & 0xFF];
4242  f |= getF() & (X_FLAG | Y_FLAG);
4243  } else {
4244  f |= table.ZSXY[res & 0xFF];
4245  }
4246  setF(f);
4247  setA(res);
4248  return {1, T::CC_NEG};
4249 }
4250 template<class T> II CPUCore<T>::scf() {
4251  byte f = C_FLAG;
4252  if (T::isR800()) {
4253  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
4254  } else {
4255  // only set X(Y) flag (don't reset if already set)
4256  if (isTurboR) {
4257  // Y flag is not changed on a turboR-Z80
4258  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | Y_FLAG);
4259  f |= (getF() | getA()) & X_FLAG;
4260  } else {
4261  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
4262  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4263  }
4264  }
4265  setF(f);
4266  return {1, T::CC_SCF};
4267 }
4268 
4269 template<class T> II CPUCore<T>::ex_af_af() {
4270  unsigned t = getAF2(); setAF2(getAF()); setAF(t);
4271  return {1, T::CC_EX};
4272 }
4273 template<class T> II CPUCore<T>::ex_de_hl() {
4274  unsigned t = getDE(); setDE(getHL()); setHL(t);
4275  return {1, T::CC_EX};
4276 }
4277 template<class T> II CPUCore<T>::exx() {
4278  unsigned t1 = getBC2(); setBC2(getBC()); setBC(t1);
4279  unsigned t2 = getDE2(); setDE2(getDE()); setDE(t2);
4280  unsigned t3 = getHL2(); setHL2(getHL()); setHL(t3);
4281  return {1, T::CC_EX};
4282 }
4283 
4284 template<class T> II CPUCore<T>::di() {
4285  setIFF1(false);
4286  setIFF2(false);
4287  return {1, T::CC_DI};
4288 }
4289 template<class T> II CPUCore<T>::ei() {
4290  setIFF1(true);
4291  setIFF2(true);
4292  setCurrentEI(); // no ints directly after this instr
4293  setSlowInstructions();
4294  return {1, T::CC_EI};
4295 }
4296 template<class T> II CPUCore<T>::halt() {
4297  setHALT(true);
4298  setSlowInstructions();
4299 
4300  if (!(getIFF1() || getIFF2())) {
4301  diHaltCallback.execute();
4302  }
4303  return {1, T::CC_HALT};
4304 }
4305 template<class T> template<unsigned N> II CPUCore<T>::im_N() {
4306  setIM(N); return {1, T::CC_IM};
4307 }
4308 
4309 // LD A,I/R
4310 template<class T> template<Reg8 REG> II CPUCore<T>::ld_a_IR() {
4311  setA(get8<REG>());
4312  byte f = getIFF2() ? V_FLAG : 0;
4313  if (T::isR800()) {
4314  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4315  f |= table.ZS[getA()];
4316  } else {
4317  f |= getF() & C_FLAG;
4318  f |= table.ZSXY[getA()];
4319  // see comment in the IRQ acceptance part of executeSlow().
4320  setCurrentLDAI(); // only Z80 (not R800) has this quirk
4321  setSlowInstructions();
4322  }
4323  setF(f);
4324  return {1, T::CC_LD_A_I};
4325 }
4326 
4327 // LD I/R,A
4328 template<class T> II CPUCore<T>::ld_r_a() {
4329  // This code sequence:
4330  // XOR A / LD R,A / LD A,R
4331  // gives A=2 for Z80, but A=1 for R800. The difference can possibly be
4332  // explained by a difference in the relative time between writing the
4333  // new value to the R register and increasing the R register per M1
4334  // cycle. Here we implemented the R800 behaviour by storing 'A-1' into
4335  // R, that's good enough for now.
4336  byte val = getA();
4337  if (T::isR800()) val -= 1;
4338  setR(val);
4339  return {1, T::CC_LD_A_I};
4340 }
4341 template<class T> II CPUCore<T>::ld_i_a() {
4342  setI(getA());
4343  return {1, T::CC_LD_A_I};
4344 }
4345 
4346 // MULUB A,r
4347 template<class T> template<Reg8 REG> II CPUCore<T>::mulub_a_R() {
4348  assert(T::isR800()); // this instruction is R800-only
4349  // Verified on real R800:
4350  // YHXN flags are unchanged
4351  // SV flags are reset
4352  // Z flag is set when result is zero
4353  // C flag is set when result doesn't fit in 8-bit
4354  setHL(unsigned(getA()) * get8<REG>());
4355  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4356  0 | // S_FLAG V_FLAG
4357  (getHL() ? 0 : Z_FLAG) |
4358  ((getHL() & 0xFF00) ? C_FLAG : 0));
4359  return {1, T::CC_MULUB};
4360 }
4361 
4362 // MULUW HL,ss
4363 template<class T> template<Reg16 REG> II CPUCore<T>::muluw_hl_SS() {
4364  assert(T::isR800()); // this instruction is R800-only
4365  // Verified on real R800:
4366  // YHXN flags are unchanged
4367  // SV flags are reset
4368  // Z flag is set when result is zero
4369  // C flag is set when result doesn't fit in 16-bit
4370  unsigned res = unsigned(getHL()) * get16<REG>();
4371  setDE(res >> 16);
4372  setHL(res & 0xffff);
4373  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4374  0 | // S_FLAG V_FLAG
4375  (res ? 0 : Z_FLAG) |
4376  ((res & 0xFFFF0000) ? C_FLAG : 0));
4377  return {1, T::CC_MULUW};
4378 }
4379 
4380 
4381 // versions:
4382 // 1 -> initial version
4383 // 2 -> moved memptr from here to Z80TYPE (and not to R800TYPE)
4384 // 3 -> timing of the emulation changed (no changes in serialization)
4385 // 4 -> timing of the emulation changed again (see doc/internal/r800-call.txt)
4386 // 5 -> added serialization of nmiEdge
4387 template<class T> template<typename Archive>
4388 void CPUCore<T>::serialize(Archive& ar, unsigned version)
4389 {
4390  T::serialize(ar, version);
4391  ar.serialize("regs", static_cast<CPURegs&>(*this));
4392  if (ar.versionBelow(version, 2)) {
4393  unsigned mptr = 0; // dummy value (avoid warning)
4394  ar.serialize("memptr", mptr);
4395  T::setMemPtr(mptr);
4396  }
4397 
4398  if (ar.versionBelow(version, 5)) {
4399  // NMI is unused on MSX and even on systems where it is used nmiEdge
4400  // is true only between the moment the NMI request comes in and the
4401  // moment the Z80 jumps to the NMI handler, so defaulting to false
4402  // is pretty safe.
4403  nmiEdge = false;
4404  } else {
4405  // CPU is deserialized after devices, so nmiEdge is restored to the
4406  // saved version even if IRQHelpers set it on deserialization.
4407  ar.serialize("nmiEdge", nmiEdge);
4408  }
4409 
4410  if (ar.isLoader()) {
4411  invalidateMemCache(0x0000, 0x10000);
4412  }
4413 
4414  // Don't serialize:
4415  // - IRQStatus, NMIStatus:
4416  // the IRQHelper deserialization makes sure these get the right value
4417  // - slowInstructions, exitLoop:
4418  // serialization happens outside the CPU emulation loop
4419 
4420  if (T::isR800() && ar.versionBelow(version, 4)) {
4421  motherboard.getMSXCliComm().printWarning(
4422  "Loading an old savestate: the timing of the R800 "
4423  "emulation has changed. This may cause synchronization "
4424  "problems in replay.");
4425  }
4426 }
4427 
4428 // Force template instantiation
4429 template class CPUCore<Z80TYPE>;
4430 template class CPUCore<R800TYPE>;
4431 
4434 
4435 } // namespace openmsx
#define CASE(X)
static const int CLOCK_FREQ
Definition: R800.hh:33
#define NEVER_INLINE
Definition: inline.hh:17
#define ALWAYS_INLINE
Definition: inline.hh:16
#define unlikely(x)
Definition: likely.hh:15
uint8_t byte
8 bit unsigned integer
Definition: openmsx.hh:26
unsigned dasm(const MSXCPUInterface &interf, word pc, byte buf[4], std::string &dest, EmuTime::param time)
Disassemble.
Definition: Dasm.cc:18
CPUCore(MSXMotherBoard &motherboard, const std::string &name, const BooleanSetting &traceSetting, TclCallback &diHaltCallback, EmuTime::param time)
Definition: CPUCore.cc:300
bool operator()(byte f) const
Definition: CPUCore.cc:290
#define CONSTEXPR
Definition: cstd.hh:17
byte ZS[256]
Definition: CPUCore.cc:238
bool operator()(byte f) const
Definition: CPUCore.cc:291
#define NEXT
#define NEXT_STOP
int cycles
Definition: CPUCore.hh:40
This class implements a subset of the proposal for std::array_ref (proposed for the next c++ standard...
Definition: array_ref.hh:19
byte ZSPH[256]
Definition: CPUCore.cc:242
bool operator()(byte) const
Definition: CPUCore.cc:298
Thanks to enen for testing this on a real cartridge:
Definition: Autofire.cc:5
size_t size() const
bool operator()(byte f) const
Definition: CPUCore.cc:297
static const int CLOCK_FREQ
Definition: Z80.hh:17
size_type size() const
Definition: array_ref.hh:61
uint16_t word
16 bit unsigned integer
Definition: openmsx.hh:29
void addListElement(string_ref element)
Definition: TclObject.cc:69
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
Definition: serialize.hh:840
bool operator()(byte f) const
Definition: CPUCore.cc:294
bool operator()(byte f) const
Definition: CPUCore.cc:296
bool operator()(byte f) const
Definition: CPUCore.cc:292
byte ZSP[256]
Definition: CPUCore.cc:240
#define NEXT_EI
#define likely(x)
Definition: likely.hh:14
bool operator()(byte f) const
Definition: CPUCore.cc:295
byte ZSXY[256]
Definition: CPUCore.cc:239
bool operator()(byte f) const
Definition: CPUCore.cc:293
byte ZSPXY[256]
Definition: CPUCore.cc:241
void serialize(Archive &ar, T &t, unsigned version)
bool isMainThread()
Returns true when called from the main thread.
Definition: Thread.cc:16
#define UNREACHABLE
Definition: unreachable.hh:35