openMSX
CPUCore.cc
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1 // MEMORY EMULATION
2 // ----------------
3 //
4 // Memory access emulation is a very important part of the CPU emulation.
5 // Because they happen so frequently they really need to be executed as fast as
6 // possible otherwise they will completely bring down the speed of the CPU
7 // emulation.
8 //
9 // A very fast way to emulate memory accesses is by simply reading/writing to a
10 // 64kb array (for a 16-bit address space). Unfortunately this doesn't allow
11 // for memory mapped IO (MMIO). These are memory regions where read/writes
12 // trigger side effects, so where we need to execute device-specific code on
13 // read or writes. An alternative that does work with MMIO is for every access
14 // execute a virtual method call, (this is the approach taken by most current
15 // MSX emulators). Unfortunately this is also a lot slower.
16 //
17 // It is possible to combine the speed of array accesses with the flexibility
18 // of virtual methods. In openMSX it's implemened as follows: the 64kb address
19 // space is divided in 256 regions of 256 bytes (called cacheLines in the code
20 // below). For each such region we store a pointer, if this pointer is nullptr
21 // then we have to use the slow way (=virtual method call). If it is not nullptr,
22 // the pointer points to a block of memory that can be directly accessed. In
23 // some contexts accesses via the pointer are known as backdoor accesses while
24 // the accesses directly to the device are known as frontdoor accesses.
25 //
26 // We keep different pointers for read and write accesses. This allows to also
27 // implement ROMs efficiently: read is handled as regular RAM, but writes end
28 // up in some dummy memory region. This region is called 'unmappedWrite' in the
29 // code. There is also a special region 'unmappedRead', this region is filled
30 // with 0xFF and can be used to model (parts of) a device that don't react to
31 // reads (so reads return 0xFF).
32 //
33 // Because of bankswitching (the MSX slot select mechanism, but also e.g.
34 // MegaROM backswitching) the memory map as seen by the Z80 is not static. This
35 // means that the cacheLine pointers also need to change during runtime. To
36 // solve this we made the bankswitch code also responsible for invalidating the
37 // cacheLines of the switched region. These pointers are filled-in again in a
38 // lazy way: the first read or write to a cache line will first get this
39 // pointer (see getReadCacheLine() and getWriteCacheLine() in the code below),
40 // from then on this pointer is used for all further accesses to this region,
41 // until the cache is invalidated again.
42 //
43 //
44 // INSTRUCTION EMULATION
45 // ---------------------
46 //
47 // UPDATE: the 'threaded interpreter model' is not enabled by default
48 // main reason is the huge memory requirement while compiling
49 // and that it doesn't work on non-gcc compilers
50 //
51 // The current implementation is based on a 'threaded interpreter model'. In
52 // the text below I'll call the older implementation the 'traditional
53 // interpreter model'. From a very high level these two models look like this:
54 //
55 // Traditional model:
56 // while (!needExit()) {
57 // byte opcode = fetch(PC++);
58 // switch (opcode) {
59 // case 0x00: nop(); break;
60 // case 0x01: ld_bc_nn(); break;
61 // ...
62 // }
63 // }
64 //
65 // Threaded model:
66 // byte opcode = fetch(PC++); //
67 // goto *(table[opcode]); // fetch-and-dispatch
68 // // note: the goto * syntax is a gcc extension called computed-gotos
69 //
70 // op00: nop(); if (!needExit()) [fetch-and-dispatch];
71 // op01: ld_bc_nn(); if (!needExit()) [fetch-and-dispatch];
72 // ...
73 //
74 // In the first model there is a central place in the code that fetches (the
75 // first byte of) the instruction and based on this byte jumps to the
76 // appropriate routine. In the second model, this fetch-and-dispatch logic is
77 // duplicated at the end of each instruction.
78 //
79 // Typically the 'dispatch' part in above paragraph is implemented (either by
80 // the compiler or manually using computed goto's) via a jump table. Thus on
81 // assembler level via an indirect jump. For the host CPU it's hard to predict
82 // the destination address of such an indirect jump, certainly if there's only
83 // one such jump for all dispatching (the traditional model). If each
84 // instruction has its own indirect jump instruction (the threaded model), it
85 // becomes a bit easier, because often one particular z80 instructions is
86 // followed by a specific other z80 instruction (or one from a small subset).
87 // For example a z80 'cp' instruction is most likely followed by a 'conditional
88 // jump' z80 instruction. Modern CPUs are quite sensitive to
89 // branch-(mis)predictions, so the above optimization helps quite a lot. I
90 // measured a speedup of more than 10%!
91 //
92 // There is another advantage to the threaded model. Because also the
93 // needExit() test is duplicated for each instruction, it becomes possible to
94 // tweak it for individual instructions. But first let me explain this
95 // exit-test in more detail.
96 //
97 // These are the main reasons why the emulator should stop emulating CPU
98 // instructions:
99 // 1) When other devices than the CPU must be emulated (e.g. video frame
100 // rendering). In openMSX this is handled by the Scheduler class and
101 // actually we don't exit the CPU loop (anymore) for this. Instead we
102 // simply execute the device code as a subroutine. Each time right before
103 // we access an IO port or do a frontdoor memory access, there is a check
104 // whether we should emulate device code (search for schedule() in the code
105 // below).
106 // 2) To keep the inner CPU loop as fast as possible we don't check for IRQ,
107 // NMI or HALT status in this loop. Instead this condition is checked only
108 // once at the beginning outside of the loop (if there wasn't a pending IRQ
109 // on the first instruction there also won't be one on the second
110 // instruction, if all we did was emulating cpu instructions). Now when one
111 // of these conditions changes, we must exit the inner loop and re-evaluate
112 // them. For example after an EI instruction we must check the IRQ status
113 // again.
114 // 3) Various reasons like:
115 // * Z80/R800 switch
116 // * executing a Tcl command (could be a cpu-register debug read)
117 // * exit the emulator
118 // 4) 'once-in-a-while': To avoid threading problems and race conditions,
119 // several threads in openMSX only 'schedule' work that will later be
120 // executed by the main emulation thread. The main thread checks for such
121 // task outside of the cpu emulation loop. So once-in-a-while we need to
122 // exit the loop. The exact timing doesn't matter here because anyway the
123 // relative timing between threads is undefined.
124 // So for 1) we don't need to do anything (we don't actually exit). For 2) and
125 // 3) we need to exit the loop as soon as possible (right after the current
126 // instruction is finished). For 4) it's OK to exit 'eventually' (a few hundred
127 // z80 instructions late is still OK).
128 //
129 // Condition 2) is implemented with the 'slowInstructions' mechanism. Condition
130 // 3) via exitCPULoopSync() (may only get called by the main emulation thread)
131 // and condition 4) is implemented via exitCPULoopAsync() (can be called from
132 // any thread).
133 //
134 // Now back to the exit-test optimization: in the threaded model each
135 // instruction ends with:
136 //
137 // if (needExit()) return
138 // byte opcode = fetch(PC++);
139 // goto *(table[opcode]);
140 //
141 // And if we look in more detail at fetch():
142 //
143 // if (canDoBackdoor(addr)) {
144 // doBackdoorAccess(addr);
145 // } else {
146 // doFrontdoorAccess(addr);
147 // }
148 //
149 // So there are in fact two checks per instruction. This can be reduced to only
150 // one check with the following trick:
151 //
152 // !!!WRONG!!!
153 // In the past we optimized this to only check canDoBackdoor() (and make sure
154 // canDoBackdoor() returned false when needExit() would return true). This
155 // worked rather well, except for one case: when we exit the CPU loop we also
156 // check for pending Syncronization points. It is possible such a SyncPoint
157 // raises the IRQ line. So it is important to check for exit after every
158 // instruction, otherwise we would enter the IRQ routine a couple of
159 // instructions too late.
160 
161 #include "CPUCore.hh"
162 #include "MSXCPUInterface.hh"
163 #include "Scheduler.hh"
164 #include "MSXMotherBoard.hh"
165 #include "CliComm.hh"
166 #include "TclCallback.hh"
167 #include "Dasm.hh"
168 #include "Z80.hh"
169 #include "R800.hh"
170 #include "Thread.hh"
171 #include "endian.hh"
172 #include "likely.hh"
173 #include "inline.hh"
174 #include "unreachable.hh"
175 #include <iostream>
176 #include <type_traits>
177 #include <cassert>
178 #include <cstring>
179 
180 
181 //
182 // #define USE_COMPUTED_GOTO
183 //
184 // Computed goto's are not enabled by default:
185 // - Computed goto's are a gcc extension, it's not part of the official c++
186 // standard. So this will only work if you use gcc as your compiler (it
187 // won't work with visual c++ for example)
188 // - This is only beneficial on CPUs with branch prediction for indirect jumps
189 // and a reasonable amout of cache. For example it is very benefical for a
190 // intel core2 cpu (10% faster), but not for a ARM920 (a few percent slower)
191 // - Compiling src/cpu/CPUCore.cc with computed goto's enabled is very demanding
192 // on the compiler. On older gcc versions it requires up to 1.5GB of memory.
193 // But even on more recent gcc versions it still requires around 700MB.
194 //
195 // Probably the easiest way to enable this, is to pass the -DUSE_COMPUTED_GOTO
196 // flag to the compiler. This is for example done in the super-opt flavour.
197 // See build/flavour-super-opt.mk
198 
199 
200 using std::string;
201 
202 namespace openmsx {
203 
204 enum Reg8 : int { A, F, B, C, D, E, H, L, IXH, IXL, IYH, IYL, REG_I, REG_R, DUMMY };
205 enum Reg16 : int { AF, BC, DE, HL, IX, IY, SP };
206 
207 // flag positions
208 constexpr byte S_FLAG = 0x80;
209 constexpr byte Z_FLAG = 0x40;
210 constexpr byte Y_FLAG = 0x20;
211 constexpr byte H_FLAG = 0x10;
212 constexpr byte X_FLAG = 0x08;
213 constexpr byte V_FLAG = 0x04;
214 constexpr byte P_FLAG = V_FLAG;
215 constexpr byte N_FLAG = 0x02;
216 constexpr byte C_FLAG = 0x01;
217 
218 // flag-register lookup tables
219 struct Table {
220  byte ZS [256];
221  byte ZSXY [256];
222  byte ZSP [256];
223  byte ZSPXY[256];
224  byte ZSPH [256];
225 };
226 
227 constexpr byte ZS0 = Z_FLAG;
228 constexpr byte ZSXY0 = Z_FLAG;
229 constexpr byte ZSP0 = Z_FLAG | V_FLAG;
230 constexpr byte ZSPXY0 = Z_FLAG | V_FLAG;
231 constexpr byte ZS255 = S_FLAG;
232 constexpr byte ZSXY255 = S_FLAG | X_FLAG | Y_FLAG;
233 
234 static constexpr Table initTables()
235 {
236  Table table = {};
237 
238  for (int i = 0; i < 256; ++i) {
239  byte zFlag = (i == 0) ? Z_FLAG : 0;
240  byte sFlag = i & S_FLAG;
241  byte xFlag = i & X_FLAG;
242  byte yFlag = i & Y_FLAG;
243  byte vFlag = V_FLAG;
244  for (int v = 128; v != 0; v >>= 1) {
245  if (i & v) vFlag ^= V_FLAG;
246  }
247  table.ZS [i] = zFlag | sFlag;
248  table.ZSXY [i] = zFlag | sFlag | xFlag | yFlag;
249  table.ZSP [i] = zFlag | sFlag | vFlag;
250  table.ZSPXY[i] = zFlag | sFlag | xFlag | yFlag | vFlag;
251  table.ZSPH [i] = zFlag | sFlag | vFlag | H_FLAG;
252  }
253  assert(table.ZS [ 0] == ZS0);
254  assert(table.ZSXY [ 0] == ZSXY0);
255  assert(table.ZSP [ 0] == ZSP0);
256  assert(table.ZSPXY[ 0] == ZSPXY0);
257  assert(table.ZS [255] == ZS255);
258  assert(table.ZSXY [255] == ZSXY255);
259 
260  return table;
261 }
262 
263 constexpr Table table = initTables();
264 
265 // Global variable, because it should be shared between Z80 and R800.
266 // It must not be shared between the CPUs of different MSX machines, but
267 // the (logical) lifetime of this variable cannot overlap between execution
268 // of two MSX machines.
269 static word start_pc;
270 
271 // conditions
272 struct CondC { bool operator()(byte f) const { return (f & C_FLAG) != 0; } };
273 struct CondNC { bool operator()(byte f) const { return !(f & C_FLAG); } };
274 struct CondZ { bool operator()(byte f) const { return (f & Z_FLAG) != 0; } };
275 struct CondNZ { bool operator()(byte f) const { return !(f & Z_FLAG); } };
276 struct CondM { bool operator()(byte f) const { return (f & S_FLAG) != 0; } };
277 struct CondP { bool operator()(byte f) const { return !(f & S_FLAG); } };
278 struct CondPE { bool operator()(byte f) const { return (f & V_FLAG) != 0; } };
279 struct CondPO { bool operator()(byte f) const { return !(f & V_FLAG); } };
280 struct CondTrue { bool operator()(byte /*f*/) const { return true; } };
281 
282 template<class T> CPUCore<T>::CPUCore(
283  MSXMotherBoard& motherboard_, const string& name,
284  const BooleanSetting& traceSetting_,
285  TclCallback& diHaltCallback_, EmuTime::param time)
286  : CPURegs(T::isR800())
287  , T(time, motherboard_.getScheduler())
288  , motherboard(motherboard_)
289  , scheduler(motherboard.getScheduler())
290  , interface(nullptr)
291  , traceSetting(traceSetting_)
292  , diHaltCallback(diHaltCallback_)
293  , IRQStatus(motherboard.getDebugger(), name + ".pendingIRQ",
294  "Non-zero if there are pending IRQs (thus CPU would enter "
295  "interrupt routine in EI mode).",
296  0)
297  , IRQAccept(motherboard.getDebugger(), name + ".acceptIRQ",
298  "This probe is only useful to set a breakpoint on (the value "
299  "return by read is meaningless). The breakpoint gets triggered "
300  "right after the CPU accepted an IRQ.")
301  , freqLocked(
302  motherboard.getCommandController(), name + "_freq_locked",
303  strCat("real (locked) or custom (unlocked) ", name, " frequency"),
304  true)
305  , freqValue(
306  motherboard.getCommandController(), name + "_freq",
307  strCat("custom ", name, " frequency (only valid when unlocked)"),
308  T::CLOCK_FREQ, 1000000, 1000000000)
309  , freq(T::CLOCK_FREQ)
310  , NMIStatus(0)
311  , nmiEdge(false)
312  , exitLoop(false)
313  , tracingEnabled(traceSetting.getBoolean())
314  , isTurboR(motherboard.isTurboR())
315 {
316  static_assert(!std::is_polymorphic_v<CPUCore<T>>,
317  "keep CPUCore non-virtual to keep PC at offset 0");
318  doSetFreq();
319  doReset(time);
320 }
321 
322 template<class T> void CPUCore<T>::warp(EmuTime::param time)
323 {
324  assert(T::getTimeFast() <= time);
325  T::setTime(time);
326 }
327 
328 template<class T> EmuTime::param CPUCore<T>::getCurrentTime() const
329 {
330  return T::getTime();
331 }
332 
333 template<class T> void CPUCore<T>::doReset(EmuTime::param time)
334 {
335  // AF and SP are 0xFFFF
336  // PC, R, IFF1, IFF2, HALT and IM are 0x0
337  // all others are random
338  setAF(0xFFFF);
339  setBC(0xFFFF);
340  setDE(0xFFFF);
341  setHL(0xFFFF);
342  setIX(0xFFFF);
343  setIY(0xFFFF);
344  setPC(0x0000);
345  setSP(0xFFFF);
346  setAF2(0xFFFF);
347  setBC2(0xFFFF);
348  setDE2(0xFFFF);
349  setHL2(0xFFFF);
350  setIFF1(false);
351  setIFF2(false);
352  setHALT(false);
353  setExtHALT(false);
354  setIM(0);
355  setI(0x00);
356  setR(0x00);
357  T::setMemPtr(0xFFFF);
358  clearPrevious();
359 
360  // We expect this assert to be valid
361  // assert(T::getTimeFast() <= time); // time shouldn't go backwards
362  // But it's disabled for the following reason:
363  // 'motion' (IRC nickname) managed to create a replay file that
364  // contains a reset command that falls in the middle of a Z80
365  // instruction. Replayed commands go via the Scheduler, and are
366  // (typically) executed right after a complete CPU instruction. So
367  // the CPU is (slightly) ahead in time of the about to be executed
368  // reset command.
369  // Normally this situation should never occur: console commands,
370  // hotkeys, commands over clicomm, ... are all handled via the global
371  // event mechanism. Such global events are scheduled between CPU
372  // instructions, so also in a replay they should fall between CPU
373  // instructions.
374  // However if for some reason the timing of the emulation changed
375  // (improved emulation accuracy or a bug so that emulation isn't
376  // deterministic or the replay file was edited, ...), then the above
377  // reasoning no longer holds and the assert can trigger.
378  // We need to be robust against loading older replays (when emulation
379  // timing has changed). So in that respect disabling the assert is
380  // good. Though in the example above (motion's replay) it's not clear
381  // whether the assert is really triggered by mixing an old replay
382  // with a newer openMSX version. In any case so far we haven't been
383  // able to reproduce this assert by recording and replaying using a
384  // single openMSX version.
385  T::setTime(time);
386 
387  assert(NMIStatus == 0); // other devices must reset their NMI source
388  assert(IRQStatus == 0); // other devices must reset their IRQ source
389 }
390 
391 // I believe the following two methods are thread safe even without any
392 // locking. The worst that can happen is that we occasionally needlessly
393 // exit the CPU loop, but that's harmless
394 // TODO thread issues are always tricky, can someone confirm this really
395 // is thread safe
396 template<class T> void CPUCore<T>::exitCPULoopAsync()
397 {
398  // can get called from non-main threads
399  exitLoop = true;
400 }
401 template<class T> void CPUCore<T>::exitCPULoopSync()
402 {
403  assert(Thread::isMainThread());
404  exitLoop = true;
405  T::disableLimit();
406 }
407 template<class T> inline bool CPUCore<T>::needExitCPULoop()
408 {
409  // always executed in main thread
410  if (unlikely(exitLoop)) {
411  // Note: The test-and-set is _not_ atomic! But that's fine.
412  // An atomic implementation is trivial (see below), but
413  // this version (at least on x86) avoids the more expensive
414  // instructions on the likely path.
415  exitLoop = false;
416  return true;
417  }
418  return false;
419 
420  // Alternative implementation:
421  // atomically set to false and return the old value
422  //return exitLoop.exchange(false);
423 }
424 
425 template<class T> void CPUCore<T>::setSlowInstructions()
426 {
427  slowInstructions = 2;
428  T::disableLimit();
429 }
430 
431 template<class T> void CPUCore<T>::raiseIRQ()
432 {
433  assert(IRQStatus >= 0);
434  if (IRQStatus == 0) {
435  setSlowInstructions();
436  }
437  IRQStatus = IRQStatus + 1;
438 }
439 
440 template<class T> void CPUCore<T>::lowerIRQ()
441 {
442  IRQStatus = IRQStatus - 1;
443  assert(IRQStatus >= 0);
444 }
445 
446 template<class T> void CPUCore<T>::raiseNMI()
447 {
448  assert(NMIStatus >= 0);
449  if (NMIStatus == 0) {
450  nmiEdge = true;
451  setSlowInstructions();
452  }
453  NMIStatus++;
454 }
455 
456 template<class T> void CPUCore<T>::lowerNMI()
457 {
458  NMIStatus--;
459  assert(NMIStatus >= 0);
460 }
461 
462 template<class T> bool CPUCore<T>::isM1Cycle(unsigned address) const
463 {
464  // This method should only be called from within a MSXDevice::readMem()
465  // method. It can be used to check whether the current read action has
466  // the M1 pin active. The 'address' parameter that is give to readMem()
467  // should be passed (unchanged) to this method.
468  //
469  // This simple implementation works because the rest of the CPUCore
470  // code is careful to only update the PC register on M1 cycles. In
471  // practice that means that the PC is (only) updated at the very end of
472  // every instruction, even if is a multi-byte instruction. Or for
473  // prefix-instructions the PC is also updated after the prefix is
474  // fetched (because such instructions activate M1 twice).
475  return address == getPC();
476 }
477 
478 template<class T> void CPUCore<T>::wait(EmuTime::param time)
479 {
480  assert(time >= getCurrentTime());
481  scheduler.schedule(time);
482  T::advanceTime(time);
483 }
484 
485 template<class T> EmuTime CPUCore<T>::waitCycles(EmuTime::param time, unsigned cycles)
486 {
487  T::add(cycles);
488  EmuTime time2 = T::calcTime(time, cycles);
489  // note: time2 is not necessarily equal to T::getTime() because of the
490  // way how WRITE_PORT() is implemented.
491  scheduler.schedule(time2);
492  return time2;
493 }
494 
495 template<class T> void CPUCore<T>::setNextSyncPoint(EmuTime::param time)
496 {
497  T::setLimit(time);
498 }
499 
500 
501 static inline char toHex(byte x)
502 {
503  return (x < 10) ? (x + '0') : (x - 10 + 'A');
504 }
505 static void toHex(byte x, char* buf)
506 {
507  buf[0] = toHex(x / 16);
508  buf[1] = toHex(x & 15);
509 }
510 
511 template<class T> void CPUCore<T>::disasmCommand(
512  Interpreter& interp, span<const TclObject> tokens, TclObject& result) const
513 {
514  word address = (tokens.size() < 3) ? getPC() : tokens[2].getInt(interp);
515  byte outBuf[4];
516  std::string dasmOutput;
517  unsigned len = dasm(*interface, address, outBuf, dasmOutput,
518  T::getTimeFast());
519  result.addListElement(dasmOutput);
520  char tmp[3]; tmp[2] = 0;
521  for (unsigned i = 0; i < len; ++i) {
522  toHex(outBuf[i], tmp);
523  result.addListElement(tmp);
524  }
525 }
526 
527 template<class T> void CPUCore<T>::update(const Setting& setting)
528 {
529  if (&setting == &freqLocked) {
530  doSetFreq();
531  } else if (&setting == &freqValue) {
532  doSetFreq();
533  } else if (&setting == &traceSetting) {
534  tracingEnabled = traceSetting.getBoolean();
535  }
536 }
537 
538 template<class T> void CPUCore<T>::setFreq(unsigned freq_)
539 {
540  freq = freq_;
541  doSetFreq();
542 }
543 
544 template<class T> void CPUCore<T>::doSetFreq()
545 {
546  if (freqLocked.getBoolean()) {
547  // locked, use value set via setFreq()
548  T::setFreq(freq);
549  } else {
550  // unlocked, use value set by user
551  T::setFreq(freqValue.getInt());
552  }
553 }
554 
555 
556 template<class T> inline byte CPUCore<T>::READ_PORT(unsigned port, unsigned cc)
557 {
558  EmuTime time = T::getTimeFast(cc);
559  scheduler.schedule(time);
560  byte result = interface->readIO(port, time);
561  // note: no forced page-break after IO
562  return result;
563 }
564 
565 template<class T> inline void CPUCore<T>::WRITE_PORT(unsigned port, byte value, unsigned cc)
566 {
567  EmuTime time = T::getTimeFast(cc);
568  scheduler.schedule(time);
569  interface->writeIO(port, value, time);
570  // note: no forced page-break after IO
571 }
572 
573 template<class T> template<bool PRE_PB, bool POST_PB>
574 NEVER_INLINE byte CPUCore<T>::RDMEMslow(unsigned address, unsigned cc)
575 {
576  interface->tick(CacheLineCounters::NonCachedRead);
577  // not cached
578  unsigned high = address >> CacheLine::BITS;
579  if (readCacheLine[high] == nullptr) {
580  // try to cache now (not a valid entry, and not yet tried)
581  unsigned addrBase = address & CacheLine::HIGH;
582  if (const byte* line = interface->getReadCacheLine(addrBase)) {
583  // cached ok
584  T::template PRE_MEM<PRE_PB, POST_PB>(address);
585  T::template POST_MEM< POST_PB>(address);
586  readCacheLine[high] = line - addrBase;
587  return readCacheLine[high][address];
588  }
589  }
590  // uncacheable
591  readCacheLine[high] = reinterpret_cast<const byte*>(1);
592  T::template PRE_MEM<PRE_PB, POST_PB>(address);
593  EmuTime time = T::getTimeFast(cc);
594  scheduler.schedule(time);
595  byte result = interface->readMem(address, time);
596  T::template POST_MEM<POST_PB>(address);
597  return result;
598 }
599 template<class T> template<bool PRE_PB, bool POST_PB>
600 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl2(unsigned address, unsigned cc)
601 {
602  const byte* line = readCacheLine[address >> CacheLine::BITS];
603  if (likely(uintptr_t(line) > 1)) {
604  // cached, fast path
605  T::template PRE_MEM<PRE_PB, POST_PB>(address);
606  T::template POST_MEM< POST_PB>(address);
607  return line[address];
608  } else {
609  return RDMEMslow<PRE_PB, POST_PB>(address, cc); // not inlined
610  }
611 }
612 template<class T> template<bool PRE_PB, bool POST_PB>
613 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl(unsigned address, unsigned cc)
614 {
615  constexpr bool PRE = T::template Normalize<PRE_PB >::value;
616  constexpr bool POST = T::template Normalize<POST_PB>::value;
617  return RDMEM_impl2<PRE, POST>(address, cc);
618 }
619 template<class T> template<unsigned PC_OFFSET> ALWAYS_INLINE byte CPUCore<T>::RDMEM_OPCODE(unsigned cc)
620 {
621  // Real Z80 would update the PC register now. In this implementation
622  // we've chosen to instead update PC only once at the end of the
623  // instruction. (Of course we made sure this difference is not
624  // noticeable by the program).
625  //
626  // See the comments in isM1Cycle() for the motivation for this
627  // deviation. Apart from that functional aspect it also turns out to be
628  // faster to only update PC once per instruction instead of after each
629  // fetch.
630  unsigned address = (getPC() + PC_OFFSET) & 0xFFFF;
631  return RDMEM_impl<false, false>(address, cc);
632 }
633 template<class T> ALWAYS_INLINE byte CPUCore<T>::RDMEM(unsigned address, unsigned cc)
634 {
635  return RDMEM_impl<true, true>(address, cc);
636 }
637 
638 template<class T> template<bool PRE_PB, bool POST_PB>
639 NEVER_INLINE unsigned CPUCore<T>::RD_WORD_slow(unsigned address, unsigned cc)
640 {
641  unsigned res = RDMEM_impl<PRE_PB, false>(address, cc);
642  res += RDMEM_impl<false, POST_PB>((address + 1) & 0xFFFF, cc + T::CC_RDMEM) << 8;
643  return res;
644 }
645 template<class T> template<bool PRE_PB, bool POST_PB>
646 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl2(unsigned address, unsigned cc)
647 {
648  const byte* line = readCacheLine[address >> CacheLine::BITS];
649  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && (uintptr_t(line) > 1))) {
650  // fast path: cached and two bytes in same cache line
651  T::template PRE_WORD<PRE_PB, POST_PB>(address);
652  T::template POST_WORD< POST_PB>(address);
653  return Endian::read_UA_L16(&line[address]);
654  } else {
655  // slow path, not inline
656  return RD_WORD_slow<PRE_PB, POST_PB>(address, cc);
657  }
658 }
659 template<class T> template<bool PRE_PB, bool POST_PB>
660 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl(unsigned address, unsigned cc)
661 {
662  constexpr bool PRE = T::template Normalize<PRE_PB >::value;
663  constexpr bool POST = T::template Normalize<POST_PB>::value;
664  return RD_WORD_impl2<PRE, POST>(address, cc);
665 }
666 template<class T> template<unsigned PC_OFFSET> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_PC(unsigned cc)
667 {
668  unsigned addr = (getPC() + PC_OFFSET) & 0xFFFF;
669  return RD_WORD_impl<false, false>(addr, cc);
670 }
671 template<class T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD(
672  unsigned address, unsigned cc)
673 {
674  return RD_WORD_impl<true, true>(address, cc);
675 }
676 
677 template<class T> template<bool PRE_PB, bool POST_PB>
678 NEVER_INLINE void CPUCore<T>::WRMEMslow(unsigned address, byte value, unsigned cc)
679 {
680  interface->tick(CacheLineCounters::NonCachedWrite);
681  // not cached
682  unsigned high = address >> CacheLine::BITS;
683  if (writeCacheLine[high] == nullptr) {
684  // try to cache now
685  unsigned addrBase = address & CacheLine::HIGH;
686  if (byte* line = interface->getWriteCacheLine(addrBase)) {
687  // cached ok
688  T::template PRE_MEM<PRE_PB, POST_PB>(address);
689  T::template POST_MEM< POST_PB>(address);
690  writeCacheLine[high] = line - addrBase;
691  writeCacheLine[high][address] = value;
692  return;
693  }
694  }
695  // uncacheable
696  writeCacheLine[high] = reinterpret_cast<byte*>(1);
697  T::template PRE_MEM<PRE_PB, POST_PB>(address);
698  EmuTime time = T::getTimeFast(cc);
699  scheduler.schedule(time);
700  interface->writeMem(address, value, time);
701  T::template POST_MEM<POST_PB>(address);
702 }
703 template<class T> template<bool PRE_PB, bool POST_PB>
705  unsigned address, byte value, unsigned cc)
706 {
707  byte* line = writeCacheLine[address >> CacheLine::BITS];
708  if (likely(uintptr_t(line) > 1)) {
709  // cached, fast path
710  T::template PRE_MEM<PRE_PB, POST_PB>(address);
711  T::template POST_MEM< POST_PB>(address);
712  line[address] = value;
713  } else {
714  WRMEMslow<PRE_PB, POST_PB>(address, value, cc); // not inlined
715  }
716 }
717 template<class T> template<bool PRE_PB, bool POST_PB>
719  unsigned address, byte value, unsigned cc)
720 {
721  constexpr bool PRE = T::template Normalize<PRE_PB >::value;
722  constexpr bool POST = T::template Normalize<POST_PB>::value;
723  WRMEM_impl2<PRE, POST>(address, value, cc);
724 }
725 template<class T> ALWAYS_INLINE void CPUCore<T>::WRMEM(
726  unsigned address, byte value, unsigned cc)
727 {
728  WRMEM_impl<true, true>(address, value, cc);
729 }
730 
731 template<class T> NEVER_INLINE void CPUCore<T>::WR_WORD_slow(
732  unsigned address, unsigned value, unsigned cc)
733 {
734  WRMEM_impl<true, false>( address, value & 255, cc);
735  WRMEM_impl<false, true>((address + 1) & 0xFFFF, value >> 8, cc + T::CC_WRMEM);
736 }
737 template<class T> ALWAYS_INLINE void CPUCore<T>::WR_WORD(
738  unsigned address, unsigned value, unsigned cc)
739 {
740  byte* line = writeCacheLine[address >> CacheLine::BITS];
741  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && (uintptr_t(line) > 1))) {
742  // fast path: cached and two bytes in same cache line
743  T::template PRE_WORD<true, true>(address);
744  T::template POST_WORD< true>(address);
745  Endian::write_UA_L16(&line[address], value);
746  } else {
747  // slow path, not inline
748  WR_WORD_slow(address, value, cc);
749  }
750 }
751 
752 // same as WR_WORD, but writes high byte first
753 template<class T> template<bool PRE_PB, bool POST_PB>
755  unsigned address, unsigned value, unsigned cc)
756 {
757  WRMEM_impl<PRE_PB, false>((address + 1) & 0xFFFF, value >> 8, cc);
758  WRMEM_impl<false, POST_PB>( address, value & 255, cc + T::CC_WRMEM);
759 }
760 template<class T> template<bool PRE_PB, bool POST_PB>
762  unsigned address, unsigned value, unsigned cc)
763 {
764  byte* line = writeCacheLine[address >> CacheLine::BITS];
765  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && (uintptr_t(line) > 1))) {
766  // fast path: cached and two bytes in same cache line
767  T::template PRE_WORD<PRE_PB, POST_PB>(address);
768  T::template POST_WORD< POST_PB>(address);
769  Endian::write_UA_L16(&line[address], value);
770  } else {
771  // slow path, not inline
772  WR_WORD_rev_slow<PRE_PB, POST_PB>(address, value, cc);
773  }
774 }
775 template<class T> template<bool PRE_PB, bool POST_PB>
777  unsigned address, unsigned value, unsigned cc)
778 {
779  constexpr bool PRE = T::template Normalize<PRE_PB >::value;
780  constexpr bool POST = T::template Normalize<POST_PB>::value;
781  WR_WORD_rev2<PRE, POST>(address, value, cc);
782 }
783 
784 
785 // NMI interrupt
786 template<class T> inline void CPUCore<T>::nmi()
787 {
788  incR(1);
789  setHALT(false);
790  setIFF1(false);
791  PUSH<T::EE_NMI_1>(getPC());
792  setPC(0x0066);
793  T::add(T::CC_NMI);
794 }
795 
796 // IM0 interrupt
797 template<class T> inline void CPUCore<T>::irq0()
798 {
799  // TODO current implementation only works for 1-byte instructions
800  // ok for MSX
801  assert(interface->readIRQVector() == 0xFF);
802  incR(1);
803  setHALT(false);
804  setIFF1(false);
805  setIFF2(false);
806  PUSH<T::EE_IRQ0_1>(getPC());
807  setPC(0x0038);
808  T::setMemPtr(getPC());
809  T::add(T::CC_IRQ0);
810 }
811 
812 // IM1 interrupt
813 template<class T> inline void CPUCore<T>::irq1()
814 {
815  incR(1);
816  setHALT(false);
817  setIFF1(false);
818  setIFF2(false);
819  PUSH<T::EE_IRQ1_1>(getPC());
820  setPC(0x0038);
821  T::setMemPtr(getPC());
822  T::add(T::CC_IRQ1);
823 }
824 
825 // IM2 interrupt
826 template<class T> inline void CPUCore<T>::irq2()
827 {
828  incR(1);
829  setHALT(false);
830  setIFF1(false);
831  setIFF2(false);
832  PUSH<T::EE_IRQ2_1>(getPC());
833  unsigned x = interface->readIRQVector() | (getI() << 8);
834  setPC(RD_WORD(x, T::CC_IRQ2_2));
835  T::setMemPtr(getPC());
836  T::add(T::CC_IRQ2);
837 }
838 
839 template<class T>
841 {
842  checkNoCurrentFlags();
843 #ifdef USE_COMPUTED_GOTO
844  // Addresses of all main-opcode routines,
845  // Note that 40/49/53/5B/64/6D/7F is replaced by 00 (ld r,r == nop)
846  static void* opcodeTable[256] = {
847  &&op00, &&op01, &&op02, &&op03, &&op04, &&op05, &&op06, &&op07,
848  &&op08, &&op09, &&op0A, &&op0B, &&op0C, &&op0D, &&op0E, &&op0F,
849  &&op10, &&op11, &&op12, &&op13, &&op14, &&op15, &&op16, &&op17,
850  &&op18, &&op19, &&op1A, &&op1B, &&op1C, &&op1D, &&op1E, &&op1F,
851  &&op20, &&op21, &&op22, &&op23, &&op24, &&op25, &&op26, &&op27,
852  &&op28, &&op29, &&op2A, &&op2B, &&op2C, &&op2D, &&op2E, &&op2F,
853  &&op30, &&op31, &&op32, &&op33, &&op34, &&op35, &&op36, &&op37,
854  &&op38, &&op39, &&op3A, &&op3B, &&op3C, &&op3D, &&op3E, &&op3F,
855  &&op00, &&op41, &&op42, &&op43, &&op44, &&op45, &&op46, &&op47,
856  &&op48, &&op00, &&op4A, &&op4B, &&op4C, &&op4D, &&op4E, &&op4F,
857  &&op50, &&op51, &&op00, &&op53, &&op54, &&op55, &&op56, &&op57,
858  &&op58, &&op59, &&op5A, &&op00, &&op5C, &&op5D, &&op5E, &&op5F,
859  &&op60, &&op61, &&op62, &&op63, &&op00, &&op65, &&op66, &&op67,
860  &&op68, &&op69, &&op6A, &&op6B, &&op6C, &&op00, &&op6E, &&op6F,
861  &&op70, &&op71, &&op72, &&op73, &&op74, &&op75, &&op76, &&op77,
862  &&op78, &&op79, &&op7A, &&op7B, &&op7C, &&op7D, &&op7E, &&op00,
863  &&op80, &&op81, &&op82, &&op83, &&op84, &&op85, &&op86, &&op87,
864  &&op88, &&op89, &&op8A, &&op8B, &&op8C, &&op8D, &&op8E, &&op8F,
865  &&op90, &&op91, &&op92, &&op93, &&op94, &&op95, &&op96, &&op97,
866  &&op98, &&op99, &&op9A, &&op9B, &&op9C, &&op9D, &&op9E, &&op9F,
867  &&opA0, &&opA1, &&opA2, &&opA3, &&opA4, &&opA5, &&opA6, &&opA7,
868  &&opA8, &&opA9, &&opAA, &&opAB, &&opAC, &&opAD, &&opAE, &&opAF,
869  &&opB0, &&opB1, &&opB2, &&opB3, &&opB4, &&opB5, &&opB6, &&opB7,
870  &&opB8, &&opB9, &&opBA, &&opBB, &&opBC, &&opBD, &&opBE, &&opBF,
871  &&opC0, &&opC1, &&opC2, &&opC3, &&opC4, &&opC5, &&opC6, &&opC7,
872  &&opC8, &&opC9, &&opCA, &&opCB, &&opCC, &&opCD, &&opCE, &&opCF,
873  &&opD0, &&opD1, &&opD2, &&opD3, &&opD4, &&opD5, &&opD6, &&opD7,
874  &&opD8, &&opD9, &&opDA, &&opDB, &&opDC, &&opDD, &&opDE, &&opDF,
875  &&opE0, &&opE1, &&opE2, &&opE3, &&opE4, &&opE5, &&opE6, &&opE7,
876  &&opE8, &&opE9, &&opEA, &&opEB, &&opEC, &&opED, &&opEE, &&opEF,
877  &&opF0, &&opF1, &&opF2, &&opF3, &&opF4, &&opF5, &&opF6, &&opF7,
878  &&opF8, &&opF9, &&opFA, &&opFB, &&opFC, &&opFD, &&opFE, &&opFF,
879  };
880 
881 // Check T::limitReached(). If it's OK to continue,
882 // fetch and execute next instruction.
883 #define NEXT \
884  setPC(getPC() + ii.length); \
885  T::add(ii.cycles); \
886  T::R800Refresh(*this); \
887  if (likely(!T::limitReached())) { \
888  incR(1); \
889  unsigned address = getPC(); \
890  const byte* line = readCacheLine[address >> CacheLine::BITS]; \
891  if (likely(uintptr_t(line) > 1)) { \
892  T::template PRE_MEM<false, false>(address); \
893  T::template POST_MEM< false>(address); \
894  byte op = line[address]; \
895  goto *(opcodeTable[op]); \
896  } else { \
897  goto fetchSlow; \
898  } \
899  } \
900  return;
901 
902 // After some instructions we must always exit the CPU loop (ei, halt, retn)
903 #define NEXT_STOP \
904  setPC(getPC() + ii.length); \
905  T::add(ii.cycles); \
906  T::R800Refresh(*this); \
907  assert(T::limitReached()); \
908  return;
909 
910 #define NEXT_EI \
911  setPC(getPC() + ii.length); \
912  T::add(ii.cycles); \
913  /* !! NO T::R800Refresh(*this); !! */ \
914  assert(T::limitReached()); \
915  return;
916 
917 // Define a label (instead of case in a switch statement)
918 #define CASE(X) op##X:
919 
920 #else // USE_COMPUTED_GOTO
921 
922 #define NEXT \
923  setPC(getPC() + ii.length); \
924  T::add(ii.cycles); \
925  T::R800Refresh(*this); \
926  if (likely(!T::limitReached())) { \
927  goto start; \
928  } \
929  return;
930 
931 #define NEXT_STOP \
932  setPC(getPC() + ii.length); \
933  T::add(ii.cycles); \
934  T::R800Refresh(*this); \
935  assert(T::limitReached()); \
936  return;
937 
938 #define NEXT_EI \
939  setPC(getPC() + ii.length); \
940  T::add(ii.cycles); \
941  /* !! NO T::R800Refresh(*this); !! */ \
942  assert(T::limitReached()); \
943  return;
944 
945 #define CASE(X) case 0x##X:
946 
947 #endif // USE_COMPUTED_GOTO
948 
949 #ifndef USE_COMPUTED_GOTO
950 start:
951 #endif
952  unsigned ixy; // for dd_cb/fd_cb
953  byte opcodeMain = RDMEM_OPCODE<0>(T::CC_MAIN);
954  incR(1);
955 #ifdef USE_COMPUTED_GOTO
956  goto *(opcodeTable[opcodeMain]);
957 
958 fetchSlow: {
959  unsigned address = getPC();
960  byte opcodeSlow = RDMEMslow<false, false>(address, T::CC_MAIN);
961  goto *(opcodeTable[opcodeSlow]);
962 }
963 #endif
964 
965 #ifndef USE_COMPUTED_GOTO
966 switchopcode:
967  switch (opcodeMain) {
968 CASE(40) // ld b,b
969 CASE(49) // ld c,c
970 CASE(52) // ld d,d
971 CASE(5B) // ld e,e
972 CASE(64) // ld h,h
973 CASE(6D) // ld l,l
974 CASE(7F) // ld a,a
975 #endif
976 CASE(00) { II ii = nop(); NEXT; }
977 CASE(07) { II ii = rlca(); NEXT; }
978 CASE(0F) { II ii = rrca(); NEXT; }
979 CASE(17) { II ii = rla(); NEXT; }
980 CASE(1F) { II ii = rra(); NEXT; }
981 CASE(08) { II ii = ex_af_af(); NEXT; }
982 CASE(27) { II ii = daa(); NEXT; }
983 CASE(2F) { II ii = cpl(); NEXT; }
984 CASE(37) { II ii = scf(); NEXT; }
985 CASE(3F) { II ii = ccf(); NEXT; }
986 CASE(20) { II ii = jr(CondNZ()); NEXT; }
987 CASE(28) { II ii = jr(CondZ ()); NEXT; }
988 CASE(30) { II ii = jr(CondNC()); NEXT; }
989 CASE(38) { II ii = jr(CondC ()); NEXT; }
990 CASE(18) { II ii = jr(CondTrue()); NEXT; }
991 CASE(10) { II ii = djnz(); NEXT; }
992 CASE(32) { II ii = ld_xbyte_a(); NEXT; }
993 CASE(3A) { II ii = ld_a_xbyte(); NEXT; }
994 CASE(22) { II ii = ld_xword_SS<HL,0>(); NEXT; }
995 CASE(2A) { II ii = ld_SS_xword<HL,0>(); NEXT; }
996 CASE(02) { II ii = ld_SS_a<BC>(); NEXT; }
997 CASE(12) { II ii = ld_SS_a<DE>(); NEXT; }
998 CASE(1A) { II ii = ld_a_SS<DE>(); NEXT; }
999 CASE(0A) { II ii = ld_a_SS<BC>(); NEXT; }
1000 CASE(03) { II ii = inc_SS<BC,0>(); NEXT; }
1001 CASE(13) { II ii = inc_SS<DE,0>(); NEXT; }
1002 CASE(23) { II ii = inc_SS<HL,0>(); NEXT; }
1003 CASE(33) { II ii = inc_SS<SP,0>(); NEXT; }
1004 CASE(0B) { II ii = dec_SS<BC,0>(); NEXT; }
1005 CASE(1B) { II ii = dec_SS<DE,0>(); NEXT; }
1006 CASE(2B) { II ii = dec_SS<HL,0>(); NEXT; }
1007 CASE(3B) { II ii = dec_SS<SP,0>(); NEXT; }
1008 CASE(09) { II ii = add_SS_TT<HL,BC,0>(); NEXT; }
1009 CASE(19) { II ii = add_SS_TT<HL,DE,0>(); NEXT; }
1010 CASE(29) { II ii = add_SS_SS<HL ,0>(); NEXT; }
1011 CASE(39) { II ii = add_SS_TT<HL,SP,0>(); NEXT; }
1012 CASE(01) { II ii = ld_SS_word<BC,0>(); NEXT; }
1013 CASE(11) { II ii = ld_SS_word<DE,0>(); NEXT; }
1014 CASE(21) { II ii = ld_SS_word<HL,0>(); NEXT; }
1015 CASE(31) { II ii = ld_SS_word<SP,0>(); NEXT; }
1016 CASE(04) { II ii = inc_R<B,0>(); NEXT; }
1017 CASE(0C) { II ii = inc_R<C,0>(); NEXT; }
1018 CASE(14) { II ii = inc_R<D,0>(); NEXT; }
1019 CASE(1C) { II ii = inc_R<E,0>(); NEXT; }
1020 CASE(24) { II ii = inc_R<H,0>(); NEXT; }
1021 CASE(2C) { II ii = inc_R<L,0>(); NEXT; }
1022 CASE(3C) { II ii = inc_R<A,0>(); NEXT; }
1023 CASE(34) { II ii = inc_xhl(); NEXT; }
1024 CASE(05) { II ii = dec_R<B,0>(); NEXT; }
1025 CASE(0D) { II ii = dec_R<C,0>(); NEXT; }
1026 CASE(15) { II ii = dec_R<D,0>(); NEXT; }
1027 CASE(1D) { II ii = dec_R<E,0>(); NEXT; }
1028 CASE(25) { II ii = dec_R<H,0>(); NEXT; }
1029 CASE(2D) { II ii = dec_R<L,0>(); NEXT; }
1030 CASE(3D) { II ii = dec_R<A,0>(); NEXT; }
1031 CASE(35) { II ii = dec_xhl(); NEXT; }
1032 CASE(06) { II ii = ld_R_byte<B,0>(); NEXT; }
1033 CASE(0E) { II ii = ld_R_byte<C,0>(); NEXT; }
1034 CASE(16) { II ii = ld_R_byte<D,0>(); NEXT; }
1035 CASE(1E) { II ii = ld_R_byte<E,0>(); NEXT; }
1036 CASE(26) { II ii = ld_R_byte<H,0>(); NEXT; }
1037 CASE(2E) { II ii = ld_R_byte<L,0>(); NEXT; }
1038 CASE(3E) { II ii = ld_R_byte<A,0>(); NEXT; }
1039 CASE(36) { II ii = ld_xhl_byte(); NEXT; }
1040 
1041 CASE(41) { II ii = ld_R_R<B,C,0>(); NEXT; }
1042 CASE(42) { II ii = ld_R_R<B,D,0>(); NEXT; }
1043 CASE(43) { II ii = ld_R_R<B,E,0>(); NEXT; }
1044 CASE(44) { II ii = ld_R_R<B,H,0>(); NEXT; }
1045 CASE(45) { II ii = ld_R_R<B,L,0>(); NEXT; }
1046 CASE(47) { II ii = ld_R_R<B,A,0>(); NEXT; }
1047 CASE(48) { II ii = ld_R_R<C,B,0>(); NEXT; }
1048 CASE(4A) { II ii = ld_R_R<C,D,0>(); NEXT; }
1049 CASE(4B) { II ii = ld_R_R<C,E,0>(); NEXT; }
1050 CASE(4C) { II ii = ld_R_R<C,H,0>(); NEXT; }
1051 CASE(4D) { II ii = ld_R_R<C,L,0>(); NEXT; }
1052 CASE(4F) { II ii = ld_R_R<C,A,0>(); NEXT; }
1053 CASE(50) { II ii = ld_R_R<D,B,0>(); NEXT; }
1054 CASE(51) { II ii = ld_R_R<D,C,0>(); NEXT; }
1055 CASE(53) { II ii = ld_R_R<D,E,0>(); NEXT; }
1056 CASE(54) { II ii = ld_R_R<D,H,0>(); NEXT; }
1057 CASE(55) { II ii = ld_R_R<D,L,0>(); NEXT; }
1058 CASE(57) { II ii = ld_R_R<D,A,0>(); NEXT; }
1059 CASE(58) { II ii = ld_R_R<E,B,0>(); NEXT; }
1060 CASE(59) { II ii = ld_R_R<E,C,0>(); NEXT; }
1061 CASE(5A) { II ii = ld_R_R<E,D,0>(); NEXT; }
1062 CASE(5C) { II ii = ld_R_R<E,H,0>(); NEXT; }
1063 CASE(5D) { II ii = ld_R_R<E,L,0>(); NEXT; }
1064 CASE(5F) { II ii = ld_R_R<E,A,0>(); NEXT; }
1065 CASE(60) { II ii = ld_R_R<H,B,0>(); NEXT; }
1066 CASE(61) { II ii = ld_R_R<H,C,0>(); NEXT; }
1067 CASE(62) { II ii = ld_R_R<H,D,0>(); NEXT; }
1068 CASE(63) { II ii = ld_R_R<H,E,0>(); NEXT; }
1069 CASE(65) { II ii = ld_R_R<H,L,0>(); NEXT; }
1070 CASE(67) { II ii = ld_R_R<H,A,0>(); NEXT; }
1071 CASE(68) { II ii = ld_R_R<L,B,0>(); NEXT; }
1072 CASE(69) { II ii = ld_R_R<L,C,0>(); NEXT; }
1073 CASE(6A) { II ii = ld_R_R<L,D,0>(); NEXT; }
1074 CASE(6B) { II ii = ld_R_R<L,E,0>(); NEXT; }
1075 CASE(6C) { II ii = ld_R_R<L,H,0>(); NEXT; }
1076 CASE(6F) { II ii = ld_R_R<L,A,0>(); NEXT; }
1077 CASE(78) { II ii = ld_R_R<A,B,0>(); NEXT; }
1078 CASE(79) { II ii = ld_R_R<A,C,0>(); NEXT; }
1079 CASE(7A) { II ii = ld_R_R<A,D,0>(); NEXT; }
1080 CASE(7B) { II ii = ld_R_R<A,E,0>(); NEXT; }
1081 CASE(7C) { II ii = ld_R_R<A,H,0>(); NEXT; }
1082 CASE(7D) { II ii = ld_R_R<A,L,0>(); NEXT; }
1083 CASE(70) { II ii = ld_xhl_R<B>(); NEXT; }
1084 CASE(71) { II ii = ld_xhl_R<C>(); NEXT; }
1085 CASE(72) { II ii = ld_xhl_R<D>(); NEXT; }
1086 CASE(73) { II ii = ld_xhl_R<E>(); NEXT; }
1087 CASE(74) { II ii = ld_xhl_R<H>(); NEXT; }
1088 CASE(75) { II ii = ld_xhl_R<L>(); NEXT; }
1089 CASE(77) { II ii = ld_xhl_R<A>(); NEXT; }
1090 CASE(46) { II ii = ld_R_xhl<B>(); NEXT; }
1091 CASE(4E) { II ii = ld_R_xhl<C>(); NEXT; }
1092 CASE(56) { II ii = ld_R_xhl<D>(); NEXT; }
1093 CASE(5E) { II ii = ld_R_xhl<E>(); NEXT; }
1094 CASE(66) { II ii = ld_R_xhl<H>(); NEXT; }
1095 CASE(6E) { II ii = ld_R_xhl<L>(); NEXT; }
1096 CASE(7E) { II ii = ld_R_xhl<A>(); NEXT; }
1097 CASE(76) { II ii = halt(); NEXT_STOP; }
1098 
1099 CASE(80) { II ii = add_a_R<B,0>(); NEXT; }
1100 CASE(81) { II ii = add_a_R<C,0>(); NEXT; }
1101 CASE(82) { II ii = add_a_R<D,0>(); NEXT; }
1102 CASE(83) { II ii = add_a_R<E,0>(); NEXT; }
1103 CASE(84) { II ii = add_a_R<H,0>(); NEXT; }
1104 CASE(85) { II ii = add_a_R<L,0>(); NEXT; }
1105 CASE(86) { II ii = add_a_xhl(); NEXT; }
1106 CASE(87) { II ii = add_a_a(); NEXT; }
1107 CASE(88) { II ii = adc_a_R<B,0>(); NEXT; }
1108 CASE(89) { II ii = adc_a_R<C,0>(); NEXT; }
1109 CASE(8A) { II ii = adc_a_R<D,0>(); NEXT; }
1110 CASE(8B) { II ii = adc_a_R<E,0>(); NEXT; }
1111 CASE(8C) { II ii = adc_a_R<H,0>(); NEXT; }
1112 CASE(8D) { II ii = adc_a_R<L,0>(); NEXT; }
1113 CASE(8E) { II ii = adc_a_xhl(); NEXT; }
1114 CASE(8F) { II ii = adc_a_a(); NEXT; }
1115 CASE(90) { II ii = sub_R<B,0>(); NEXT; }
1116 CASE(91) { II ii = sub_R<C,0>(); NEXT; }
1117 CASE(92) { II ii = sub_R<D,0>(); NEXT; }
1118 CASE(93) { II ii = sub_R<E,0>(); NEXT; }
1119 CASE(94) { II ii = sub_R<H,0>(); NEXT; }
1120 CASE(95) { II ii = sub_R<L,0>(); NEXT; }
1121 CASE(96) { II ii = sub_xhl(); NEXT; }
1122 CASE(97) { II ii = sub_a(); NEXT; }
1123 CASE(98) { II ii = sbc_a_R<B,0>(); NEXT; }
1124 CASE(99) { II ii = sbc_a_R<C,0>(); NEXT; }
1125 CASE(9A) { II ii = sbc_a_R<D,0>(); NEXT; }
1126 CASE(9B) { II ii = sbc_a_R<E,0>(); NEXT; }
1127 CASE(9C) { II ii = sbc_a_R<H,0>(); NEXT; }
1128 CASE(9D) { II ii = sbc_a_R<L,0>(); NEXT; }
1129 CASE(9E) { II ii = sbc_a_xhl(); NEXT; }
1130 CASE(9F) { II ii = sbc_a_a(); NEXT; }
1131 CASE(A0) { II ii = and_R<B,0>(); NEXT; }
1132 CASE(A1) { II ii = and_R<C,0>(); NEXT; }
1133 CASE(A2) { II ii = and_R<D,0>(); NEXT; }
1134 CASE(A3) { II ii = and_R<E,0>(); NEXT; }
1135 CASE(A4) { II ii = and_R<H,0>(); NEXT; }
1136 CASE(A5) { II ii = and_R<L,0>(); NEXT; }
1137 CASE(A6) { II ii = and_xhl(); NEXT; }
1138 CASE(A7) { II ii = and_a(); NEXT; }
1139 CASE(A8) { II ii = xor_R<B,0>(); NEXT; }
1140 CASE(A9) { II ii = xor_R<C,0>(); NEXT; }
1141 CASE(AA) { II ii = xor_R<D,0>(); NEXT; }
1142 CASE(AB) { II ii = xor_R<E,0>(); NEXT; }
1143 CASE(AC) { II ii = xor_R<H,0>(); NEXT; }
1144 CASE(AD) { II ii = xor_R<L,0>(); NEXT; }
1145 CASE(AE) { II ii = xor_xhl(); NEXT; }
1146 CASE(AF) { II ii = xor_a(); NEXT; }
1147 CASE(B0) { II ii = or_R<B,0>(); NEXT; }
1148 CASE(B1) { II ii = or_R<C,0>(); NEXT; }
1149 CASE(B2) { II ii = or_R<D,0>(); NEXT; }
1150 CASE(B3) { II ii = or_R<E,0>(); NEXT; }
1151 CASE(B4) { II ii = or_R<H,0>(); NEXT; }
1152 CASE(B5) { II ii = or_R<L,0>(); NEXT; }
1153 CASE(B6) { II ii = or_xhl(); NEXT; }
1154 CASE(B7) { II ii = or_a(); NEXT; }
1155 CASE(B8) { II ii = cp_R<B,0>(); NEXT; }
1156 CASE(B9) { II ii = cp_R<C,0>(); NEXT; }
1157 CASE(BA) { II ii = cp_R<D,0>(); NEXT; }
1158 CASE(BB) { II ii = cp_R<E,0>(); NEXT; }
1159 CASE(BC) { II ii = cp_R<H,0>(); NEXT; }
1160 CASE(BD) { II ii = cp_R<L,0>(); NEXT; }
1161 CASE(BE) { II ii = cp_xhl(); NEXT; }
1162 CASE(BF) { II ii = cp_a(); NEXT; }
1163 
1164 CASE(D3) { II ii = out_byte_a(); NEXT; }
1165 CASE(DB) { II ii = in_a_byte(); NEXT; }
1166 CASE(D9) { II ii = exx(); NEXT; }
1167 CASE(E3) { II ii = ex_xsp_SS<HL,0>(); NEXT; }
1168 CASE(EB) { II ii = ex_de_hl(); NEXT; }
1169 CASE(E9) { II ii = jp_SS<HL,0>(); NEXT; }
1170 CASE(F9) { II ii = ld_sp_SS<HL,0>(); NEXT; }
1171 CASE(F3) { II ii = di(); NEXT; }
1172 CASE(FB) { II ii = ei(); NEXT_EI; }
1173 CASE(C6) { II ii = add_a_byte(); NEXT; }
1174 CASE(CE) { II ii = adc_a_byte(); NEXT; }
1175 CASE(D6) { II ii = sub_byte(); NEXT; }
1176 CASE(DE) { II ii = sbc_a_byte(); NEXT; }
1177 CASE(E6) { II ii = and_byte(); NEXT; }
1178 CASE(EE) { II ii = xor_byte(); NEXT; }
1179 CASE(F6) { II ii = or_byte(); NEXT; }
1180 CASE(FE) { II ii = cp_byte(); NEXT; }
1181 CASE(C0) { II ii = ret(CondNZ()); NEXT; }
1182 CASE(C8) { II ii = ret(CondZ ()); NEXT; }
1183 CASE(D0) { II ii = ret(CondNC()); NEXT; }
1184 CASE(D8) { II ii = ret(CondC ()); NEXT; }
1185 CASE(E0) { II ii = ret(CondPO()); NEXT; }
1186 CASE(E8) { II ii = ret(CondPE()); NEXT; }
1187 CASE(F0) { II ii = ret(CondP ()); NEXT; }
1188 CASE(F8) { II ii = ret(CondM ()); NEXT; }
1189 CASE(C9) { II ii = ret(); NEXT; }
1190 CASE(C2) { II ii = jp(CondNZ()); NEXT; }
1191 CASE(CA) { II ii = jp(CondZ ()); NEXT; }
1192 CASE(D2) { II ii = jp(CondNC()); NEXT; }
1193 CASE(DA) { II ii = jp(CondC ()); NEXT; }
1194 CASE(E2) { II ii = jp(CondPO()); NEXT; }
1195 CASE(EA) { II ii = jp(CondPE()); NEXT; }
1196 CASE(F2) { II ii = jp(CondP ()); NEXT; }
1197 CASE(FA) { II ii = jp(CondM ()); NEXT; }
1198 CASE(C3) { II ii = jp(CondTrue()); NEXT; }
1199 CASE(C4) { II ii = call(CondNZ()); NEXT; }
1200 CASE(CC) { II ii = call(CondZ ()); NEXT; }
1201 CASE(D4) { II ii = call(CondNC()); NEXT; }
1202 CASE(DC) { II ii = call(CondC ()); NEXT; }
1203 CASE(E4) { II ii = call(CondPO()); NEXT; }
1204 CASE(EC) { II ii = call(CondPE()); NEXT; }
1205 CASE(F4) { II ii = call(CondP ()); NEXT; }
1206 CASE(FC) { II ii = call(CondM ()); NEXT; }
1207 CASE(CD) { II ii = call(CondTrue()); NEXT; }
1208 CASE(C1) { II ii = pop_SS <BC,0>(); NEXT; }
1209 CASE(D1) { II ii = pop_SS <DE,0>(); NEXT; }
1210 CASE(E1) { II ii = pop_SS <HL,0>(); NEXT; }
1211 CASE(F1) { II ii = pop_SS <AF,0>(); NEXT; }
1212 CASE(C5) { II ii = push_SS<BC,0>(); NEXT; }
1213 CASE(D5) { II ii = push_SS<DE,0>(); NEXT; }
1214 CASE(E5) { II ii = push_SS<HL,0>(); NEXT; }
1215 CASE(F5) { II ii = push_SS<AF,0>(); NEXT; }
1216 CASE(C7) { II ii = rst<0x00>(); NEXT; }
1217 CASE(CF) { II ii = rst<0x08>(); NEXT; }
1218 CASE(D7) { II ii = rst<0x10>(); NEXT; }
1219 CASE(DF) { II ii = rst<0x18>(); NEXT; }
1220 CASE(E7) { II ii = rst<0x20>(); NEXT; }
1221 CASE(EF) { II ii = rst<0x28>(); NEXT; }
1222 CASE(F7) { II ii = rst<0x30>(); NEXT; }
1223 CASE(FF) { II ii = rst<0x38>(); NEXT; }
1224 CASE(CB) {
1225  setPC(getPC() + 1); // M1 cycle at this point
1226  byte cb_opcode = RDMEM_OPCODE<0>(T::CC_PREFIX);
1227  incR(1);
1228  switch (cb_opcode) {
1229  case 0x00: { II ii = rlc_R<B>(); NEXT; }
1230  case 0x01: { II ii = rlc_R<C>(); NEXT; }
1231  case 0x02: { II ii = rlc_R<D>(); NEXT; }
1232  case 0x03: { II ii = rlc_R<E>(); NEXT; }
1233  case 0x04: { II ii = rlc_R<H>(); NEXT; }
1234  case 0x05: { II ii = rlc_R<L>(); NEXT; }
1235  case 0x07: { II ii = rlc_R<A>(); NEXT; }
1236  case 0x06: { II ii = rlc_xhl(); NEXT; }
1237  case 0x08: { II ii = rrc_R<B>(); NEXT; }
1238  case 0x09: { II ii = rrc_R<C>(); NEXT; }
1239  case 0x0a: { II ii = rrc_R<D>(); NEXT; }
1240  case 0x0b: { II ii = rrc_R<E>(); NEXT; }
1241  case 0x0c: { II ii = rrc_R<H>(); NEXT; }
1242  case 0x0d: { II ii = rrc_R<L>(); NEXT; }
1243  case 0x0f: { II ii = rrc_R<A>(); NEXT; }
1244  case 0x0e: { II ii = rrc_xhl(); NEXT; }
1245  case 0x10: { II ii = rl_R<B>(); NEXT; }
1246  case 0x11: { II ii = rl_R<C>(); NEXT; }
1247  case 0x12: { II ii = rl_R<D>(); NEXT; }
1248  case 0x13: { II ii = rl_R<E>(); NEXT; }
1249  case 0x14: { II ii = rl_R<H>(); NEXT; }
1250  case 0x15: { II ii = rl_R<L>(); NEXT; }
1251  case 0x17: { II ii = rl_R<A>(); NEXT; }
1252  case 0x16: { II ii = rl_xhl(); NEXT; }
1253  case 0x18: { II ii = rr_R<B>(); NEXT; }
1254  case 0x19: { II ii = rr_R<C>(); NEXT; }
1255  case 0x1a: { II ii = rr_R<D>(); NEXT; }
1256  case 0x1b: { II ii = rr_R<E>(); NEXT; }
1257  case 0x1c: { II ii = rr_R<H>(); NEXT; }
1258  case 0x1d: { II ii = rr_R<L>(); NEXT; }
1259  case 0x1f: { II ii = rr_R<A>(); NEXT; }
1260  case 0x1e: { II ii = rr_xhl(); NEXT; }
1261  case 0x20: { II ii = sla_R<B>(); NEXT; }
1262  case 0x21: { II ii = sla_R<C>(); NEXT; }
1263  case 0x22: { II ii = sla_R<D>(); NEXT; }
1264  case 0x23: { II ii = sla_R<E>(); NEXT; }
1265  case 0x24: { II ii = sla_R<H>(); NEXT; }
1266  case 0x25: { II ii = sla_R<L>(); NEXT; }
1267  case 0x27: { II ii = sla_R<A>(); NEXT; }
1268  case 0x26: { II ii = sla_xhl(); NEXT; }
1269  case 0x28: { II ii = sra_R<B>(); NEXT; }
1270  case 0x29: { II ii = sra_R<C>(); NEXT; }
1271  case 0x2a: { II ii = sra_R<D>(); NEXT; }
1272  case 0x2b: { II ii = sra_R<E>(); NEXT; }
1273  case 0x2c: { II ii = sra_R<H>(); NEXT; }
1274  case 0x2d: { II ii = sra_R<L>(); NEXT; }
1275  case 0x2f: { II ii = sra_R<A>(); NEXT; }
1276  case 0x2e: { II ii = sra_xhl(); NEXT; }
1277  case 0x30: { II ii = T::isR800() ? sla_R<B>() : sll_R<B>(); NEXT; }
1278  case 0x31: { II ii = T::isR800() ? sla_R<C>() : sll_R<C>(); NEXT; }
1279  case 0x32: { II ii = T::isR800() ? sla_R<D>() : sll_R<D>(); NEXT; }
1280  case 0x33: { II ii = T::isR800() ? sla_R<E>() : sll_R<E>(); NEXT; }
1281  case 0x34: { II ii = T::isR800() ? sla_R<H>() : sll_R<H>(); NEXT; }
1282  case 0x35: { II ii = T::isR800() ? sla_R<L>() : sll_R<L>(); NEXT; }
1283  case 0x37: { II ii = T::isR800() ? sla_R<A>() : sll_R<A>(); NEXT; }
1284  case 0x36: { II ii = T::isR800() ? sla_xhl() : sll_xhl(); NEXT; }
1285  case 0x38: { II ii = srl_R<B>(); NEXT; }
1286  case 0x39: { II ii = srl_R<C>(); NEXT; }
1287  case 0x3a: { II ii = srl_R<D>(); NEXT; }
1288  case 0x3b: { II ii = srl_R<E>(); NEXT; }
1289  case 0x3c: { II ii = srl_R<H>(); NEXT; }
1290  case 0x3d: { II ii = srl_R<L>(); NEXT; }
1291  case 0x3f: { II ii = srl_R<A>(); NEXT; }
1292  case 0x3e: { II ii = srl_xhl(); NEXT; }
1293 
1294  case 0x40: { II ii = bit_N_R<0,B>(); NEXT; }
1295  case 0x41: { II ii = bit_N_R<0,C>(); NEXT; }
1296  case 0x42: { II ii = bit_N_R<0,D>(); NEXT; }
1297  case 0x43: { II ii = bit_N_R<0,E>(); NEXT; }
1298  case 0x44: { II ii = bit_N_R<0,H>(); NEXT; }
1299  case 0x45: { II ii = bit_N_R<0,L>(); NEXT; }
1300  case 0x47: { II ii = bit_N_R<0,A>(); NEXT; }
1301  case 0x48: { II ii = bit_N_R<1,B>(); NEXT; }
1302  case 0x49: { II ii = bit_N_R<1,C>(); NEXT; }
1303  case 0x4a: { II ii = bit_N_R<1,D>(); NEXT; }
1304  case 0x4b: { II ii = bit_N_R<1,E>(); NEXT; }
1305  case 0x4c: { II ii = bit_N_R<1,H>(); NEXT; }
1306  case 0x4d: { II ii = bit_N_R<1,L>(); NEXT; }
1307  case 0x4f: { II ii = bit_N_R<1,A>(); NEXT; }
1308  case 0x50: { II ii = bit_N_R<2,B>(); NEXT; }
1309  case 0x51: { II ii = bit_N_R<2,C>(); NEXT; }
1310  case 0x52: { II ii = bit_N_R<2,D>(); NEXT; }
1311  case 0x53: { II ii = bit_N_R<2,E>(); NEXT; }
1312  case 0x54: { II ii = bit_N_R<2,H>(); NEXT; }
1313  case 0x55: { II ii = bit_N_R<2,L>(); NEXT; }
1314  case 0x57: { II ii = bit_N_R<2,A>(); NEXT; }
1315  case 0x58: { II ii = bit_N_R<3,B>(); NEXT; }
1316  case 0x59: { II ii = bit_N_R<3,C>(); NEXT; }
1317  case 0x5a: { II ii = bit_N_R<3,D>(); NEXT; }
1318  case 0x5b: { II ii = bit_N_R<3,E>(); NEXT; }
1319  case 0x5c: { II ii = bit_N_R<3,H>(); NEXT; }
1320  case 0x5d: { II ii = bit_N_R<3,L>(); NEXT; }
1321  case 0x5f: { II ii = bit_N_R<3,A>(); NEXT; }
1322  case 0x60: { II ii = bit_N_R<4,B>(); NEXT; }
1323  case 0x61: { II ii = bit_N_R<4,C>(); NEXT; }
1324  case 0x62: { II ii = bit_N_R<4,D>(); NEXT; }
1325  case 0x63: { II ii = bit_N_R<4,E>(); NEXT; }
1326  case 0x64: { II ii = bit_N_R<4,H>(); NEXT; }
1327  case 0x65: { II ii = bit_N_R<4,L>(); NEXT; }
1328  case 0x67: { II ii = bit_N_R<4,A>(); NEXT; }
1329  case 0x68: { II ii = bit_N_R<5,B>(); NEXT; }
1330  case 0x69: { II ii = bit_N_R<5,C>(); NEXT; }
1331  case 0x6a: { II ii = bit_N_R<5,D>(); NEXT; }
1332  case 0x6b: { II ii = bit_N_R<5,E>(); NEXT; }
1333  case 0x6c: { II ii = bit_N_R<5,H>(); NEXT; }
1334  case 0x6d: { II ii = bit_N_R<5,L>(); NEXT; }
1335  case 0x6f: { II ii = bit_N_R<5,A>(); NEXT; }
1336  case 0x70: { II ii = bit_N_R<6,B>(); NEXT; }
1337  case 0x71: { II ii = bit_N_R<6,C>(); NEXT; }
1338  case 0x72: { II ii = bit_N_R<6,D>(); NEXT; }
1339  case 0x73: { II ii = bit_N_R<6,E>(); NEXT; }
1340  case 0x74: { II ii = bit_N_R<6,H>(); NEXT; }
1341  case 0x75: { II ii = bit_N_R<6,L>(); NEXT; }
1342  case 0x77: { II ii = bit_N_R<6,A>(); NEXT; }
1343  case 0x78: { II ii = bit_N_R<7,B>(); NEXT; }
1344  case 0x79: { II ii = bit_N_R<7,C>(); NEXT; }
1345  case 0x7a: { II ii = bit_N_R<7,D>(); NEXT; }
1346  case 0x7b: { II ii = bit_N_R<7,E>(); NEXT; }
1347  case 0x7c: { II ii = bit_N_R<7,H>(); NEXT; }
1348  case 0x7d: { II ii = bit_N_R<7,L>(); NEXT; }
1349  case 0x7f: { II ii = bit_N_R<7,A>(); NEXT; }
1350  case 0x46: { II ii = bit_N_xhl<0>(); NEXT; }
1351  case 0x4e: { II ii = bit_N_xhl<1>(); NEXT; }
1352  case 0x56: { II ii = bit_N_xhl<2>(); NEXT; }
1353  case 0x5e: { II ii = bit_N_xhl<3>(); NEXT; }
1354  case 0x66: { II ii = bit_N_xhl<4>(); NEXT; }
1355  case 0x6e: { II ii = bit_N_xhl<5>(); NEXT; }
1356  case 0x76: { II ii = bit_N_xhl<6>(); NEXT; }
1357  case 0x7e: { II ii = bit_N_xhl<7>(); NEXT; }
1358 
1359  case 0x80: { II ii = res_N_R<0,B>(); NEXT; }
1360  case 0x81: { II ii = res_N_R<0,C>(); NEXT; }
1361  case 0x82: { II ii = res_N_R<0,D>(); NEXT; }
1362  case 0x83: { II ii = res_N_R<0,E>(); NEXT; }
1363  case 0x84: { II ii = res_N_R<0,H>(); NEXT; }
1364  case 0x85: { II ii = res_N_R<0,L>(); NEXT; }
1365  case 0x87: { II ii = res_N_R<0,A>(); NEXT; }
1366  case 0x88: { II ii = res_N_R<1,B>(); NEXT; }
1367  case 0x89: { II ii = res_N_R<1,C>(); NEXT; }
1368  case 0x8a: { II ii = res_N_R<1,D>(); NEXT; }
1369  case 0x8b: { II ii = res_N_R<1,E>(); NEXT; }
1370  case 0x8c: { II ii = res_N_R<1,H>(); NEXT; }
1371  case 0x8d: { II ii = res_N_R<1,L>(); NEXT; }
1372  case 0x8f: { II ii = res_N_R<1,A>(); NEXT; }
1373  case 0x90: { II ii = res_N_R<2,B>(); NEXT; }
1374  case 0x91: { II ii = res_N_R<2,C>(); NEXT; }
1375  case 0x92: { II ii = res_N_R<2,D>(); NEXT; }
1376  case 0x93: { II ii = res_N_R<2,E>(); NEXT; }
1377  case 0x94: { II ii = res_N_R<2,H>(); NEXT; }
1378  case 0x95: { II ii = res_N_R<2,L>(); NEXT; }
1379  case 0x97: { II ii = res_N_R<2,A>(); NEXT; }
1380  case 0x98: { II ii = res_N_R<3,B>(); NEXT; }
1381  case 0x99: { II ii = res_N_R<3,C>(); NEXT; }
1382  case 0x9a: { II ii = res_N_R<3,D>(); NEXT; }
1383  case 0x9b: { II ii = res_N_R<3,E>(); NEXT; }
1384  case 0x9c: { II ii = res_N_R<3,H>(); NEXT; }
1385  case 0x9d: { II ii = res_N_R<3,L>(); NEXT; }
1386  case 0x9f: { II ii = res_N_R<3,A>(); NEXT; }
1387  case 0xa0: { II ii = res_N_R<4,B>(); NEXT; }
1388  case 0xa1: { II ii = res_N_R<4,C>(); NEXT; }
1389  case 0xa2: { II ii = res_N_R<4,D>(); NEXT; }
1390  case 0xa3: { II ii = res_N_R<4,E>(); NEXT; }
1391  case 0xa4: { II ii = res_N_R<4,H>(); NEXT; }
1392  case 0xa5: { II ii = res_N_R<4,L>(); NEXT; }
1393  case 0xa7: { II ii = res_N_R<4,A>(); NEXT; }
1394  case 0xa8: { II ii = res_N_R<5,B>(); NEXT; }
1395  case 0xa9: { II ii = res_N_R<5,C>(); NEXT; }
1396  case 0xaa: { II ii = res_N_R<5,D>(); NEXT; }
1397  case 0xab: { II ii = res_N_R<5,E>(); NEXT; }
1398  case 0xac: { II ii = res_N_R<5,H>(); NEXT; }
1399  case 0xad: { II ii = res_N_R<5,L>(); NEXT; }
1400  case 0xaf: { II ii = res_N_R<5,A>(); NEXT; }
1401  case 0xb0: { II ii = res_N_R<6,B>(); NEXT; }
1402  case 0xb1: { II ii = res_N_R<6,C>(); NEXT; }
1403  case 0xb2: { II ii = res_N_R<6,D>(); NEXT; }
1404  case 0xb3: { II ii = res_N_R<6,E>(); NEXT; }
1405  case 0xb4: { II ii = res_N_R<6,H>(); NEXT; }
1406  case 0xb5: { II ii = res_N_R<6,L>(); NEXT; }
1407  case 0xb7: { II ii = res_N_R<6,A>(); NEXT; }
1408  case 0xb8: { II ii = res_N_R<7,B>(); NEXT; }
1409  case 0xb9: { II ii = res_N_R<7,C>(); NEXT; }
1410  case 0xba: { II ii = res_N_R<7,D>(); NEXT; }
1411  case 0xbb: { II ii = res_N_R<7,E>(); NEXT; }
1412  case 0xbc: { II ii = res_N_R<7,H>(); NEXT; }
1413  case 0xbd: { II ii = res_N_R<7,L>(); NEXT; }
1414  case 0xbf: { II ii = res_N_R<7,A>(); NEXT; }
1415  case 0x86: { II ii = res_N_xhl<0>(); NEXT; }
1416  case 0x8e: { II ii = res_N_xhl<1>(); NEXT; }
1417  case 0x96: { II ii = res_N_xhl<2>(); NEXT; }
1418  case 0x9e: { II ii = res_N_xhl<3>(); NEXT; }
1419  case 0xa6: { II ii = res_N_xhl<4>(); NEXT; }
1420  case 0xae: { II ii = res_N_xhl<5>(); NEXT; }
1421  case 0xb6: { II ii = res_N_xhl<6>(); NEXT; }
1422  case 0xbe: { II ii = res_N_xhl<7>(); NEXT; }
1423 
1424  case 0xc0: { II ii = set_N_R<0,B>(); NEXT; }
1425  case 0xc1: { II ii = set_N_R<0,C>(); NEXT; }
1426  case 0xc2: { II ii = set_N_R<0,D>(); NEXT; }
1427  case 0xc3: { II ii = set_N_R<0,E>(); NEXT; }
1428  case 0xc4: { II ii = set_N_R<0,H>(); NEXT; }
1429  case 0xc5: { II ii = set_N_R<0,L>(); NEXT; }
1430  case 0xc7: { II ii = set_N_R<0,A>(); NEXT; }
1431  case 0xc8: { II ii = set_N_R<1,B>(); NEXT; }
1432  case 0xc9: { II ii = set_N_R<1,C>(); NEXT; }
1433  case 0xca: { II ii = set_N_R<1,D>(); NEXT; }
1434  case 0xcb: { II ii = set_N_R<1,E>(); NEXT; }
1435  case 0xcc: { II ii = set_N_R<1,H>(); NEXT; }
1436  case 0xcd: { II ii = set_N_R<1,L>(); NEXT; }
1437  case 0xcf: { II ii = set_N_R<1,A>(); NEXT; }
1438  case 0xd0: { II ii = set_N_R<2,B>(); NEXT; }
1439  case 0xd1: { II ii = set_N_R<2,C>(); NEXT; }
1440  case 0xd2: { II ii = set_N_R<2,D>(); NEXT; }
1441  case 0xd3: { II ii = set_N_R<2,E>(); NEXT; }
1442  case 0xd4: { II ii = set_N_R<2,H>(); NEXT; }
1443  case 0xd5: { II ii = set_N_R<2,L>(); NEXT; }
1444  case 0xd7: { II ii = set_N_R<2,A>(); NEXT; }
1445  case 0xd8: { II ii = set_N_R<3,B>(); NEXT; }
1446  case 0xd9: { II ii = set_N_R<3,C>(); NEXT; }
1447  case 0xda: { II ii = set_N_R<3,D>(); NEXT; }
1448  case 0xdb: { II ii = set_N_R<3,E>(); NEXT; }
1449  case 0xdc: { II ii = set_N_R<3,H>(); NEXT; }
1450  case 0xdd: { II ii = set_N_R<3,L>(); NEXT; }
1451  case 0xdf: { II ii = set_N_R<3,A>(); NEXT; }
1452  case 0xe0: { II ii = set_N_R<4,B>(); NEXT; }
1453  case 0xe1: { II ii = set_N_R<4,C>(); NEXT; }
1454  case 0xe2: { II ii = set_N_R<4,D>(); NEXT; }
1455  case 0xe3: { II ii = set_N_R<4,E>(); NEXT; }
1456  case 0xe4: { II ii = set_N_R<4,H>(); NEXT; }
1457  case 0xe5: { II ii = set_N_R<4,L>(); NEXT; }
1458  case 0xe7: { II ii = set_N_R<4,A>(); NEXT; }
1459  case 0xe8: { II ii = set_N_R<5,B>(); NEXT; }
1460  case 0xe9: { II ii = set_N_R<5,C>(); NEXT; }
1461  case 0xea: { II ii = set_N_R<5,D>(); NEXT; }
1462  case 0xeb: { II ii = set_N_R<5,E>(); NEXT; }
1463  case 0xec: { II ii = set_N_R<5,H>(); NEXT; }
1464  case 0xed: { II ii = set_N_R<5,L>(); NEXT; }
1465  case 0xef: { II ii = set_N_R<5,A>(); NEXT; }
1466  case 0xf0: { II ii = set_N_R<6,B>(); NEXT; }
1467  case 0xf1: { II ii = set_N_R<6,C>(); NEXT; }
1468  case 0xf2: { II ii = set_N_R<6,D>(); NEXT; }
1469  case 0xf3: { II ii = set_N_R<6,E>(); NEXT; }
1470  case 0xf4: { II ii = set_N_R<6,H>(); NEXT; }
1471  case 0xf5: { II ii = set_N_R<6,L>(); NEXT; }
1472  case 0xf7: { II ii = set_N_R<6,A>(); NEXT; }
1473  case 0xf8: { II ii = set_N_R<7,B>(); NEXT; }
1474  case 0xf9: { II ii = set_N_R<7,C>(); NEXT; }
1475  case 0xfa: { II ii = set_N_R<7,D>(); NEXT; }
1476  case 0xfb: { II ii = set_N_R<7,E>(); NEXT; }
1477  case 0xfc: { II ii = set_N_R<7,H>(); NEXT; }
1478  case 0xfd: { II ii = set_N_R<7,L>(); NEXT; }
1479  case 0xff: { II ii = set_N_R<7,A>(); NEXT; }
1480  case 0xc6: { II ii = set_N_xhl<0>(); NEXT; }
1481  case 0xce: { II ii = set_N_xhl<1>(); NEXT; }
1482  case 0xd6: { II ii = set_N_xhl<2>(); NEXT; }
1483  case 0xde: { II ii = set_N_xhl<3>(); NEXT; }
1484  case 0xe6: { II ii = set_N_xhl<4>(); NEXT; }
1485  case 0xee: { II ii = set_N_xhl<5>(); NEXT; }
1486  case 0xf6: { II ii = set_N_xhl<6>(); NEXT; }
1487  case 0xfe: { II ii = set_N_xhl<7>(); NEXT; }
1488  default: UNREACHABLE; return;
1489  }
1490 }
1491 CASE(ED) {
1492  setPC(getPC() + 1); // M1 cycle at this point
1493  byte ed_opcode = RDMEM_OPCODE<0>(T::CC_PREFIX);
1494  incR(1);
1495  switch (ed_opcode) {
1496  case 0x00: case 0x01: case 0x02: case 0x03:
1497  case 0x04: case 0x05: case 0x06: case 0x07:
1498  case 0x08: case 0x09: case 0x0a: case 0x0b:
1499  case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1500  case 0x10: case 0x11: case 0x12: case 0x13:
1501  case 0x14: case 0x15: case 0x16: case 0x17:
1502  case 0x18: case 0x19: case 0x1a: case 0x1b:
1503  case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1504  case 0x20: case 0x21: case 0x22: case 0x23:
1505  case 0x24: case 0x25: case 0x26: case 0x27:
1506  case 0x28: case 0x29: case 0x2a: case 0x2b:
1507  case 0x2c: case 0x2d: case 0x2e: case 0x2f:
1508  case 0x30: case 0x31: case 0x32: case 0x33:
1509  case 0x34: case 0x35: case 0x36: case 0x37:
1510  case 0x38: case 0x39: case 0x3a: case 0x3b:
1511  case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1512 
1513  case 0x77: case 0x7f:
1514 
1515  case 0x80: case 0x81: case 0x82: case 0x83:
1516  case 0x84: case 0x85: case 0x86: case 0x87:
1517  case 0x88: case 0x89: case 0x8a: case 0x8b:
1518  case 0x8c: case 0x8d: case 0x8e: case 0x8f:
1519  case 0x90: case 0x91: case 0x92: case 0x93:
1520  case 0x94: case 0x95: case 0x96: case 0x97:
1521  case 0x98: case 0x99: case 0x9a: case 0x9b:
1522  case 0x9c: case 0x9d: case 0x9e: case 0x9f:
1523  case 0xa4: case 0xa5: case 0xa6: case 0xa7:
1524  case 0xac: case 0xad: case 0xae: case 0xaf:
1525  case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1526  case 0xbc: case 0xbd: case 0xbe: case 0xbf:
1527 
1528  case 0xc0: case 0xc2:
1529  case 0xc4: case 0xc5: case 0xc6: case 0xc7:
1530  case 0xc8: case 0xca: case 0xcb:
1531  case 0xcc: case 0xcd: case 0xce: case 0xcf:
1532  case 0xd0: case 0xd2: case 0xd3:
1533  case 0xd4: case 0xd5: case 0xd6: case 0xd7:
1534  case 0xd8: case 0xda: case 0xdb:
1535  case 0xdc: case 0xdd: case 0xde: case 0xdf:
1536  case 0xe0: case 0xe1: case 0xe2: case 0xe3:
1537  case 0xe4: case 0xe5: case 0xe6: case 0xe7:
1538  case 0xe8: case 0xe9: case 0xea: case 0xeb:
1539  case 0xec: case 0xed: case 0xee: case 0xef:
1540  case 0xf0: case 0xf1: case 0xf2:
1541  case 0xf4: case 0xf5: case 0xf6: case 0xf7:
1542  case 0xf8: case 0xf9: case 0xfa: case 0xfb:
1543  case 0xfc: case 0xfd: case 0xfe: case 0xff:
1544  { II ii = nop(); NEXT; }
1545 
1546  case 0x40: { II ii = in_R_c<B>(); NEXT; }
1547  case 0x48: { II ii = in_R_c<C>(); NEXT; }
1548  case 0x50: { II ii = in_R_c<D>(); NEXT; }
1549  case 0x58: { II ii = in_R_c<E>(); NEXT; }
1550  case 0x60: { II ii = in_R_c<H>(); NEXT; }
1551  case 0x68: { II ii = in_R_c<L>(); NEXT; }
1552  case 0x70: { II ii = in_R_c<DUMMY>(); NEXT; }
1553  case 0x78: { II ii = in_R_c<A>(); NEXT; }
1554 
1555  case 0x41: { II ii = out_c_R<B>(); NEXT; }
1556  case 0x49: { II ii = out_c_R<C>(); NEXT; }
1557  case 0x51: { II ii = out_c_R<D>(); NEXT; }
1558  case 0x59: { II ii = out_c_R<E>(); NEXT; }
1559  case 0x61: { II ii = out_c_R<H>(); NEXT; }
1560  case 0x69: { II ii = out_c_R<L>(); NEXT; }
1561  case 0x71: { II ii = out_c_0(); NEXT; }
1562  case 0x79: { II ii = out_c_R<A>(); NEXT; }
1563 
1564  case 0x42: { II ii = sbc_hl_SS<BC>(); NEXT; }
1565  case 0x52: { II ii = sbc_hl_SS<DE>(); NEXT; }
1566  case 0x62: { II ii = sbc_hl_hl (); NEXT; }
1567  case 0x72: { II ii = sbc_hl_SS<SP>(); NEXT; }
1568 
1569  case 0x4a: { II ii = adc_hl_SS<BC>(); NEXT; }
1570  case 0x5a: { II ii = adc_hl_SS<DE>(); NEXT; }
1571  case 0x6a: { II ii = adc_hl_hl (); NEXT; }
1572  case 0x7a: { II ii = adc_hl_SS<SP>(); NEXT; }
1573 
1574  case 0x43: { II ii = ld_xword_SS_ED<BC>(); NEXT; }
1575  case 0x53: { II ii = ld_xword_SS_ED<DE>(); NEXT; }
1576  case 0x63: { II ii = ld_xword_SS_ED<HL>(); NEXT; }
1577  case 0x73: { II ii = ld_xword_SS_ED<SP>(); NEXT; }
1578 
1579  case 0x4b: { II ii = ld_SS_xword_ED<BC>(); NEXT; }
1580  case 0x5b: { II ii = ld_SS_xword_ED<DE>(); NEXT; }
1581  case 0x6b: { II ii = ld_SS_xword_ED<HL>(); NEXT; }
1582  case 0x7b: { II ii = ld_SS_xword_ED<SP>(); NEXT; }
1583 
1584  case 0x47: { II ii = ld_i_a(); NEXT; }
1585  case 0x4f: { II ii = ld_r_a(); NEXT; }
1586  case 0x57: { II ii = ld_a_IR<REG_I>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1587  case 0x5f: { II ii = ld_a_IR<REG_R>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1588 
1589  case 0x67: { II ii = rrd(); NEXT; }
1590  case 0x6f: { II ii = rld(); NEXT; }
1591 
1592  case 0x45: case 0x4d: case 0x55: case 0x5d:
1593  case 0x65: case 0x6d: case 0x75: case 0x7d:
1594  { II ii = retn(); NEXT_STOP; }
1595  case 0x46: case 0x4e: case 0x66: case 0x6e:
1596  { II ii = im_N<0>(); NEXT; }
1597  case 0x56: case 0x76:
1598  { II ii = im_N<1>(); NEXT; }
1599  case 0x5e: case 0x7e:
1600  { II ii = im_N<2>(); NEXT; }
1601  case 0x44: case 0x4c: case 0x54: case 0x5c:
1602  case 0x64: case 0x6c: case 0x74: case 0x7c:
1603  { II ii = neg(); NEXT; }
1604 
1605  case 0xa0: { II ii = ldi(); NEXT; }
1606  case 0xa1: { II ii = cpi(); NEXT; }
1607  case 0xa2: { II ii = ini(); NEXT; }
1608  case 0xa3: { II ii = outi(); NEXT; }
1609  case 0xa8: { II ii = ldd(); NEXT; }
1610  case 0xa9: { II ii = cpd(); NEXT; }
1611  case 0xaa: { II ii = ind(); NEXT; }
1612  case 0xab: { II ii = outd(); NEXT; }
1613  case 0xb0: { II ii = ldir(); NEXT; }
1614  case 0xb1: { II ii = cpir(); NEXT; }
1615  case 0xb2: { II ii = inir(); NEXT; }
1616  case 0xb3: { II ii = otir(); NEXT; }
1617  case 0xb8: { II ii = lddr(); NEXT; }
1618  case 0xb9: { II ii = cpdr(); NEXT; }
1619  case 0xba: { II ii = indr(); NEXT; }
1620  case 0xbb: { II ii = otdr(); NEXT; }
1621 
1622  case 0xc1: { II ii = T::isR800() ? mulub_a_R<B>() : nop(); NEXT; }
1623  case 0xc9: { II ii = T::isR800() ? mulub_a_R<C>() : nop(); NEXT; }
1624  case 0xd1: { II ii = T::isR800() ? mulub_a_R<D>() : nop(); NEXT; }
1625  case 0xd9: { II ii = T::isR800() ? mulub_a_R<E>() : nop(); NEXT; }
1626  case 0xc3: { II ii = T::isR800() ? muluw_hl_SS<BC>() : nop(); NEXT; }
1627  case 0xf3: { II ii = T::isR800() ? muluw_hl_SS<SP>() : nop(); NEXT; }
1628  default: UNREACHABLE; return;
1629  }
1630 }
1631 opDD_2:
1632 CASE(DD) {
1633  setPC(getPC() + 1); // M1 cycle at this point
1634  byte opcodeDD = RDMEM_OPCODE<0>(T::CC_DD + T::CC_MAIN);
1635  incR(1);
1636  switch (opcodeDD) {
1637  case 0x00: // nop();
1638  case 0x01: // ld_bc_word();
1639  case 0x02: // ld_xbc_a();
1640  case 0x03: // inc_bc();
1641  case 0x04: // inc_b();
1642  case 0x05: // dec_b();
1643  case 0x06: // ld_b_byte();
1644  case 0x07: // rlca();
1645  case 0x08: // ex_af_af();
1646  case 0x0a: // ld_a_xbc();
1647  case 0x0b: // dec_bc();
1648  case 0x0c: // inc_c();
1649  case 0x0d: // dec_c();
1650  case 0x0e: // ld_c_byte();
1651  case 0x0f: // rrca();
1652  case 0x10: // djnz();
1653  case 0x11: // ld_de_word();
1654  case 0x12: // ld_xde_a();
1655  case 0x13: // inc_de();
1656  case 0x14: // inc_d();
1657  case 0x15: // dec_d();
1658  case 0x16: // ld_d_byte();
1659  case 0x17: // rla();
1660  case 0x18: // jr();
1661  case 0x1a: // ld_a_xde();
1662  case 0x1b: // dec_de();
1663  case 0x1c: // inc_e();
1664  case 0x1d: // dec_e();
1665  case 0x1e: // ld_e_byte();
1666  case 0x1f: // rra();
1667  case 0x20: // jr_nz();
1668  case 0x27: // daa();
1669  case 0x28: // jr_z();
1670  case 0x2f: // cpl();
1671  case 0x30: // jr_nc();
1672  case 0x31: // ld_sp_word();
1673  case 0x32: // ld_xbyte_a();
1674  case 0x33: // inc_sp();
1675  case 0x37: // scf();
1676  case 0x38: // jr_c();
1677  case 0x3a: // ld_a_xbyte();
1678  case 0x3b: // dec_sp();
1679  case 0x3c: // inc_a();
1680  case 0x3d: // dec_a();
1681  case 0x3e: // ld_a_byte();
1682  case 0x3f: // ccf();
1683 
1684  case 0x40: // ld_b_b();
1685  case 0x41: // ld_b_c();
1686  case 0x42: // ld_b_d();
1687  case 0x43: // ld_b_e();
1688  case 0x47: // ld_b_a();
1689  case 0x48: // ld_c_b();
1690  case 0x49: // ld_c_c();
1691  case 0x4a: // ld_c_d();
1692  case 0x4b: // ld_c_e();
1693  case 0x4f: // ld_c_a();
1694  case 0x50: // ld_d_b();
1695  case 0x51: // ld_d_c();
1696  case 0x52: // ld_d_d();
1697  case 0x53: // ld_d_e();
1698  case 0x57: // ld_d_a();
1699  case 0x58: // ld_e_b();
1700  case 0x59: // ld_e_c();
1701  case 0x5a: // ld_e_d();
1702  case 0x5b: // ld_e_e();
1703  case 0x5f: // ld_e_a();
1704  case 0x64: // ld_ixh_ixh(); == nop
1705  case 0x6d: // ld_ixl_ixl(); == nop
1706  case 0x76: // halt();
1707  case 0x78: // ld_a_b();
1708  case 0x79: // ld_a_c();
1709  case 0x7a: // ld_a_d();
1710  case 0x7b: // ld_a_e();
1711  case 0x7f: // ld_a_a();
1712 
1713  case 0x80: // add_a_b();
1714  case 0x81: // add_a_c();
1715  case 0x82: // add_a_d();
1716  case 0x83: // add_a_e();
1717  case 0x87: // add_a_a();
1718  case 0x88: // adc_a_b();
1719  case 0x89: // adc_a_c();
1720  case 0x8a: // adc_a_d();
1721  case 0x8b: // adc_a_e();
1722  case 0x8f: // adc_a_a();
1723  case 0x90: // sub_b();
1724  case 0x91: // sub_c();
1725  case 0x92: // sub_d();
1726  case 0x93: // sub_e();
1727  case 0x97: // sub_a();
1728  case 0x98: // sbc_a_b();
1729  case 0x99: // sbc_a_c();
1730  case 0x9a: // sbc_a_d();
1731  case 0x9b: // sbc_a_e();
1732  case 0x9f: // sbc_a_a();
1733  case 0xa0: // and_b();
1734  case 0xa1: // and_c();
1735  case 0xa2: // and_d();
1736  case 0xa3: // and_e();
1737  case 0xa7: // and_a();
1738  case 0xa8: // xor_b();
1739  case 0xa9: // xor_c();
1740  case 0xaa: // xor_d();
1741  case 0xab: // xor_e();
1742  case 0xaf: // xor_a();
1743  case 0xb0: // or_b();
1744  case 0xb1: // or_c();
1745  case 0xb2: // or_d();
1746  case 0xb3: // or_e();
1747  case 0xb7: // or_a();
1748  case 0xb8: // cp_b();
1749  case 0xb9: // cp_c();
1750  case 0xba: // cp_d();
1751  case 0xbb: // cp_e();
1752  case 0xbf: // cp_a();
1753 
1754  case 0xc0: // ret_nz();
1755  case 0xc1: // pop_bc();
1756  case 0xc2: // jp_nz();
1757  case 0xc3: // jp();
1758  case 0xc4: // call_nz();
1759  case 0xc5: // push_bc();
1760  case 0xc6: // add_a_byte();
1761  case 0xc7: // rst_00();
1762  case 0xc8: // ret_z();
1763  case 0xc9: // ret();
1764  case 0xca: // jp_z();
1765  case 0xcc: // call_z();
1766  case 0xcd: // call();
1767  case 0xce: // adc_a_byte();
1768  case 0xcf: // rst_08();
1769  case 0xd0: // ret_nc();
1770  case 0xd1: // pop_de();
1771  case 0xd2: // jp_nc();
1772  case 0xd3: // out_byte_a();
1773  case 0xd4: // call_nc();
1774  case 0xd5: // push_de();
1775  case 0xd6: // sub_byte();
1776  case 0xd7: // rst_10();
1777  case 0xd8: // ret_c();
1778  case 0xd9: // exx();
1779  case 0xda: // jp_c();
1780  case 0xdb: // in_a_byte();
1781  case 0xdc: // call_c();
1782  case 0xde: // sbc_a_byte();
1783  case 0xdf: // rst_18();
1784  case 0xe0: // ret_po();
1785  case 0xe2: // jp_po();
1786  case 0xe4: // call_po();
1787  case 0xe6: // and_byte();
1788  case 0xe7: // rst_20();
1789  case 0xe8: // ret_pe();
1790  case 0xea: // jp_pe();
1791  case 0xeb: // ex_de_hl();
1792  case 0xec: // call_pe();
1793  case 0xed: // ed();
1794  case 0xee: // xor_byte();
1795  case 0xef: // rst_28();
1796  case 0xf0: // ret_p();
1797  case 0xf1: // pop_af();
1798  case 0xf2: // jp_p();
1799  case 0xf3: // di();
1800  case 0xf4: // call_p();
1801  case 0xf5: // push_af();
1802  case 0xf6: // or_byte();
1803  case 0xf7: // rst_30();
1804  case 0xf8: // ret_m();
1805  case 0xfa: // jp_m();
1806  case 0xfb: // ei();
1807  case 0xfc: // call_m();
1808  case 0xfe: // cp_byte();
1809  case 0xff: // rst_38();
1810  if (T::isR800()) {
1811  II ii = nop();
1812  ii.cycles += T::CC_DD;
1813  NEXT;
1814  } else {
1815  T::add(T::CC_DD);
1816  #ifdef USE_COMPUTED_GOTO
1817  goto *(opcodeTable[opcodeDD]);
1818  #else
1819  opcodeMain = opcodeDD;
1820  goto switchopcode;
1821  #endif
1822  }
1823 
1824  case 0x09: { II ii = add_SS_TT<IX,BC,T::CC_DD>(); NEXT; }
1825  case 0x19: { II ii = add_SS_TT<IX,DE,T::CC_DD>(); NEXT; }
1826  case 0x29: { II ii = add_SS_SS<IX ,T::CC_DD>(); NEXT; }
1827  case 0x39: { II ii = add_SS_TT<IX,SP,T::CC_DD>(); NEXT; }
1828  case 0x21: { II ii = ld_SS_word<IX,T::CC_DD>(); NEXT; }
1829  case 0x22: { II ii = ld_xword_SS<IX,T::CC_DD>(); NEXT; }
1830  case 0x2a: { II ii = ld_SS_xword<IX,T::CC_DD>(); NEXT; }
1831  case 0x23: { II ii = inc_SS<IX,T::CC_DD>(); NEXT; }
1832  case 0x2b: { II ii = dec_SS<IX,T::CC_DD>(); NEXT; }
1833  case 0x24: { II ii = inc_R<IXH,T::CC_DD>(); NEXT; }
1834  case 0x2c: { II ii = inc_R<IXL,T::CC_DD>(); NEXT; }
1835  case 0x25: { II ii = dec_R<IXH,T::CC_DD>(); NEXT; }
1836  case 0x2d: { II ii = dec_R<IXL,T::CC_DD>(); NEXT; }
1837  case 0x26: { II ii = ld_R_byte<IXH,T::CC_DD>(); NEXT; }
1838  case 0x2e: { II ii = ld_R_byte<IXL,T::CC_DD>(); NEXT; }
1839  case 0x34: { II ii = inc_xix<IX>(); NEXT; }
1840  case 0x35: { II ii = dec_xix<IX>(); NEXT; }
1841  case 0x36: { II ii = ld_xix_byte<IX>(); NEXT; }
1842 
1843  case 0x44: { II ii = ld_R_R<B,IXH,T::CC_DD>(); NEXT; }
1844  case 0x45: { II ii = ld_R_R<B,IXL,T::CC_DD>(); NEXT; }
1845  case 0x4c: { II ii = ld_R_R<C,IXH,T::CC_DD>(); NEXT; }
1846  case 0x4d: { II ii = ld_R_R<C,IXL,T::CC_DD>(); NEXT; }
1847  case 0x54: { II ii = ld_R_R<D,IXH,T::CC_DD>(); NEXT; }
1848  case 0x55: { II ii = ld_R_R<D,IXL,T::CC_DD>(); NEXT; }
1849  case 0x5c: { II ii = ld_R_R<E,IXH,T::CC_DD>(); NEXT; }
1850  case 0x5d: { II ii = ld_R_R<E,IXL,T::CC_DD>(); NEXT; }
1851  case 0x7c: { II ii = ld_R_R<A,IXH,T::CC_DD>(); NEXT; }
1852  case 0x7d: { II ii = ld_R_R<A,IXL,T::CC_DD>(); NEXT; }
1853  case 0x60: { II ii = ld_R_R<IXH,B,T::CC_DD>(); NEXT; }
1854  case 0x61: { II ii = ld_R_R<IXH,C,T::CC_DD>(); NEXT; }
1855  case 0x62: { II ii = ld_R_R<IXH,D,T::CC_DD>(); NEXT; }
1856  case 0x63: { II ii = ld_R_R<IXH,E,T::CC_DD>(); NEXT; }
1857  case 0x65: { II ii = ld_R_R<IXH,IXL,T::CC_DD>(); NEXT; }
1858  case 0x67: { II ii = ld_R_R<IXH,A,T::CC_DD>(); NEXT; }
1859  case 0x68: { II ii = ld_R_R<IXL,B,T::CC_DD>(); NEXT; }
1860  case 0x69: { II ii = ld_R_R<IXL,C,T::CC_DD>(); NEXT; }
1861  case 0x6a: { II ii = ld_R_R<IXL,D,T::CC_DD>(); NEXT; }
1862  case 0x6b: { II ii = ld_R_R<IXL,E,T::CC_DD>(); NEXT; }
1863  case 0x6c: { II ii = ld_R_R<IXL,IXH,T::CC_DD>(); NEXT; }
1864  case 0x6f: { II ii = ld_R_R<IXL,A,T::CC_DD>(); NEXT; }
1865  case 0x70: { II ii = ld_xix_R<IX,B>(); NEXT; }
1866  case 0x71: { II ii = ld_xix_R<IX,C>(); NEXT; }
1867  case 0x72: { II ii = ld_xix_R<IX,D>(); NEXT; }
1868  case 0x73: { II ii = ld_xix_R<IX,E>(); NEXT; }
1869  case 0x74: { II ii = ld_xix_R<IX,H>(); NEXT; }
1870  case 0x75: { II ii = ld_xix_R<IX,L>(); NEXT; }
1871  case 0x77: { II ii = ld_xix_R<IX,A>(); NEXT; }
1872  case 0x46: { II ii = ld_R_xix<B,IX>(); NEXT; }
1873  case 0x4e: { II ii = ld_R_xix<C,IX>(); NEXT; }
1874  case 0x56: { II ii = ld_R_xix<D,IX>(); NEXT; }
1875  case 0x5e: { II ii = ld_R_xix<E,IX>(); NEXT; }
1876  case 0x66: { II ii = ld_R_xix<H,IX>(); NEXT; }
1877  case 0x6e: { II ii = ld_R_xix<L,IX>(); NEXT; }
1878  case 0x7e: { II ii = ld_R_xix<A,IX>(); NEXT; }
1879 
1880  case 0x84: { II ii = add_a_R<IXH,T::CC_DD>(); NEXT; }
1881  case 0x85: { II ii = add_a_R<IXL,T::CC_DD>(); NEXT; }
1882  case 0x86: { II ii = add_a_xix<IX>(); NEXT; }
1883  case 0x8c: { II ii = adc_a_R<IXH,T::CC_DD>(); NEXT; }
1884  case 0x8d: { II ii = adc_a_R<IXL,T::CC_DD>(); NEXT; }
1885  case 0x8e: { II ii = adc_a_xix<IX>(); NEXT; }
1886  case 0x94: { II ii = sub_R<IXH,T::CC_DD>(); NEXT; }
1887  case 0x95: { II ii = sub_R<IXL,T::CC_DD>(); NEXT; }
1888  case 0x96: { II ii = sub_xix<IX>(); NEXT; }
1889  case 0x9c: { II ii = sbc_a_R<IXH,T::CC_DD>(); NEXT; }
1890  case 0x9d: { II ii = sbc_a_R<IXL,T::CC_DD>(); NEXT; }
1891  case 0x9e: { II ii = sbc_a_xix<IX>(); NEXT; }
1892  case 0xa4: { II ii = and_R<IXH,T::CC_DD>(); NEXT; }
1893  case 0xa5: { II ii = and_R<IXL,T::CC_DD>(); NEXT; }
1894  case 0xa6: { II ii = and_xix<IX>(); NEXT; }
1895  case 0xac: { II ii = xor_R<IXH,T::CC_DD>(); NEXT; }
1896  case 0xad: { II ii = xor_R<IXL,T::CC_DD>(); NEXT; }
1897  case 0xae: { II ii = xor_xix<IX>(); NEXT; }
1898  case 0xb4: { II ii = or_R<IXH,T::CC_DD>(); NEXT; }
1899  case 0xb5: { II ii = or_R<IXL,T::CC_DD>(); NEXT; }
1900  case 0xb6: { II ii = or_xix<IX>(); NEXT; }
1901  case 0xbc: { II ii = cp_R<IXH,T::CC_DD>(); NEXT; }
1902  case 0xbd: { II ii = cp_R<IXL,T::CC_DD>(); NEXT; }
1903  case 0xbe: { II ii = cp_xix<IX>(); NEXT; }
1904 
1905  case 0xe1: { II ii = pop_SS <IX,T::CC_DD>(); NEXT; }
1906  case 0xe5: { II ii = push_SS<IX,T::CC_DD>(); NEXT; }
1907  case 0xe3: { II ii = ex_xsp_SS<IX,T::CC_DD>(); NEXT; }
1908  case 0xe9: { II ii = jp_SS<IX,T::CC_DD>(); NEXT; }
1909  case 0xf9: { II ii = ld_sp_SS<IX,T::CC_DD>(); NEXT; }
1910  case 0xcb: ixy = getIX(); goto xx_cb;
1911  case 0xdd: T::add(T::CC_DD); goto opDD_2;
1912  case 0xfd: T::add(T::CC_DD); goto opFD_2;
1913  default: UNREACHABLE; return;
1914  }
1915 }
1916 opFD_2:
1917 CASE(FD) {
1918  setPC(getPC() + 1); // M1 cycle at this point
1919  byte opcodeFD = RDMEM_OPCODE<0>(T::CC_DD + T::CC_MAIN);
1920  incR(1);
1921  switch (opcodeFD) {
1922  case 0x00: // nop();
1923  case 0x01: // ld_bc_word();
1924  case 0x02: // ld_xbc_a();
1925  case 0x03: // inc_bc();
1926  case 0x04: // inc_b();
1927  case 0x05: // dec_b();
1928  case 0x06: // ld_b_byte();
1929  case 0x07: // rlca();
1930  case 0x08: // ex_af_af();
1931  case 0x0a: // ld_a_xbc();
1932  case 0x0b: // dec_bc();
1933  case 0x0c: // inc_c();
1934  case 0x0d: // dec_c();
1935  case 0x0e: // ld_c_byte();
1936  case 0x0f: // rrca();
1937  case 0x10: // djnz();
1938  case 0x11: // ld_de_word();
1939  case 0x12: // ld_xde_a();
1940  case 0x13: // inc_de();
1941  case 0x14: // inc_d();
1942  case 0x15: // dec_d();
1943  case 0x16: // ld_d_byte();
1944  case 0x17: // rla();
1945  case 0x18: // jr();
1946  case 0x1a: // ld_a_xde();
1947  case 0x1b: // dec_de();
1948  case 0x1c: // inc_e();
1949  case 0x1d: // dec_e();
1950  case 0x1e: // ld_e_byte();
1951  case 0x1f: // rra();
1952  case 0x20: // jr_nz();
1953  case 0x27: // daa();
1954  case 0x28: // jr_z();
1955  case 0x2f: // cpl();
1956  case 0x30: // jr_nc();
1957  case 0x31: // ld_sp_word();
1958  case 0x32: // ld_xbyte_a();
1959  case 0x33: // inc_sp();
1960  case 0x37: // scf();
1961  case 0x38: // jr_c();
1962  case 0x3a: // ld_a_xbyte();
1963  case 0x3b: // dec_sp();
1964  case 0x3c: // inc_a();
1965  case 0x3d: // dec_a();
1966  case 0x3e: // ld_a_byte();
1967  case 0x3f: // ccf();
1968 
1969  case 0x40: // ld_b_b();
1970  case 0x41: // ld_b_c();
1971  case 0x42: // ld_b_d();
1972  case 0x43: // ld_b_e();
1973  case 0x47: // ld_b_a();
1974  case 0x48: // ld_c_b();
1975  case 0x49: // ld_c_c();
1976  case 0x4a: // ld_c_d();
1977  case 0x4b: // ld_c_e();
1978  case 0x4f: // ld_c_a();
1979  case 0x50: // ld_d_b();
1980  case 0x51: // ld_d_c();
1981  case 0x52: // ld_d_d();
1982  case 0x53: // ld_d_e();
1983  case 0x57: // ld_d_a();
1984  case 0x58: // ld_e_b();
1985  case 0x59: // ld_e_c();
1986  case 0x5a: // ld_e_d();
1987  case 0x5b: // ld_e_e();
1988  case 0x5f: // ld_e_a();
1989  case 0x64: // ld_ixh_ixh(); == nop
1990  case 0x6d: // ld_ixl_ixl(); == nop
1991  case 0x76: // halt();
1992  case 0x78: // ld_a_b();
1993  case 0x79: // ld_a_c();
1994  case 0x7a: // ld_a_d();
1995  case 0x7b: // ld_a_e();
1996  case 0x7f: // ld_a_a();
1997 
1998  case 0x80: // add_a_b();
1999  case 0x81: // add_a_c();
2000  case 0x82: // add_a_d();
2001  case 0x83: // add_a_e();
2002  case 0x87: // add_a_a();
2003  case 0x88: // adc_a_b();
2004  case 0x89: // adc_a_c();
2005  case 0x8a: // adc_a_d();
2006  case 0x8b: // adc_a_e();
2007  case 0x8f: // adc_a_a();
2008  case 0x90: // sub_b();
2009  case 0x91: // sub_c();
2010  case 0x92: // sub_d();
2011  case 0x93: // sub_e();
2012  case 0x97: // sub_a();
2013  case 0x98: // sbc_a_b();
2014  case 0x99: // sbc_a_c();
2015  case 0x9a: // sbc_a_d();
2016  case 0x9b: // sbc_a_e();
2017  case 0x9f: // sbc_a_a();
2018  case 0xa0: // and_b();
2019  case 0xa1: // and_c();
2020  case 0xa2: // and_d();
2021  case 0xa3: // and_e();
2022  case 0xa7: // and_a();
2023  case 0xa8: // xor_b();
2024  case 0xa9: // xor_c();
2025  case 0xaa: // xor_d();
2026  case 0xab: // xor_e();
2027  case 0xaf: // xor_a();
2028  case 0xb0: // or_b();
2029  case 0xb1: // or_c();
2030  case 0xb2: // or_d();
2031  case 0xb3: // or_e();
2032  case 0xb7: // or_a();
2033  case 0xb8: // cp_b();
2034  case 0xb9: // cp_c();
2035  case 0xba: // cp_d();
2036  case 0xbb: // cp_e();
2037  case 0xbf: // cp_a();
2038 
2039  case 0xc0: // ret_nz();
2040  case 0xc1: // pop_bc();
2041  case 0xc2: // jp_nz();
2042  case 0xc3: // jp();
2043  case 0xc4: // call_nz();
2044  case 0xc5: // push_bc();
2045  case 0xc6: // add_a_byte();
2046  case 0xc7: // rst_00();
2047  case 0xc8: // ret_z();
2048  case 0xc9: // ret();
2049  case 0xca: // jp_z();
2050  case 0xcc: // call_z();
2051  case 0xcd: // call();
2052  case 0xce: // adc_a_byte();
2053  case 0xcf: // rst_08();
2054  case 0xd0: // ret_nc();
2055  case 0xd1: // pop_de();
2056  case 0xd2: // jp_nc();
2057  case 0xd3: // out_byte_a();
2058  case 0xd4: // call_nc();
2059  case 0xd5: // push_de();
2060  case 0xd6: // sub_byte();
2061  case 0xd7: // rst_10();
2062  case 0xd8: // ret_c();
2063  case 0xd9: // exx();
2064  case 0xda: // jp_c();
2065  case 0xdb: // in_a_byte();
2066  case 0xdc: // call_c();
2067  case 0xde: // sbc_a_byte();
2068  case 0xdf: // rst_18();
2069  case 0xe0: // ret_po();
2070  case 0xe2: // jp_po();
2071  case 0xe4: // call_po();
2072  case 0xe6: // and_byte();
2073  case 0xe7: // rst_20();
2074  case 0xe8: // ret_pe();
2075  case 0xea: // jp_pe();
2076  case 0xeb: // ex_de_hl();
2077  case 0xec: // call_pe();
2078  case 0xed: // ed();
2079  case 0xee: // xor_byte();
2080  case 0xef: // rst_28();
2081  case 0xf0: // ret_p();
2082  case 0xf1: // pop_af();
2083  case 0xf2: // jp_p();
2084  case 0xf3: // di();
2085  case 0xf4: // call_p();
2086  case 0xf5: // push_af();
2087  case 0xf6: // or_byte();
2088  case 0xf7: // rst_30();
2089  case 0xf8: // ret_m();
2090  case 0xfa: // jp_m();
2091  case 0xfb: // ei();
2092  case 0xfc: // call_m();
2093  case 0xfe: // cp_byte();
2094  case 0xff: // rst_38();
2095  if (T::isR800()) {
2096  II ii = nop();
2097  ii.cycles += T::CC_DD;
2098  NEXT;
2099  } else {
2100  T::add(T::CC_DD);
2101  #ifdef USE_COMPUTED_GOTO
2102  goto *(opcodeTable[opcodeFD]);
2103  #else
2104  opcodeMain = opcodeFD;
2105  goto switchopcode;
2106  #endif
2107  }
2108 
2109  case 0x09: { II ii = add_SS_TT<IY,BC,T::CC_DD>(); NEXT; }
2110  case 0x19: { II ii = add_SS_TT<IY,DE,T::CC_DD>(); NEXT; }
2111  case 0x29: { II ii = add_SS_SS<IY ,T::CC_DD>(); NEXT; }
2112  case 0x39: { II ii = add_SS_TT<IY,SP,T::CC_DD>(); NEXT; }
2113  case 0x21: { II ii = ld_SS_word<IY,T::CC_DD>(); NEXT; }
2114  case 0x22: { II ii = ld_xword_SS<IY,T::CC_DD>(); NEXT; }
2115  case 0x2a: { II ii = ld_SS_xword<IY,T::CC_DD>(); NEXT; }
2116  case 0x23: { II ii = inc_SS<IY,T::CC_DD>(); NEXT; }
2117  case 0x2b: { II ii = dec_SS<IY,T::CC_DD>(); NEXT; }
2118  case 0x24: { II ii = inc_R<IYH,T::CC_DD>(); NEXT; }
2119  case 0x2c: { II ii = inc_R<IYL,T::CC_DD>(); NEXT; }
2120  case 0x25: { II ii = dec_R<IYH,T::CC_DD>(); NEXT; }
2121  case 0x2d: { II ii = dec_R<IYL,T::CC_DD>(); NEXT; }
2122  case 0x26: { II ii = ld_R_byte<IYH,T::CC_DD>(); NEXT; }
2123  case 0x2e: { II ii = ld_R_byte<IYL,T::CC_DD>(); NEXT; }
2124  case 0x34: { II ii = inc_xix<IY>(); NEXT; }
2125  case 0x35: { II ii = dec_xix<IY>(); NEXT; }
2126  case 0x36: { II ii = ld_xix_byte<IY>(); NEXT; }
2127 
2128  case 0x44: { II ii = ld_R_R<B,IYH,T::CC_DD>(); NEXT; }
2129  case 0x45: { II ii = ld_R_R<B,IYL,T::CC_DD>(); NEXT; }
2130  case 0x4c: { II ii = ld_R_R<C,IYH,T::CC_DD>(); NEXT; }
2131  case 0x4d: { II ii = ld_R_R<C,IYL,T::CC_DD>(); NEXT; }
2132  case 0x54: { II ii = ld_R_R<D,IYH,T::CC_DD>(); NEXT; }
2133  case 0x55: { II ii = ld_R_R<D,IYL,T::CC_DD>(); NEXT; }
2134  case 0x5c: { II ii = ld_R_R<E,IYH,T::CC_DD>(); NEXT; }
2135  case 0x5d: { II ii = ld_R_R<E,IYL,T::CC_DD>(); NEXT; }
2136  case 0x7c: { II ii = ld_R_R<A,IYH,T::CC_DD>(); NEXT; }
2137  case 0x7d: { II ii = ld_R_R<A,IYL,T::CC_DD>(); NEXT; }
2138  case 0x60: { II ii = ld_R_R<IYH,B,T::CC_DD>(); NEXT; }
2139  case 0x61: { II ii = ld_R_R<IYH,C,T::CC_DD>(); NEXT; }
2140  case 0x62: { II ii = ld_R_R<IYH,D,T::CC_DD>(); NEXT; }
2141  case 0x63: { II ii = ld_R_R<IYH,E,T::CC_DD>(); NEXT; }
2142  case 0x65: { II ii = ld_R_R<IYH,IYL,T::CC_DD>(); NEXT; }
2143  case 0x67: { II ii = ld_R_R<IYH,A,T::CC_DD>(); NEXT; }
2144  case 0x68: { II ii = ld_R_R<IYL,B,T::CC_DD>(); NEXT; }
2145  case 0x69: { II ii = ld_R_R<IYL,C,T::CC_DD>(); NEXT; }
2146  case 0x6a: { II ii = ld_R_R<IYL,D,T::CC_DD>(); NEXT; }
2147  case 0x6b: { II ii = ld_R_R<IYL,E,T::CC_DD>(); NEXT; }
2148  case 0x6c: { II ii = ld_R_R<IYL,IYH,T::CC_DD>(); NEXT; }
2149  case 0x6f: { II ii = ld_R_R<IYL,A,T::CC_DD>(); NEXT; }
2150  case 0x70: { II ii = ld_xix_R<IY,B>(); NEXT; }
2151  case 0x71: { II ii = ld_xix_R<IY,C>(); NEXT; }
2152  case 0x72: { II ii = ld_xix_R<IY,D>(); NEXT; }
2153  case 0x73: { II ii = ld_xix_R<IY,E>(); NEXT; }
2154  case 0x74: { II ii = ld_xix_R<IY,H>(); NEXT; }
2155  case 0x75: { II ii = ld_xix_R<IY,L>(); NEXT; }
2156  case 0x77: { II ii = ld_xix_R<IY,A>(); NEXT; }
2157  case 0x46: { II ii = ld_R_xix<B,IY>(); NEXT; }
2158  case 0x4e: { II ii = ld_R_xix<C,IY>(); NEXT; }
2159  case 0x56: { II ii = ld_R_xix<D,IY>(); NEXT; }
2160  case 0x5e: { II ii = ld_R_xix<E,IY>(); NEXT; }
2161  case 0x66: { II ii = ld_R_xix<H,IY>(); NEXT; }
2162  case 0x6e: { II ii = ld_R_xix<L,IY>(); NEXT; }
2163  case 0x7e: { II ii = ld_R_xix<A,IY>(); NEXT; }
2164 
2165  case 0x84: { II ii = add_a_R<IYH,T::CC_DD>(); NEXT; }
2166  case 0x85: { II ii = add_a_R<IYL,T::CC_DD>(); NEXT; }
2167  case 0x86: { II ii = add_a_xix<IY>(); NEXT; }
2168  case 0x8c: { II ii = adc_a_R<IYH,T::CC_DD>(); NEXT; }
2169  case 0x8d: { II ii = adc_a_R<IYL,T::CC_DD>(); NEXT; }
2170  case 0x8e: { II ii = adc_a_xix<IY>(); NEXT; }
2171  case 0x94: { II ii = sub_R<IYH,T::CC_DD>(); NEXT; }
2172  case 0x95: { II ii = sub_R<IYL,T::CC_DD>(); NEXT; }
2173  case 0x96: { II ii = sub_xix<IY>(); NEXT; }
2174  case 0x9c: { II ii = sbc_a_R<IYH,T::CC_DD>(); NEXT; }
2175  case 0x9d: { II ii = sbc_a_R<IYL,T::CC_DD>(); NEXT; }
2176  case 0x9e: { II ii = sbc_a_xix<IY>(); NEXT; }
2177  case 0xa4: { II ii = and_R<IYH,T::CC_DD>(); NEXT; }
2178  case 0xa5: { II ii = and_R<IYL,T::CC_DD>(); NEXT; }
2179  case 0xa6: { II ii = and_xix<IY>(); NEXT; }
2180  case 0xac: { II ii = xor_R<IYH,T::CC_DD>(); NEXT; }
2181  case 0xad: { II ii = xor_R<IYL,T::CC_DD>(); NEXT; }
2182  case 0xae: { II ii = xor_xix<IY>(); NEXT; }
2183  case 0xb4: { II ii = or_R<IYH,T::CC_DD>(); NEXT; }
2184  case 0xb5: { II ii = or_R<IYL,T::CC_DD>(); NEXT; }
2185  case 0xb6: { II ii = or_xix<IY>(); NEXT; }
2186  case 0xbc: { II ii = cp_R<IYH,T::CC_DD>(); NEXT; }
2187  case 0xbd: { II ii = cp_R<IYL,T::CC_DD>(); NEXT; }
2188  case 0xbe: { II ii = cp_xix<IY>(); NEXT; }
2189 
2190  case 0xe1: { II ii = pop_SS <IY,T::CC_DD>(); NEXT; }
2191  case 0xe5: { II ii = push_SS<IY,T::CC_DD>(); NEXT; }
2192  case 0xe3: { II ii = ex_xsp_SS<IY,T::CC_DD>(); NEXT; }
2193  case 0xe9: { II ii = jp_SS<IY,T::CC_DD>(); NEXT; }
2194  case 0xf9: { II ii = ld_sp_SS<IY,T::CC_DD>(); NEXT; }
2195  case 0xcb: ixy = getIY(); goto xx_cb;
2196  case 0xdd: T::add(T::CC_DD); goto opDD_2;
2197  case 0xfd: T::add(T::CC_DD); goto opFD_2;
2198  default: UNREACHABLE; return;
2199  }
2200 }
2201 #ifndef USE_COMPUTED_GOTO
2202  default: UNREACHABLE; return;
2203 }
2204 #endif
2205 
2206 xx_cb: {
2207  unsigned tmp = RD_WORD_PC<1>(T::CC_DD + T::CC_DD_CB);
2208  int8_t ofst = tmp & 0xFF;
2209  unsigned addr = (ixy + ofst) & 0xFFFF;
2210  byte xxcb_opcode = tmp >> 8;
2211  switch (xxcb_opcode) {
2212  case 0x00: { II ii = rlc_xix_R<B>(addr); NEXT; }
2213  case 0x01: { II ii = rlc_xix_R<C>(addr); NEXT; }
2214  case 0x02: { II ii = rlc_xix_R<D>(addr); NEXT; }
2215  case 0x03: { II ii = rlc_xix_R<E>(addr); NEXT; }
2216  case 0x04: { II ii = rlc_xix_R<H>(addr); NEXT; }
2217  case 0x05: { II ii = rlc_xix_R<L>(addr); NEXT; }
2218  case 0x06: { II ii = rlc_xix_R<DUMMY>(addr); NEXT; }
2219  case 0x07: { II ii = rlc_xix_R<A>(addr); NEXT; }
2220  case 0x08: { II ii = rrc_xix_R<B>(addr); NEXT; }
2221  case 0x09: { II ii = rrc_xix_R<C>(addr); NEXT; }
2222  case 0x0a: { II ii = rrc_xix_R<D>(addr); NEXT; }
2223  case 0x0b: { II ii = rrc_xix_R<E>(addr); NEXT; }
2224  case 0x0c: { II ii = rrc_xix_R<H>(addr); NEXT; }
2225  case 0x0d: { II ii = rrc_xix_R<L>(addr); NEXT; }
2226  case 0x0e: { II ii = rrc_xix_R<DUMMY>(addr); NEXT; }
2227  case 0x0f: { II ii = rrc_xix_R<A>(addr); NEXT; }
2228  case 0x10: { II ii = rl_xix_R<B>(addr); NEXT; }
2229  case 0x11: { II ii = rl_xix_R<C>(addr); NEXT; }
2230  case 0x12: { II ii = rl_xix_R<D>(addr); NEXT; }
2231  case 0x13: { II ii = rl_xix_R<E>(addr); NEXT; }
2232  case 0x14: { II ii = rl_xix_R<H>(addr); NEXT; }
2233  case 0x15: { II ii = rl_xix_R<L>(addr); NEXT; }
2234  case 0x16: { II ii = rl_xix_R<DUMMY>(addr); NEXT; }
2235  case 0x17: { II ii = rl_xix_R<A>(addr); NEXT; }
2236  case 0x18: { II ii = rr_xix_R<B>(addr); NEXT; }
2237  case 0x19: { II ii = rr_xix_R<C>(addr); NEXT; }
2238  case 0x1a: { II ii = rr_xix_R<D>(addr); NEXT; }
2239  case 0x1b: { II ii = rr_xix_R<E>(addr); NEXT; }
2240  case 0x1c: { II ii = rr_xix_R<H>(addr); NEXT; }
2241  case 0x1d: { II ii = rr_xix_R<L>(addr); NEXT; }
2242  case 0x1e: { II ii = rr_xix_R<DUMMY>(addr); NEXT; }
2243  case 0x1f: { II ii = rr_xix_R<A>(addr); NEXT; }
2244  case 0x20: { II ii = sla_xix_R<B>(addr); NEXT; }
2245  case 0x21: { II ii = sla_xix_R<C>(addr); NEXT; }
2246  case 0x22: { II ii = sla_xix_R<D>(addr); NEXT; }
2247  case 0x23: { II ii = sla_xix_R<E>(addr); NEXT; }
2248  case 0x24: { II ii = sla_xix_R<H>(addr); NEXT; }
2249  case 0x25: { II ii = sla_xix_R<L>(addr); NEXT; }
2250  case 0x26: { II ii = sla_xix_R<DUMMY>(addr); NEXT; }
2251  case 0x27: { II ii = sla_xix_R<A>(addr); NEXT; }
2252  case 0x28: { II ii = sra_xix_R<B>(addr); NEXT; }
2253  case 0x29: { II ii = sra_xix_R<C>(addr); NEXT; }
2254  case 0x2a: { II ii = sra_xix_R<D>(addr); NEXT; }
2255  case 0x2b: { II ii = sra_xix_R<E>(addr); NEXT; }
2256  case 0x2c: { II ii = sra_xix_R<H>(addr); NEXT; }
2257  case 0x2d: { II ii = sra_xix_R<L>(addr); NEXT; }
2258  case 0x2e: { II ii = sra_xix_R<DUMMY>(addr); NEXT; }
2259  case 0x2f: { II ii = sra_xix_R<A>(addr); NEXT; }
2260  case 0x30: { II ii = T::isR800() ? sll2() : sll_xix_R<B>(addr); NEXT; }
2261  case 0x31: { II ii = T::isR800() ? sll2() : sll_xix_R<C>(addr); NEXT; }
2262  case 0x32: { II ii = T::isR800() ? sll2() : sll_xix_R<D>(addr); NEXT; }
2263  case 0x33: { II ii = T::isR800() ? sll2() : sll_xix_R<E>(addr); NEXT; }
2264  case 0x34: { II ii = T::isR800() ? sll2() : sll_xix_R<H>(addr); NEXT; }
2265  case 0x35: { II ii = T::isR800() ? sll2() : sll_xix_R<L>(addr); NEXT; }
2266  case 0x36: { II ii = T::isR800() ? sll2() : sll_xix_R<DUMMY>(addr); NEXT; }
2267  case 0x37: { II ii = T::isR800() ? sll2() : sll_xix_R<A>(addr); NEXT; }
2268  case 0x38: { II ii = srl_xix_R<B>(addr); NEXT; }
2269  case 0x39: { II ii = srl_xix_R<C>(addr); NEXT; }
2270  case 0x3a: { II ii = srl_xix_R<D>(addr); NEXT; }
2271  case 0x3b: { II ii = srl_xix_R<E>(addr); NEXT; }
2272  case 0x3c: { II ii = srl_xix_R<H>(addr); NEXT; }
2273  case 0x3d: { II ii = srl_xix_R<L>(addr); NEXT; }
2274  case 0x3e: { II ii = srl_xix_R<DUMMY>(addr); NEXT; }
2275  case 0x3f: { II ii = srl_xix_R<A>(addr); NEXT; }
2276 
2277  case 0x40: case 0x41: case 0x42: case 0x43:
2278  case 0x44: case 0x45: case 0x46: case 0x47:
2279  { II ii = bit_N_xix<0>(addr); NEXT; }
2280  case 0x48: case 0x49: case 0x4a: case 0x4b:
2281  case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2282  { II ii = bit_N_xix<1>(addr); NEXT; }
2283  case 0x50: case 0x51: case 0x52: case 0x53:
2284  case 0x54: case 0x55: case 0x56: case 0x57:
2285  { II ii = bit_N_xix<2>(addr); NEXT; }
2286  case 0x58: case 0x59: case 0x5a: case 0x5b:
2287  case 0x5c: case 0x5d: case 0x5e: case 0x5f:
2288  { II ii = bit_N_xix<3>(addr); NEXT; }
2289  case 0x60: case 0x61: case 0x62: case 0x63:
2290  case 0x64: case 0x65: case 0x66: case 0x67:
2291  { II ii = bit_N_xix<4>(addr); NEXT; }
2292  case 0x68: case 0x69: case 0x6a: case 0x6b:
2293  case 0x6c: case 0x6d: case 0x6e: case 0x6f:
2294  { II ii = bit_N_xix<5>(addr); NEXT; }
2295  case 0x70: case 0x71: case 0x72: case 0x73:
2296  case 0x74: case 0x75: case 0x76: case 0x77:
2297  { II ii = bit_N_xix<6>(addr); NEXT; }
2298  case 0x78: case 0x79: case 0x7a: case 0x7b:
2299  case 0x7c: case 0x7d: case 0x7e: case 0x7f:
2300  { II ii = bit_N_xix<7>(addr); NEXT; }
2301 
2302  case 0x80: { II ii = res_N_xix_R<0,B>(addr); NEXT; }
2303  case 0x81: { II ii = res_N_xix_R<0,C>(addr); NEXT; }
2304  case 0x82: { II ii = res_N_xix_R<0,D>(addr); NEXT; }
2305  case 0x83: { II ii = res_N_xix_R<0,E>(addr); NEXT; }
2306  case 0x84: { II ii = res_N_xix_R<0,H>(addr); NEXT; }
2307  case 0x85: { II ii = res_N_xix_R<0,L>(addr); NEXT; }
2308  case 0x87: { II ii = res_N_xix_R<0,A>(addr); NEXT; }
2309  case 0x88: { II ii = res_N_xix_R<1,B>(addr); NEXT; }
2310  case 0x89: { II ii = res_N_xix_R<1,C>(addr); NEXT; }
2311  case 0x8a: { II ii = res_N_xix_R<1,D>(addr); NEXT; }
2312  case 0x8b: { II ii = res_N_xix_R<1,E>(addr); NEXT; }
2313  case 0x8c: { II ii = res_N_xix_R<1,H>(addr); NEXT; }
2314  case 0x8d: { II ii = res_N_xix_R<1,L>(addr); NEXT; }
2315  case 0x8f: { II ii = res_N_xix_R<1,A>(addr); NEXT; }
2316  case 0x90: { II ii = res_N_xix_R<2,B>(addr); NEXT; }
2317  case 0x91: { II ii = res_N_xix_R<2,C>(addr); NEXT; }
2318  case 0x92: { II ii = res_N_xix_R<2,D>(addr); NEXT; }
2319  case 0x93: { II ii = res_N_xix_R<2,E>(addr); NEXT; }
2320  case 0x94: { II ii = res_N_xix_R<2,H>(addr); NEXT; }
2321  case 0x95: { II ii = res_N_xix_R<2,L>(addr); NEXT; }
2322  case 0x97: { II ii = res_N_xix_R<2,A>(addr); NEXT; }
2323  case 0x98: { II ii = res_N_xix_R<3,B>(addr); NEXT; }
2324  case 0x99: { II ii = res_N_xix_R<3,C>(addr); NEXT; }
2325  case 0x9a: { II ii = res_N_xix_R<3,D>(addr); NEXT; }
2326  case 0x9b: { II ii = res_N_xix_R<3,E>(addr); NEXT; }
2327  case 0x9c: { II ii = res_N_xix_R<3,H>(addr); NEXT; }
2328  case 0x9d: { II ii = res_N_xix_R<3,L>(addr); NEXT; }
2329  case 0x9f: { II ii = res_N_xix_R<3,A>(addr); NEXT; }
2330  case 0xa0: { II ii = res_N_xix_R<4,B>(addr); NEXT; }
2331  case 0xa1: { II ii = res_N_xix_R<4,C>(addr); NEXT; }
2332  case 0xa2: { II ii = res_N_xix_R<4,D>(addr); NEXT; }
2333  case 0xa3: { II ii = res_N_xix_R<4,E>(addr); NEXT; }
2334  case 0xa4: { II ii = res_N_xix_R<4,H>(addr); NEXT; }
2335  case 0xa5: { II ii = res_N_xix_R<4,L>(addr); NEXT; }
2336  case 0xa7: { II ii = res_N_xix_R<4,A>(addr); NEXT; }
2337  case 0xa8: { II ii = res_N_xix_R<5,B>(addr); NEXT; }
2338  case 0xa9: { II ii = res_N_xix_R<5,C>(addr); NEXT; }
2339  case 0xaa: { II ii = res_N_xix_R<5,D>(addr); NEXT; }
2340  case 0xab: { II ii = res_N_xix_R<5,E>(addr); NEXT; }
2341  case 0xac: { II ii = res_N_xix_R<5,H>(addr); NEXT; }
2342  case 0xad: { II ii = res_N_xix_R<5,L>(addr); NEXT; }
2343  case 0xaf: { II ii = res_N_xix_R<5,A>(addr); NEXT; }
2344  case 0xb0: { II ii = res_N_xix_R<6,B>(addr); NEXT; }
2345  case 0xb1: { II ii = res_N_xix_R<6,C>(addr); NEXT; }
2346  case 0xb2: { II ii = res_N_xix_R<6,D>(addr); NEXT; }
2347  case 0xb3: { II ii = res_N_xix_R<6,E>(addr); NEXT; }
2348  case 0xb4: { II ii = res_N_xix_R<6,H>(addr); NEXT; }
2349  case 0xb5: { II ii = res_N_xix_R<6,L>(addr); NEXT; }
2350  case 0xb7: { II ii = res_N_xix_R<6,A>(addr); NEXT; }
2351  case 0xb8: { II ii = res_N_xix_R<7,B>(addr); NEXT; }
2352  case 0xb9: { II ii = res_N_xix_R<7,C>(addr); NEXT; }
2353  case 0xba: { II ii = res_N_xix_R<7,D>(addr); NEXT; }
2354  case 0xbb: { II ii = res_N_xix_R<7,E>(addr); NEXT; }
2355  case 0xbc: { II ii = res_N_xix_R<7,H>(addr); NEXT; }
2356  case 0xbd: { II ii = res_N_xix_R<7,L>(addr); NEXT; }
2357  case 0xbf: { II ii = res_N_xix_R<7,A>(addr); NEXT; }
2358  case 0x86: { II ii = res_N_xix_R<0,DUMMY>(addr); NEXT; }
2359  case 0x8e: { II ii = res_N_xix_R<1,DUMMY>(addr); NEXT; }
2360  case 0x96: { II ii = res_N_xix_R<2,DUMMY>(addr); NEXT; }
2361  case 0x9e: { II ii = res_N_xix_R<3,DUMMY>(addr); NEXT; }
2362  case 0xa6: { II ii = res_N_xix_R<4,DUMMY>(addr); NEXT; }
2363  case 0xae: { II ii = res_N_xix_R<5,DUMMY>(addr); NEXT; }
2364  case 0xb6: { II ii = res_N_xix_R<6,DUMMY>(addr); NEXT; }
2365  case 0xbe: { II ii = res_N_xix_R<7,DUMMY>(addr); NEXT; }
2366 
2367  case 0xc0: { II ii = set_N_xix_R<0,B>(addr); NEXT; }
2368  case 0xc1: { II ii = set_N_xix_R<0,C>(addr); NEXT; }
2369  case 0xc2: { II ii = set_N_xix_R<0,D>(addr); NEXT; }
2370  case 0xc3: { II ii = set_N_xix_R<0,E>(addr); NEXT; }
2371  case 0xc4: { II ii = set_N_xix_R<0,H>(addr); NEXT; }
2372  case 0xc5: { II ii = set_N_xix_R<0,L>(addr); NEXT; }
2373  case 0xc7: { II ii = set_N_xix_R<0,A>(addr); NEXT; }
2374  case 0xc8: { II ii = set_N_xix_R<1,B>(addr); NEXT; }
2375  case 0xc9: { II ii = set_N_xix_R<1,C>(addr); NEXT; }
2376  case 0xca: { II ii = set_N_xix_R<1,D>(addr); NEXT; }
2377  case 0xcb: { II ii = set_N_xix_R<1,E>(addr); NEXT; }
2378  case 0xcc: { II ii = set_N_xix_R<1,H>(addr); NEXT; }
2379  case 0xcd: { II ii = set_N_xix_R<1,L>(addr); NEXT; }
2380  case 0xcf: { II ii = set_N_xix_R<1,A>(addr); NEXT; }
2381  case 0xd0: { II ii = set_N_xix_R<2,B>(addr); NEXT; }
2382  case 0xd1: { II ii = set_N_xix_R<2,C>(addr); NEXT; }
2383  case 0xd2: { II ii = set_N_xix_R<2,D>(addr); NEXT; }
2384  case 0xd3: { II ii = set_N_xix_R<2,E>(addr); NEXT; }
2385  case 0xd4: { II ii = set_N_xix_R<2,H>(addr); NEXT; }
2386  case 0xd5: { II ii = set_N_xix_R<2,L>(addr); NEXT; }
2387  case 0xd7: { II ii = set_N_xix_R<2,A>(addr); NEXT; }
2388  case 0xd8: { II ii = set_N_xix_R<3,B>(addr); NEXT; }
2389  case 0xd9: { II ii = set_N_xix_R<3,C>(addr); NEXT; }
2390  case 0xda: { II ii = set_N_xix_R<3,D>(addr); NEXT; }
2391  case 0xdb: { II ii = set_N_xix_R<3,E>(addr); NEXT; }
2392  case 0xdc: { II ii = set_N_xix_R<3,H>(addr); NEXT; }
2393  case 0xdd: { II ii = set_N_xix_R<3,L>(addr); NEXT; }
2394  case 0xdf: { II ii = set_N_xix_R<3,A>(addr); NEXT; }
2395  case 0xe0: { II ii = set_N_xix_R<4,B>(addr); NEXT; }
2396  case 0xe1: { II ii = set_N_xix_R<4,C>(addr); NEXT; }
2397  case 0xe2: { II ii = set_N_xix_R<4,D>(addr); NEXT; }
2398  case 0xe3: { II ii = set_N_xix_R<4,E>(addr); NEXT; }
2399  case 0xe4: { II ii = set_N_xix_R<4,H>(addr); NEXT; }
2400  case 0xe5: { II ii = set_N_xix_R<4,L>(addr); NEXT; }
2401  case 0xe7: { II ii = set_N_xix_R<4,A>(addr); NEXT; }
2402  case 0xe8: { II ii = set_N_xix_R<5,B>(addr); NEXT; }
2403  case 0xe9: { II ii = set_N_xix_R<5,C>(addr); NEXT; }
2404  case 0xea: { II ii = set_N_xix_R<5,D>(addr); NEXT; }
2405  case 0xeb: { II ii = set_N_xix_R<5,E>(addr); NEXT; }
2406  case 0xec: { II ii = set_N_xix_R<5,H>(addr); NEXT; }
2407  case 0xed: { II ii = set_N_xix_R<5,L>(addr); NEXT; }
2408  case 0xef: { II ii = set_N_xix_R<5,A>(addr); NEXT; }
2409  case 0xf0: { II ii = set_N_xix_R<6,B>(addr); NEXT; }
2410  case 0xf1: { II ii = set_N_xix_R<6,C>(addr); NEXT; }
2411  case 0xf2: { II ii = set_N_xix_R<6,D>(addr); NEXT; }
2412  case 0xf3: { II ii = set_N_xix_R<6,E>(addr); NEXT; }
2413  case 0xf4: { II ii = set_N_xix_R<6,H>(addr); NEXT; }
2414  case 0xf5: { II ii = set_N_xix_R<6,L>(addr); NEXT; }
2415  case 0xf7: { II ii = set_N_xix_R<6,A>(addr); NEXT; }
2416  case 0xf8: { II ii = set_N_xix_R<7,B>(addr); NEXT; }
2417  case 0xf9: { II ii = set_N_xix_R<7,C>(addr); NEXT; }
2418  case 0xfa: { II ii = set_N_xix_R<7,D>(addr); NEXT; }
2419  case 0xfb: { II ii = set_N_xix_R<7,E>(addr); NEXT; }
2420  case 0xfc: { II ii = set_N_xix_R<7,H>(addr); NEXT; }
2421  case 0xfd: { II ii = set_N_xix_R<7,L>(addr); NEXT; }
2422  case 0xff: { II ii = set_N_xix_R<7,A>(addr); NEXT; }
2423  case 0xc6: { II ii = set_N_xix_R<0,DUMMY>(addr); NEXT; }
2424  case 0xce: { II ii = set_N_xix_R<1,DUMMY>(addr); NEXT; }
2425  case 0xd6: { II ii = set_N_xix_R<2,DUMMY>(addr); NEXT; }
2426  case 0xde: { II ii = set_N_xix_R<3,DUMMY>(addr); NEXT; }
2427  case 0xe6: { II ii = set_N_xix_R<4,DUMMY>(addr); NEXT; }
2428  case 0xee: { II ii = set_N_xix_R<5,DUMMY>(addr); NEXT; }
2429  case 0xf6: { II ii = set_N_xix_R<6,DUMMY>(addr); NEXT; }
2430  case 0xfe: { II ii = set_N_xix_R<7,DUMMY>(addr); NEXT; }
2431  default: UNREACHABLE;
2432  }
2433  }
2434 }
2435 
2436 template<class T> inline void CPUCore<T>::cpuTracePre()
2437 {
2438  start_pc = getPC();
2439 }
2440 template<class T> inline void CPUCore<T>::cpuTracePost()
2441 {
2442  if (unlikely(tracingEnabled)) {
2443  cpuTracePost_slow();
2444  }
2445 }
2446 template<class T> void CPUCore<T>::cpuTracePost_slow()
2447 {
2448  byte opbuf[4];
2449  string dasmOutput;
2450  dasm(*interface, start_pc, opbuf, dasmOutput, T::getTimeFast());
2451  std::cout << strCat(hex_string<4>(start_pc),
2452  " : ", dasmOutput,
2453  " AF=", hex_string<4>(getAF()),
2454  " BC=", hex_string<4>(getBC()),
2455  " DE=", hex_string<4>(getDE()),
2456  " HL=", hex_string<4>(getHL()),
2457  " IX=", hex_string<4>(getIX()),
2458  " IY=", hex_string<4>(getIY()),
2459  " SP=", hex_string<4>(getSP()),
2460  '\n')
2461  << std::flush;
2462 }
2463 
2464 template<class T> ExecIRQ CPUCore<T>::getExecIRQ() const
2465 {
2466  if (unlikely(nmiEdge)) return ExecIRQ::NMI;
2467  if (unlikely(IRQStatus && getIFF1() && !prevWasEI())) return ExecIRQ::IRQ;
2468  return ExecIRQ::NONE;
2469 }
2470 
2471 template<class T> void CPUCore<T>::executeSlow(ExecIRQ execIRQ)
2472 {
2473  if (unlikely(execIRQ == ExecIRQ::NMI)) {
2474  nmiEdge = false;
2475  nmi(); // NMI occured
2476  } else if (unlikely(execIRQ == ExecIRQ::IRQ)) {
2477  // normal interrupt
2478  if (unlikely(prevWasLDAI())) {
2479  // HACK!!!
2480  // The 'ld a,i' or 'ld a,r' instruction copies the IFF2
2481  // bit to the V flag. Though when the Z80 accepts an
2482  // IRQ directly after this instruction, the V flag is 0
2483  // (instead of the expected value 1). This can probably
2484  // be explained if you look at the pipeline of the Z80.
2485  // But for speed reasons we implement it here as a
2486  // fix-up (a hack) in the IRQ routine. This behaviour
2487  // is actually a bug in the Z80.
2488  // Thanks to n_n for reporting this behaviour. I think
2489  // this was discovered by GuyveR800. Also thanks to
2490  // n_n for writing a test program that demonstrates
2491  // this quirk.
2492  // I also wrote a test program that demonstrates this
2493  // behaviour is the same whether 'ld a,i' is preceded
2494  // by a 'ei' instruction or not (so it's not caused by
2495  // the 'delayed IRQ acceptance of ei').
2496  assert(getF() & V_FLAG);
2497  setF(getF() & ~V_FLAG);
2498  }
2499  IRQAccept.signal();
2500  switch (getIM()) {
2501  case 0: irq0();
2502  break;
2503  case 1: irq1();
2504  break;
2505  case 2: irq2();
2506  break;
2507  default:
2508  UNREACHABLE;
2509  }
2510  } else if (unlikely(getHALT())) {
2511  // in halt mode
2512  incR(T::advanceHalt(T::haltStates(), scheduler.getNext()));
2513  setSlowInstructions();
2514  } else {
2515  cpuTracePre();
2516  assert(T::limitReached()); // we want only one instruction
2517  executeInstructions();
2518  endInstruction();
2519 
2520  if (T::isR800()) {
2521  if (unlikely(prev2WasCall()) && likely(!prevWasPopRet())) {
2522  // On R800 a CALL or RST instruction not _immediately_
2523  // followed by a (single-byte) POP or RET instruction
2524  // causes an extra cycle in that following instruction.
2525  // No idea why yet. See doc/internal/r800-call.txt
2526  // for more information.
2527  //
2528  // TODO this implementation adds the extra cycle at
2529  // the end of the instruction POP/RET. It is not known
2530  // where in the instruction the real R800 adds this cycle.
2531  T::add(1);
2532  }
2533  }
2534  cpuTracePost();
2535  }
2536 }
2537 
2538 template<class T> void CPUCore<T>::execute(bool fastForward)
2539 {
2540  // In fast-forward mode, breakpoints, watchpoints or debug condtions
2541  // won't trigger. It is possible we already are in break mode, but
2542  // break is ignored in fast-forward mode.
2543  assert(fastForward || !interface->isBreaked());
2544  if (fastForward) {
2545  interface->setFastForward(true);
2546  }
2547  execute2(fastForward);
2548  interface->setFastForward(false);
2549 }
2550 
2551 template<class T> void CPUCore<T>::execute2(bool fastForward)
2552 {
2553  // note: Don't use getTimeFast() here, because 'once in a while' we
2554  // need to CPUClock::sync() to avoid overflow.
2555  // Should be done at least once per second (approx). So only
2556  // once in this method is enough.
2557  scheduler.schedule(T::getTime());
2558  setSlowInstructions();
2559 
2560  // Note: we call scheduler _after_ executing the instruction and before
2561  // deciding between executeFast() and executeSlow() (because a
2562  // SyncPoint could set an IRQ and then we must choose executeSlow())
2563  if (fastForward ||
2564  (!interface->anyBreakPoints() && !tracingEnabled)) {
2565  // fast path, no breakpoints, no tracing
2566  do {
2567  if (slowInstructions) {
2568  --slowInstructions;
2569  executeSlow(getExecIRQ());
2570  scheduler.schedule(T::getTimeFast());
2571  } else {
2572  while (slowInstructions == 0) {
2573  T::enableLimit(); // does CPUClock::sync()
2574  if (likely(!T::limitReached())) {
2575  // multiple instructions
2576  executeInstructions();
2577  // note: pipeline only shifted one
2578  // step for multiple instructions
2579  endInstruction();
2580  }
2581  scheduler.schedule(T::getTimeFast());
2582  if (needExitCPULoop()) return;
2583  }
2584  }
2585  } while (!needExitCPULoop());
2586  } else {
2587  do {
2588  if (slowInstructions == 0) {
2589  cpuTracePre();
2590  assert(T::limitReached()); // only one instruction
2591  executeInstructions();
2592  endInstruction();
2593  cpuTracePost();
2594  } else {
2595  --slowInstructions;
2596  executeSlow(getExecIRQ());
2597  }
2598  // Don't use getTimeFast() here, we need a call to
2599  // CPUClock::sync() 'once in a while'. (During a
2600  // reverse fast-forward this wasn't always the case).
2601  scheduler.schedule(T::getTime());
2602 
2603  // Only check for breakpoints when we're not about to jump to an IRQ handler.
2604  //
2605  // This fixes the following problem reported by Grauw:
2606  //
2607  // I found a breakpoints bug: sometimes a breakpoint gets hit twice even
2608  // though the code is executed once. This manifests itself in my profiler
2609  // as an imbalance between section begin- and end-calls.
2610  //
2611  // Turns out this occurs when an interrupt occurs exactly on the line of
2612  // the breakpoint, then the breakpoint gets hit before immediately going
2613  // to the ISR, as well as when returning from the ISR.
2614  //
2615  // The IRQ is handled by the Z80 at the end of an instruction. So it
2616  // should change the PC before the next instruction is fetched and the
2617  // breakpoints should be evaluated during instruction fetch.
2618  //
2619  // I think Grauw's analysis is correct. Though for performance reasons we
2620  // don't emulate the Z80 like that: we don't check for IRQs at the end of
2621  // every instruction. In the openMSX emulation model, we can only enter an
2622  // ISR:
2623  // - (One instruction after) switching from DI to EI mode.
2624  // - After emulating device code. This can be:
2625  // * When the Z80 communicated with the device (IO or memory mapped IO).
2626  // * The device had set a synchronization point.
2627  // In all cases disableLimit() gets called which will cause
2628  // limitReached() to return true (and possibly slowInstructions to be > 0).
2629  // So after most emulated Z80 instructions there can't be a pending IRQ, so
2630  // checking for it is wasteful. Also synchronization points are handled
2631  // between emulated Z80 instructions, that means me must check for pending
2632  // IRQs at the start (instead of end) of an instruction.
2633  //
2634  auto execIRQ = getExecIRQ();
2635  if ((execIRQ == ExecIRQ::NONE) &&
2636  interface->checkBreakPoints(getPC(), motherboard)) {
2637  assert(interface->isBreaked());
2638  break;
2639  }
2640  } while (!needExitCPULoop());
2641  }
2642 }
2643 
2644 template<class T> template<Reg8 R8> ALWAYS_INLINE byte CPUCore<T>::get8() const {
2645  if (R8 == A) { return getA(); }
2646  else if (R8 == F) { return getF(); }
2647  else if (R8 == B) { return getB(); }
2648  else if (R8 == C) { return getC(); }
2649  else if (R8 == D) { return getD(); }
2650  else if (R8 == E) { return getE(); }
2651  else if (R8 == H) { return getH(); }
2652  else if (R8 == L) { return getL(); }
2653  else if (R8 == IXH) { return getIXh(); }
2654  else if (R8 == IXL) { return getIXl(); }
2655  else if (R8 == IYH) { return getIYh(); }
2656  else if (R8 == IYL) { return getIYl(); }
2657  else if (R8 == REG_I) { return getI(); }
2658  else if (R8 == REG_R) { return getR(); }
2659  else if (R8 == DUMMY) { return 0; }
2660  else { UNREACHABLE; return 0; }
2661 }
2662 template<class T> template<Reg16 R16> ALWAYS_INLINE unsigned CPUCore<T>::get16() const {
2663  if (R16 == AF) { return getAF(); }
2664  else if (R16 == BC) { return getBC(); }
2665  else if (R16 == DE) { return getDE(); }
2666  else if (R16 == HL) { return getHL(); }
2667  else if (R16 == IX) { return getIX(); }
2668  else if (R16 == IY) { return getIY(); }
2669  else if (R16 == SP) { return getSP(); }
2670  else { UNREACHABLE; return 0; }
2671 }
2672 template<class T> template<Reg8 R8> ALWAYS_INLINE void CPUCore<T>::set8(byte x) {
2673  if (R8 == A) { setA(x); }
2674  else if (R8 == F) { setF(x); }
2675  else if (R8 == B) { setB(x); }
2676  else if (R8 == C) { setC(x); }
2677  else if (R8 == D) { setD(x); }
2678  else if (R8 == E) { setE(x); }
2679  else if (R8 == H) { setH(x); }
2680  else if (R8 == L) { setL(x); }
2681  else if (R8 == IXH) { setIXh(x); }
2682  else if (R8 == IXL) { setIXl(x); }
2683  else if (R8 == IYH) { setIYh(x); }
2684  else if (R8 == IYL) { setIYl(x); }
2685  else if (R8 == REG_I) { setI(x); }
2686  else if (R8 == REG_R) { setR(x); }
2687  else if (R8 == DUMMY) { /* nothing */ }
2688  else { UNREACHABLE; }
2689 }
2690 template<class T> template<Reg16 R16> ALWAYS_INLINE void CPUCore<T>::set16(unsigned x) {
2691  if (R16 == AF) { setAF(x); }
2692  else if (R16 == BC) { setBC(x); }
2693  else if (R16 == DE) { setDE(x); }
2694  else if (R16 == HL) { setHL(x); }
2695  else if (R16 == IX) { setIX(x); }
2696  else if (R16 == IY) { setIY(x); }
2697  else if (R16 == SP) { setSP(x); }
2698  else { UNREACHABLE; }
2699 }
2700 
2701 // LD r,r
2702 template<class T> template<Reg8 DST, Reg8 SRC, int EE> II CPUCore<T>::ld_R_R() {
2703  set8<DST>(get8<SRC>()); return {1, T::CC_LD_R_R + EE};
2704 }
2705 
2706 // LD SP,ss
2707 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ld_sp_SS() {
2708  setSP(get16<REG>()); return {1, T::CC_LD_SP_HL + EE};
2709 }
2710 
2711 // LD (ss),a
2712 template<class T> template<Reg16 REG> II CPUCore<T>::ld_SS_a() {
2713  T::setMemPtr((getA() << 8) | ((get16<REG>() + 1) & 0xFF));
2714  WRMEM(get16<REG>(), getA(), T::CC_LD_SS_A_1);
2715  return {1, T::CC_LD_SS_A};
2716 }
2717 
2718 // LD (HL),r
2719 template<class T> template<Reg8 SRC> II CPUCore<T>::ld_xhl_R() {
2720  WRMEM(getHL(), get8<SRC>(), T::CC_LD_HL_R_1);
2721  return {1, T::CC_LD_HL_R};
2722 }
2723 
2724 // LD (IXY+e),r
2725 template<class T> template<Reg16 IXY, Reg8 SRC> II CPUCore<T>::ld_xix_R() {
2726  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_LD_XIX_R_1);
2727  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2728  T::setMemPtr(addr);
2729  WRMEM(addr, get8<SRC>(), T::CC_DD + T::CC_LD_XIX_R_2);
2730  return {2, T::CC_DD + T::CC_LD_XIX_R};
2731 }
2732 
2733 // LD (HL),n
2734 template<class T> II CPUCore<T>::ld_xhl_byte() {
2735  byte val = RDMEM_OPCODE<1>(T::CC_LD_HL_N_1);
2736  WRMEM(getHL(), val, T::CC_LD_HL_N_2);
2737  return {2, T::CC_LD_HL_N};
2738 }
2739 
2740 // LD (IXY+e),n
2741 template<class T> template<Reg16 IXY> II CPUCore<T>::ld_xix_byte() {
2742  unsigned tmp = RD_WORD_PC<1>(T::CC_DD + T::CC_LD_XIX_N_1);
2743  int8_t ofst = tmp & 0xFF;
2744  byte val = tmp >> 8;
2745  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2746  T::setMemPtr(addr);
2747  WRMEM(addr, val, T::CC_DD + T::CC_LD_XIX_N_2);
2748  return {3, T::CC_DD + T::CC_LD_XIX_N};
2749 }
2750 
2751 // LD (nn),A
2752 template<class T> II CPUCore<T>::ld_xbyte_a() {
2753  unsigned x = RD_WORD_PC<1>(T::CC_LD_NN_A_1);
2754  T::setMemPtr((getA() << 8) | ((x + 1) & 0xFF));
2755  WRMEM(x, getA(), T::CC_LD_NN_A_2);
2756  return {3, T::CC_LD_NN_A};
2757 }
2758 
2759 // LD (nn),ss
2760 template<class T> template<int EE> inline II CPUCore<T>::WR_NN_Y(unsigned reg) {
2761  unsigned addr = RD_WORD_PC<1>(T::CC_LD_XX_HL_1 + EE);
2762  T::setMemPtr(addr + 1);
2763  WR_WORD(addr, reg, T::CC_LD_XX_HL_2 + EE);
2764  return {3, T::CC_LD_XX_HL + EE};
2765 }
2766 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ld_xword_SS() {
2767  return WR_NN_Y<EE >(get16<REG>());
2768 }
2769 template<class T> template<Reg16 REG> II CPUCore<T>::ld_xword_SS_ED() {
2770  return WR_NN_Y<T::EE_ED>(get16<REG>());
2771 }
2772 
2773 // LD A,(ss)
2774 template<class T> template<Reg16 REG> II CPUCore<T>::ld_a_SS() {
2775  T::setMemPtr(get16<REG>() + 1);
2776  setA(RDMEM(get16<REG>(), T::CC_LD_A_SS_1));
2777  return {1, T::CC_LD_A_SS};
2778 }
2779 
2780 // LD A,(nn)
2781 template<class T> II CPUCore<T>::ld_a_xbyte() {
2782  unsigned addr = RD_WORD_PC<1>(T::CC_LD_A_NN_1);
2783  T::setMemPtr(addr + 1);
2784  setA(RDMEM(addr, T::CC_LD_A_NN_2));
2785  return {3, T::CC_LD_A_NN};
2786 }
2787 
2788 // LD r,n
2789 template<class T> template<Reg8 DST, int EE> II CPUCore<T>::ld_R_byte() {
2790  set8<DST>(RDMEM_OPCODE<1>(T::CC_LD_R_N_1 + EE)); return {2, T::CC_LD_R_N + EE};
2791 }
2792 
2793 // LD r,(hl)
2794 template<class T> template<Reg8 DST> II CPUCore<T>::ld_R_xhl() {
2795  set8<DST>(RDMEM(getHL(), T::CC_LD_R_HL_1)); return {1, T::CC_LD_R_HL};
2796 }
2797 
2798 // LD r,(IXY+e)
2799 template<class T> template<Reg8 DST, Reg16 IXY> II CPUCore<T>::ld_R_xix() {
2800  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_LD_R_XIX_1);
2801  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2802  T::setMemPtr(addr);
2803  set8<DST>(RDMEM(addr, T::CC_DD + T::CC_LD_R_XIX_2));
2804  return {2, T::CC_DD + T::CC_LD_R_XIX};
2805 }
2806 
2807 // LD ss,(nn)
2808 template<class T> template<int EE> inline unsigned CPUCore<T>::RD_P_XX() {
2809  unsigned addr = RD_WORD_PC<1>(T::CC_LD_HL_XX_1 + EE);
2810  T::setMemPtr(addr + 1);
2811  unsigned result = RD_WORD(addr, T::CC_LD_HL_XX_2 + EE);
2812  return result;
2813 }
2814 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ld_SS_xword() {
2815  set16<REG>(RD_P_XX<EE>()); return {3, T::CC_LD_HL_XX + EE};
2816 }
2817 template<class T> template<Reg16 REG> II CPUCore<T>::ld_SS_xword_ED() {
2818  set16<REG>(RD_P_XX<T::EE_ED>()); return {3, T::CC_LD_HL_XX + T::EE_ED};
2819 }
2820 
2821 // LD ss,nn
2822 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ld_SS_word() {
2823  set16<REG>(RD_WORD_PC<1>(T::CC_LD_SS_NN_1 + EE)); return {3, T::CC_LD_SS_NN + EE};
2824 }
2825 
2826 
2827 // ADC A,r
2828 template<class T> inline void CPUCore<T>::ADC(byte reg) {
2829  unsigned res = getA() + reg + ((getF() & C_FLAG) ? 1 : 0);
2830  byte f = ((res & 0x100) ? C_FLAG : 0) |
2831  ((getA() ^ res ^ reg) & H_FLAG) |
2832  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2833  0; // N_FLAG
2834  if (T::isR800()) {
2835  f |= table.ZS[res & 0xFF];
2836  f |= getF() & (X_FLAG | Y_FLAG);
2837  } else {
2838  f |= table.ZSXY[res & 0xFF];
2839  }
2840  setF(f);
2841  setA(res);
2842 }
2843 template<class T> inline II CPUCore<T>::adc_a_a() {
2844  unsigned res = 2 * getA() + ((getF() & C_FLAG) ? 1 : 0);
2845  byte f = ((res & 0x100) ? C_FLAG : 0) |
2846  (res & H_FLAG) |
2847  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2848  0; // N_FLAG
2849  if (T::isR800()) {
2850  f |= table.ZS[res & 0xFF];
2851  f |= getF() & (X_FLAG | Y_FLAG);
2852  } else {
2853  f |= table.ZSXY[res & 0xFF];
2854  }
2855  setF(f);
2856  setA(res);
2857  return {1, T::CC_CP_R};
2858 }
2859 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::adc_a_R() {
2860  ADC(get8<SRC>()); return {1, T::CC_CP_R + EE};
2861 }
2862 template<class T> II CPUCore<T>::adc_a_byte() {
2863  ADC(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2864 }
2865 template<class T> II CPUCore<T>::adc_a_xhl() {
2866  ADC(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2867 }
2868 template<class T> template<Reg16 IXY> II CPUCore<T>::adc_a_xix() {
2869  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2870  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2871  T::setMemPtr(addr);
2872  ADC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2873  return {2, T::CC_DD + T::CC_CP_XIX};
2874 }
2875 
2876 // ADD A,r
2877 template<class T> inline void CPUCore<T>::ADD(byte reg) {
2878  unsigned res = getA() + reg;
2879  byte f = ((res & 0x100) ? C_FLAG : 0) |
2880  ((getA() ^ res ^ reg) & H_FLAG) |
2881  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2882  0; // N_FLAG
2883  if (T::isR800()) {
2884  f |= table.ZS[res & 0xFF];
2885  f |= getF() & (X_FLAG | Y_FLAG);
2886  } else {
2887  f |= table.ZSXY[res & 0xFF];
2888  }
2889  setF(f);
2890  setA(res);
2891 }
2892 template<class T> inline II CPUCore<T>::add_a_a() {
2893  unsigned res = 2 * getA();
2894  byte f = ((res & 0x100) ? C_FLAG : 0) |
2895  (res & H_FLAG) |
2896  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2897  0; // N_FLAG
2898  if (T::isR800()) {
2899  f |= table.ZS[res & 0xFF];
2900  f |= getF() & (X_FLAG | Y_FLAG);
2901  } else {
2902  f |= table.ZSXY[res & 0xFF];
2903  }
2904  setF(f);
2905  setA(res);
2906  return {1, T::CC_CP_R};
2907 }
2908 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::add_a_R() {
2909  ADD(get8<SRC>()); return {1, T::CC_CP_R + EE};
2910 }
2911 template<class T> II CPUCore<T>::add_a_byte() {
2912  ADD(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2913 }
2914 template<class T> II CPUCore<T>::add_a_xhl() {
2915  ADD(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2916 }
2917 template<class T> template<Reg16 IXY> II CPUCore<T>::add_a_xix() {
2918  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2919  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2920  T::setMemPtr(addr);
2921  ADD(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2922  return {2, T::CC_DD + T::CC_CP_XIX};
2923 }
2924 
2925 // AND r
2926 template<class T> inline void CPUCore<T>::AND(byte reg) {
2927  setA(getA() & reg);
2928  byte f = 0;
2929  if (T::isR800()) {
2930  f |= table.ZSPH[getA()];
2931  f |= getF() & (X_FLAG | Y_FLAG);
2932  } else {
2933  f |= table.ZSPXY[getA()] | H_FLAG;
2934  }
2935  setF(f);
2936 }
2937 template<class T> II CPUCore<T>::and_a() {
2938  byte f = 0;
2939  if (T::isR800()) {
2940  f |= table.ZSPH[getA()];
2941  f |= getF() & (X_FLAG | Y_FLAG);
2942  } else {
2943  f |= table.ZSPXY[getA()] | H_FLAG;
2944  }
2945  setF(f);
2946  return {1, T::CC_CP_R};
2947 }
2948 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::and_R() {
2949  AND(get8<SRC>()); return {1, T::CC_CP_R + EE};
2950 }
2951 template<class T> II CPUCore<T>::and_byte() {
2952  AND(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2953 }
2954 template<class T> II CPUCore<T>::and_xhl() {
2955  AND(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2956 }
2957 template<class T> template<Reg16 IXY> II CPUCore<T>::and_xix() {
2958  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2959  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2960  T::setMemPtr(addr);
2961  AND(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2962  return {2, T::CC_DD + T::CC_CP_XIX};
2963 }
2964 
2965 // CP r
2966 template<class T> inline void CPUCore<T>::CP(byte reg) {
2967  unsigned q = getA() - reg;
2968  byte f = table.ZS[q & 0xFF] |
2969  ((q & 0x100) ? C_FLAG : 0) |
2970  N_FLAG |
2971  ((getA() ^ q ^ reg) & H_FLAG) |
2972  (((reg ^ getA()) & (getA() ^ q) & 0x80) >> 5); // V_FLAG
2973  if (T::isR800()) {
2974  f |= getF() & (X_FLAG | Y_FLAG);
2975  } else {
2976  f |= reg & (X_FLAG | Y_FLAG); // XY from operand, not from result
2977  }
2978  setF(f);
2979 }
2980 template<class T> II CPUCore<T>::cp_a() {
2981  byte f = ZS0 | N_FLAG;
2982  if (T::isR800()) {
2983  f |= getF() & (X_FLAG | Y_FLAG);
2984  } else {
2985  f |= getA() & (X_FLAG | Y_FLAG); // XY from operand, not from result
2986  }
2987  setF(f);
2988  return {1, T::CC_CP_R};
2989 }
2990 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::cp_R() {
2991  CP(get8<SRC>()); return {1, T::CC_CP_R + EE};
2992 }
2993 template<class T> II CPUCore<T>::cp_byte() {
2994  CP(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2995 }
2996 template<class T> II CPUCore<T>::cp_xhl() {
2997  CP(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2998 }
2999 template<class T> template<Reg16 IXY> II CPUCore<T>::cp_xix() {
3000  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3001  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3002  T::setMemPtr(addr);
3003  CP(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3004  return {2, T::CC_DD + T::CC_CP_XIX};
3005 }
3006 
3007 // OR r
3008 template<class T> inline void CPUCore<T>::OR(byte reg) {
3009  setA(getA() | reg);
3010  byte f = 0;
3011  if (T::isR800()) {
3012  f |= table.ZSP[getA()];
3013  f |= getF() & (X_FLAG | Y_FLAG);
3014  } else {
3015  f |= table.ZSPXY[getA()];
3016  }
3017  setF(f);
3018 }
3019 template<class T> II CPUCore<T>::or_a() {
3020  byte f = 0;
3021  if (T::isR800()) {
3022  f |= table.ZSP[getA()];
3023  f |= getF() & (X_FLAG | Y_FLAG);
3024  } else {
3025  f |= table.ZSPXY[getA()];
3026  }
3027  setF(f);
3028  return {1, T::CC_CP_R};
3029 }
3030 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::or_R() {
3031  OR(get8<SRC>()); return {1, T::CC_CP_R + EE};
3032 }
3033 template<class T> II CPUCore<T>::or_byte() {
3034  OR(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3035 }
3036 template<class T> II CPUCore<T>::or_xhl() {
3037  OR(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3038 }
3039 template<class T> template<Reg16 IXY> II CPUCore<T>::or_xix() {
3040  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3041  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3042  T::setMemPtr(addr);
3043  OR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3044  return {2, T::CC_DD + T::CC_CP_XIX};
3045 }
3046 
3047 // SBC A,r
3048 template<class T> inline void CPUCore<T>::SBC(byte reg) {
3049  unsigned res = getA() - reg - ((getF() & C_FLAG) ? 1 : 0);
3050  byte f = ((res & 0x100) ? C_FLAG : 0) |
3051  N_FLAG |
3052  ((getA() ^ res ^ reg) & H_FLAG) |
3053  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3054  if (T::isR800()) {
3055  f |= table.ZS[res & 0xFF];
3056  f |= getF() & (X_FLAG | Y_FLAG);
3057  } else {
3058  f |= table.ZSXY[res & 0xFF];
3059  }
3060  setF(f);
3061  setA(res);
3062 }
3063 template<class T> II CPUCore<T>::sbc_a_a() {
3064  if (T::isR800()) {
3065  word t = (getF() & C_FLAG)
3066  ? (255 * 256 | ZS255 | C_FLAG | H_FLAG | N_FLAG)
3067  : ( 0 * 256 | ZS0 | N_FLAG);
3068  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3069  } else {
3070  setAF((getF() & C_FLAG) ?
3071  (255 * 256 | ZSXY255 | C_FLAG | H_FLAG | N_FLAG) :
3072  ( 0 * 256 | ZSXY0 | N_FLAG));
3073  }
3074  return {1, T::CC_CP_R};
3075 }
3076 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::sbc_a_R() {
3077  SBC(get8<SRC>()); return {1, T::CC_CP_R + EE};
3078 }
3079 template<class T> II CPUCore<T>::sbc_a_byte() {
3080  SBC(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3081 }
3082 template<class T> II CPUCore<T>::sbc_a_xhl() {
3083  SBC(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3084 }
3085 template<class T> template<Reg16 IXY> II CPUCore<T>::sbc_a_xix() {
3086  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3087  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3088  T::setMemPtr(addr);
3089  SBC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3090  return {2, T::CC_DD + T::CC_CP_XIX};
3091 }
3092 
3093 // SUB r
3094 template<class T> inline void CPUCore<T>::SUB(byte reg) {
3095  unsigned res = getA() - reg;
3096  byte f = ((res & 0x100) ? C_FLAG : 0) |
3097  N_FLAG |
3098  ((getA() ^ res ^ reg) & H_FLAG) |
3099  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3100  if (T::isR800()) {
3101  f |= table.ZS[res & 0xFF];
3102  f |= getF() & (X_FLAG | Y_FLAG);
3103  } else {
3104  f |= table.ZSXY[res & 0xFF];
3105  }
3106  setF(f);
3107  setA(res);
3108 }
3109 template<class T> II CPUCore<T>::sub_a() {
3110  if (T::isR800()) {
3111  word t = 0 * 256 | ZS0 | N_FLAG;
3112  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3113  } else {
3114  setAF(0 * 256 | ZSXY0 | N_FLAG);
3115  }
3116  return {1, T::CC_CP_R};
3117 }
3118 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::sub_R() {
3119  SUB(get8<SRC>()); return {1, T::CC_CP_R + EE};
3120 }
3121 template<class T> II CPUCore<T>::sub_byte() {
3122  SUB(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3123 }
3124 template<class T> II CPUCore<T>::sub_xhl() {
3125  SUB(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3126 }
3127 template<class T> template<Reg16 IXY> II CPUCore<T>::sub_xix() {
3128  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3129  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3130  T::setMemPtr(addr);
3131  SUB(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3132  return {2, T::CC_DD + T::CC_CP_XIX};
3133 }
3134 
3135 // XOR r
3136 template<class T> inline void CPUCore<T>::XOR(byte reg) {
3137  setA(getA() ^ reg);
3138  byte f = 0;
3139  if (T::isR800()) {
3140  f |= table.ZSP[getA()];
3141  f |= getF() & (X_FLAG | Y_FLAG);
3142  } else {
3143  f |= table.ZSPXY[getA()];
3144  }
3145  setF(f);
3146 }
3147 template<class T> II CPUCore<T>::xor_a() {
3148  if (T::isR800()) {
3149  word t = 0 * 256 + ZSP0;
3150  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3151  } else {
3152  setAF(0 * 256 + ZSPXY0);
3153  }
3154  return {1, T::CC_CP_R};
3155 }
3156 template<class T> template<Reg8 SRC, int EE> II CPUCore<T>::xor_R() {
3157  XOR(get8<SRC>()); return {1, T::CC_CP_R + EE};
3158 }
3159 template<class T> II CPUCore<T>::xor_byte() {
3160  XOR(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3161 }
3162 template<class T> II CPUCore<T>::xor_xhl() {
3163  XOR(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3164 }
3165 template<class T> template<Reg16 IXY> II CPUCore<T>::xor_xix() {
3166  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3167  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3168  T::setMemPtr(addr);
3169  XOR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3170  return {2, T::CC_DD + T::CC_CP_XIX};
3171 }
3172 
3173 
3174 // DEC r
3175 template<class T> inline byte CPUCore<T>::DEC(byte reg) {
3176  byte res = reg - 1;
3177  byte f = ((reg & ~res & 0x80) >> 5) | // V_FLAG
3178  (((res & 0x0F) + 1) & H_FLAG) |
3179  N_FLAG;
3180  if (T::isR800()) {
3181  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3182  f |= table.ZS[res];
3183  } else {
3184  f |= getF() & C_FLAG;
3185  f |= table.ZSXY[res];
3186  }
3187  setF(f);
3188  return res;
3189 }
3190 template<class T> template<Reg8 REG, int EE> II CPUCore<T>::dec_R() {
3191  set8<REG>(DEC(get8<REG>())); return {1, T::CC_INC_R + EE};
3192 }
3193 template<class T> template<int EE> inline void CPUCore<T>::DEC_X(unsigned x) {
3194  byte val = DEC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3195  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3196 }
3197 template<class T> II CPUCore<T>::dec_xhl() {
3198  DEC_X<0>(getHL());
3199  return {1, T::CC_INC_XHL};
3200 }
3201 template<class T> template<Reg16 IXY> II CPUCore<T>::dec_xix() {
3202  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_INC_XIX_1);
3203  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3204  T::setMemPtr(addr);
3205  DEC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3206  return {2, T::CC_INC_XHL + T::CC_DD + T::EE_INC_XIX};
3207 }
3208 
3209 // INC r
3210 template<class T> inline byte CPUCore<T>::INC(byte reg) {
3211  reg++;
3212  byte f = ((reg & -reg & 0x80) >> 5) | // V_FLAG
3213  (((reg & 0x0F) - 1) & H_FLAG) |
3214  0; // N_FLAG
3215  if (T::isR800()) {
3216  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3217  f |= table.ZS[reg];
3218  } else {
3219  f |= getF() & C_FLAG;
3220  f |= table.ZSXY[reg];
3221  }
3222  setF(f);
3223  return reg;
3224 }
3225 template<class T> template<Reg8 REG, int EE> II CPUCore<T>::inc_R() {
3226  set8<REG>(INC(get8<REG>())); return {1, T::CC_INC_R + EE};
3227 }
3228 template<class T> template<int EE> inline void CPUCore<T>::INC_X(unsigned x) {
3229  byte val = INC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3230  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3231 }
3232 template<class T> II CPUCore<T>::inc_xhl() {
3233  INC_X<0>(getHL());
3234  return {1, T::CC_INC_XHL};
3235 }
3236 template<class T> template<Reg16 IXY> II CPUCore<T>::inc_xix() {
3237  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_INC_XIX_1);
3238  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3239  T::setMemPtr(addr);
3240  INC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3241  return {2, T::CC_INC_XHL + T::CC_DD + T::EE_INC_XIX};
3242 }
3243 
3244 
3245 // ADC HL,ss
3246 template<class T> template<Reg16 REG> inline II CPUCore<T>::adc_hl_SS() {
3247  unsigned reg = get16<REG>();
3248  T::setMemPtr(getHL() + 1);
3249  unsigned res = getHL() + reg + ((getF() & C_FLAG) ? 1 : 0);
3250  byte f = (res >> 16) | // C_FLAG
3251  0; // N_FLAG
3252  if (T::isR800()) {
3253  f |= getF() & (X_FLAG | Y_FLAG);
3254  }
3255  if (res & 0xFFFF) {
3256  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3257  f |= 0; // Z_FLAG
3258  f |= ((getHL() ^ res) & (reg ^ res) & 0x8000) >> 13; // V_FLAG
3259  if (T::isR800()) {
3260  f |= (res >> 8) & S_FLAG;
3261  } else {
3262  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3263  }
3264  } else {
3265  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3266  f |= Z_FLAG;
3267  f |= (getHL() & reg & 0x8000) >> 13; // V_FLAG
3268  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3269  }
3270  setF(f);
3271  setHL(res);
3272  return {1, T::CC_ADC_HL_SS};
3273 }
3274 template<class T> II CPUCore<T>::adc_hl_hl() {
3275  T::setMemPtr(getHL() + 1);
3276  unsigned res = 2 * getHL() + ((getF() & C_FLAG) ? 1 : 0);
3277  byte f = (res >> 16) | // C_FLAG
3278  0; // N_FLAG
3279  if (T::isR800()) {
3280  f |= getF() & (X_FLAG | Y_FLAG);
3281  }
3282  if (res & 0xFFFF) {
3283  f |= 0; // Z_FLAG
3284  f |= ((getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3285  if (T::isR800()) {
3286  f |= (res >> 8) & (H_FLAG | S_FLAG);
3287  } else {
3288  f |= (res >> 8) & (H_FLAG | S_FLAG | X_FLAG | Y_FLAG);
3289  }
3290  } else {
3291  f |= Z_FLAG;
3292  f |= (getHL() & 0x8000) >> 13; // V_FLAG
3293  f |= 0; // H_FLAG S_FLAG (X_FLAG Y_FLAG)
3294  }
3295  setF(f);
3296  setHL(res);
3297  return {1, T::CC_ADC_HL_SS};
3298 }
3299 
3300 // ADD HL/IX/IY,ss
3301 template<class T> template<Reg16 REG1, Reg16 REG2, int EE> II CPUCore<T>::add_SS_TT() {
3302  unsigned reg1 = get16<REG1>();
3303  unsigned reg2 = get16<REG2>();
3304  T::setMemPtr(reg1 + 1);
3305  unsigned res = reg1 + reg2;
3306  byte f = (((reg1 ^ res ^ reg2) >> 8) & H_FLAG) |
3307  (res >> 16) | // C_FLAG
3308  0; // N_FLAG
3309  if (T::isR800()) {
3310  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3311  } else {
3312  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3313  f |= (res >> 8) & (X_FLAG | Y_FLAG);
3314  }
3315  setF(f);
3316  set16<REG1>(res & 0xFFFF);
3317  return {1, T::CC_ADD_HL_SS + EE};
3318 }
3319 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::add_SS_SS() {
3320  unsigned reg = get16<REG>();
3321  T::setMemPtr(reg + 1);
3322  unsigned res = 2 * reg;
3323  byte f = (res >> 16) | // C_FLAG
3324  0; // N_FLAG
3325  if (T::isR800()) {
3326  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3327  f |= (res >> 8) & H_FLAG;
3328  } else {
3329  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3330  f |= (res >> 8) & (H_FLAG | X_FLAG | Y_FLAG);
3331  }
3332  setF(f);
3333  set16<REG>(res & 0xFFFF);
3334  return {1, T::CC_ADD_HL_SS + EE};
3335 }
3336 
3337 // SBC HL,ss
3338 template<class T> template<Reg16 REG> inline II CPUCore<T>::sbc_hl_SS() {
3339  unsigned reg = get16<REG>();
3340  T::setMemPtr(getHL() + 1);
3341  unsigned res = getHL() - reg - ((getF() & C_FLAG) ? 1 : 0);
3342  byte f = ((res & 0x10000) ? C_FLAG : 0) |
3343  N_FLAG;
3344  if (T::isR800()) {
3345  f |= getF() & (X_FLAG | Y_FLAG);
3346  }
3347  if (res & 0xFFFF) {
3348  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3349  f |= 0; // Z_FLAG
3350  f |= ((reg ^ getHL()) & (getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3351  if (T::isR800()) {
3352  f |= (res >> 8) & S_FLAG;
3353  } else {
3354  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3355  }
3356  } else {
3357  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3358  f |= Z_FLAG;
3359  f |= ((reg ^ getHL()) & getHL() & 0x8000) >> 13; // V_FLAG
3360  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3361  }
3362  setF(f);
3363  setHL(res);
3364  return {1, T::CC_ADC_HL_SS};
3365 }
3366 template<class T> II CPUCore<T>::sbc_hl_hl() {
3367  T::setMemPtr(getHL() + 1);
3368  byte f = T::isR800() ? (getF() & (X_FLAG | Y_FLAG)) : 0;
3369  if (getF() & C_FLAG) {
3370  f |= C_FLAG | H_FLAG | S_FLAG | N_FLAG;
3371  if (!T::isR800()) {
3372  f |= X_FLAG | Y_FLAG;
3373  }
3374  setHL(0xFFFF);
3375  } else {
3376  f |= Z_FLAG | N_FLAG;
3377  setHL(0);
3378  }
3379  setF(f);
3380  return {1, T::CC_ADC_HL_SS};
3381 }
3382 
3383 // DEC ss
3384 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::dec_SS() {
3385  set16<REG>(get16<REG>() - 1); return {1, T::CC_INC_SS + EE};
3386 }
3387 
3388 // INC ss
3389 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::inc_SS() {
3390  set16<REG>(get16<REG>() + 1); return {1, T::CC_INC_SS + EE};
3391 }
3392 
3393 
3394 // BIT n,r
3395 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::bit_N_R() {
3396  byte reg = get8<REG>();
3397  byte f = 0; // N_FLAG
3398  if (T::isR800()) {
3399  // this is very different from Z80 (not only XY flags)
3400  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3401  f |= H_FLAG;
3402  f |= (reg & (1 << N)) ? 0 : Z_FLAG;
3403  } else {
3404  f |= table.ZSPH[reg & (1 << N)];
3405  f |= getF() & C_FLAG;
3406  f |= reg & (X_FLAG | Y_FLAG);
3407  }
3408  setF(f);
3409  return {1, T::CC_BIT_R};
3410 }
3411 template<class T> template<unsigned N> inline II CPUCore<T>::bit_N_xhl() {
3412  byte m = RDMEM(getHL(), T::CC_BIT_XHL_1) & (1 << N);
3413  byte f = 0; // N_FLAG
3414  if (T::isR800()) {
3415  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3416  f |= H_FLAG;
3417  f |= m ? 0 : Z_FLAG;
3418  } else {
3419  f |= table.ZSPH[m];
3420  f |= getF() & C_FLAG;
3421  f |= (T::getMemPtr() >> 8) & (X_FLAG | Y_FLAG);
3422  }
3423  setF(f);
3424  return {1, T::CC_BIT_XHL};
3425 }
3426 template<class T> template<unsigned N> inline II CPUCore<T>::bit_N_xix(unsigned addr) {
3427  T::setMemPtr(addr);
3428  byte m = RDMEM(addr, T::CC_DD + T::CC_BIT_XIX_1) & (1 << N);
3429  byte f = 0; // N_FLAG
3430  if (T::isR800()) {
3431  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3432  f |= H_FLAG;
3433  f |= m ? 0 : Z_FLAG;
3434  } else {
3435  f |= table.ZSPH[m];
3436  f |= getF() & C_FLAG;
3437  f |= (addr >> 8) & (X_FLAG | Y_FLAG);
3438  }
3439  setF(f);
3440  return {3, T::CC_DD + T::CC_BIT_XIX};
3441 }
3442 
3443 // RES n,r
3444 static inline byte RES(unsigned b, byte reg) {
3445  return reg & ~(1 << b);
3446 }
3447 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::res_N_R() {
3448  set8<REG>(RES(N, get8<REG>())); return {1, T::CC_SET_R};
3449 }
3450 template<class T> template<int EE> inline byte CPUCore<T>::RES_X(unsigned bit, unsigned addr) {
3451  byte res = RES(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3452  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3453  return res;
3454 }
3455 template<class T> template<unsigned N> II CPUCore<T>::res_N_xhl() {
3456  RES_X<0>(N, getHL()); return {1, T::CC_SET_XHL};
3457 }
3458 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::res_N_xix_R(unsigned a) {
3459  T::setMemPtr(a);
3460  set8<REG>(RES_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3461  return {3, T::CC_DD + T::CC_SET_XIX};
3462 }
3463 
3464 // SET n,r
3465 static inline byte SET(unsigned b, byte reg) {
3466  return reg | (1 << b);
3467 }
3468 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::set_N_R() {
3469  set8<REG>(SET(N, get8<REG>())); return {1, T::CC_SET_R};
3470 }
3471 template<class T> template<int EE> inline byte CPUCore<T>::SET_X(unsigned bit, unsigned addr) {
3472  byte res = SET(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3473  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3474  return res;
3475 }
3476 template<class T> template<unsigned N> II CPUCore<T>::set_N_xhl() {
3477  SET_X<0>(N, getHL()); return {1, T::CC_SET_XHL};
3478 }
3479 template<class T> template<unsigned N, Reg8 REG> II CPUCore<T>::set_N_xix_R(unsigned a) {
3480  T::setMemPtr(a);
3481  set8<REG>(SET_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3482  return {3, T::CC_DD + T::CC_SET_XIX};
3483 }
3484 
3485 // RL r
3486 template<class T> inline byte CPUCore<T>::RL(byte reg) {
3487  byte c = reg >> 7;
3488  reg = (reg << 1) | ((getF() & C_FLAG) ? 0x01 : 0);
3489  byte f = c ? C_FLAG : 0;
3490  if (T::isR800()) {
3491  f |= table.ZSP[reg];
3492  f |= getF() & (X_FLAG | Y_FLAG);
3493  } else {
3494  f |= table.ZSPXY[reg];
3495  }
3496  setF(f);
3497  return reg;
3498 }
3499 template<class T> template<int EE> inline byte CPUCore<T>::RL_X(unsigned x) {
3500  byte res = RL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3501  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3502  return res;
3503 }
3504 template<class T> template<Reg8 REG> II CPUCore<T>::rl_R() {
3505  set8<REG>(RL(get8<REG>())); return {1, T::CC_SET_R};
3506 }
3507 template<class T> II CPUCore<T>::rl_xhl() {
3508  RL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3509 }
3510 template<class T> template<Reg8 REG> II CPUCore<T>::rl_xix_R(unsigned a) {
3511  T::setMemPtr(a);
3512  set8<REG>(RL_X<T::CC_DD + T::EE_SET_XIX>(a));
3513  return {3, T::CC_DD + T::CC_SET_XIX};
3514 }
3515 
3516 // RLC r
3517 template<class T> inline byte CPUCore<T>::RLC(byte reg) {
3518  byte c = reg >> 7;
3519  reg = (reg << 1) | c;
3520  byte f = c ? C_FLAG : 0;
3521  if (T::isR800()) {
3522  f |= table.ZSP[reg];
3523  f |= getF() & (X_FLAG | Y_FLAG);
3524  } else {
3525  f |= table.ZSPXY[reg];
3526  }
3527  setF(f);
3528  return reg;
3529 }
3530 template<class T> template<int EE> inline byte CPUCore<T>::RLC_X(unsigned x) {
3531  byte res = RLC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3532  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3533  return res;
3534 }
3535 template<class T> template<Reg8 REG> II CPUCore<T>::rlc_R() {
3536  set8<REG>(RLC(get8<REG>())); return {1, T::CC_SET_R};
3537 }
3538 template<class T> II CPUCore<T>::rlc_xhl() {
3539  RLC_X<0>(getHL()); return {1, T::CC_SET_XHL};
3540 }
3541 template<class T> template<Reg8 REG> II CPUCore<T>::rlc_xix_R(unsigned a) {
3542  T::setMemPtr(a);
3543  set8<REG>(RLC_X<T::CC_DD + T::EE_SET_XIX>(a));
3544  return {3, T::CC_DD + T::CC_SET_XIX};
3545 }
3546 
3547 // RR r
3548 template<class T> inline byte CPUCore<T>::RR(byte reg) {
3549  byte c = reg & 1;
3550  reg = (reg >> 1) | ((getF() & C_FLAG) << 7);
3551  byte f = c ? C_FLAG : 0;
3552  if (T::isR800()) {
3553  f |= table.ZSP[reg];
3554  f |= getF() & (X_FLAG | Y_FLAG);
3555  } else {
3556  f |= table.ZSPXY[reg];
3557  }
3558  setF(f);
3559  return reg;
3560 }
3561 template<class T> template<int EE> inline byte CPUCore<T>::RR_X(unsigned x) {
3562  byte res = RR(RDMEM(x, T::CC_SET_XHL_1 + EE));
3563  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3564  return res;
3565 }
3566 template<class T> template<Reg8 REG> II CPUCore<T>::rr_R() {
3567  set8<REG>(RR(get8<REG>())); return {1, T::CC_SET_R};
3568 }
3569 template<class T> II CPUCore<T>::rr_xhl() {
3570  RR_X<0>(getHL()); return {1, T::CC_SET_XHL};
3571 }
3572 template<class T> template<Reg8 REG> II CPUCore<T>::rr_xix_R(unsigned a) {
3573  T::setMemPtr(a);
3574  set8<REG>(RR_X<T::CC_DD + T::EE_SET_XIX>(a));
3575  return {3, T::CC_DD + T::CC_SET_XIX};
3576 }
3577 
3578 // RRC r
3579 template<class T> inline byte CPUCore<T>::RRC(byte reg) {
3580  byte c = reg & 1;
3581  reg = (reg >> 1) | (c << 7);
3582  byte f = c ? C_FLAG : 0;
3583  if (T::isR800()) {
3584  f |= table.ZSP[reg];
3585  f |= getF() & (X_FLAG | Y_FLAG);
3586  } else {
3587  f |= table.ZSPXY[reg];
3588  }
3589  setF(f);
3590  return reg;
3591 }
3592 template<class T> template<int EE> inline byte CPUCore<T>::RRC_X(unsigned x) {
3593  byte res = RRC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3594  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3595  return res;
3596 }
3597 template<class T> template<Reg8 REG> II CPUCore<T>::rrc_R() {
3598  set8<REG>(RRC(get8<REG>())); return {1, T::CC_SET_R};
3599 }
3600 template<class T> II CPUCore<T>::rrc_xhl() {
3601  RRC_X<0>(getHL()); return {1, T::CC_SET_XHL};
3602 }
3603 template<class T> template<Reg8 REG> II CPUCore<T>::rrc_xix_R(unsigned a) {
3604  T::setMemPtr(a);
3605  set8<REG>(RRC_X<T::CC_DD + T::EE_SET_XIX>(a));
3606  return {3, T::CC_DD + T::CC_SET_XIX};
3607 }
3608 
3609 // SLA r
3610 template<class T> inline byte CPUCore<T>::SLA(byte reg) {
3611  byte c = reg >> 7;
3612  reg <<= 1;
3613  byte f = c ? C_FLAG : 0;
3614  if (T::isR800()) {
3615  f |= table.ZSP[reg];
3616  f |= getF() & (X_FLAG | Y_FLAG);
3617  } else {
3618  f |= table.ZSPXY[reg];
3619  }
3620  setF(f);
3621  return reg;
3622 }
3623 template<class T> template<int EE> inline byte CPUCore<T>::SLA_X(unsigned x) {
3624  byte res = SLA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3625  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3626  return res;
3627 }
3628 template<class T> template<Reg8 REG> II CPUCore<T>::sla_R() {
3629  set8<REG>(SLA(get8<REG>())); return {1, T::CC_SET_R};
3630 }
3631 template<class T> II CPUCore<T>::sla_xhl() {
3632  SLA_X<0>(getHL()); return {1, T::CC_SET_XHL};
3633 }
3634 template<class T> template<Reg8 REG> II CPUCore<T>::sla_xix_R(unsigned a) {
3635  T::setMemPtr(a);
3636  set8<REG>(SLA_X<T::CC_DD + T::EE_SET_XIX>(a));
3637  return {3, T::CC_DD + T::CC_SET_XIX};
3638 }
3639 
3640 // SLL r
3641 template<class T> inline byte CPUCore<T>::SLL(byte reg) {
3642  assert(!T::isR800()); // this instruction is Z80-only
3643  byte c = reg >> 7;
3644  reg = (reg << 1) | 1;
3645  byte f = c ? C_FLAG : 0;
3646  f |= table.ZSPXY[reg];
3647  setF(f);
3648  return reg;
3649 }
3650 template<class T> template<int EE> inline byte CPUCore<T>::SLL_X(unsigned x) {
3651  byte res = SLL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3652  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3653  return res;
3654 }
3655 template<class T> template<Reg8 REG> II CPUCore<T>::sll_R() {
3656  set8<REG>(SLL(get8<REG>())); return {1, T::CC_SET_R};
3657 }
3658 template<class T> II CPUCore<T>::sll_xhl() {
3659  SLL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3660 }
3661 template<class T> template<Reg8 REG> II CPUCore<T>::sll_xix_R(unsigned a) {
3662  T::setMemPtr(a);
3663  set8<REG>(SLL_X<T::CC_DD + T::EE_SET_XIX>(a));
3664  return {3, T::CC_DD + T::CC_SET_XIX};
3665 }
3666 template<class T> II CPUCore<T>::sll2() {
3667  assert(T::isR800()); // this instruction is R800-only
3668  byte f = (getF() & (X_FLAG | Y_FLAG)) |
3669  (getA() >> 7) | // C_FLAG
3670  0; // all other flags zero
3671  setF(f);
3672  return {3, T::CC_DD + T::CC_SET_XIX}; // TODO
3673 }
3674 
3675 // SRA r
3676 template<class T> inline byte CPUCore<T>::SRA(byte reg) {
3677  byte c = reg & 1;
3678  reg = (reg >> 1) | (reg & 0x80);
3679  byte f = c ? C_FLAG : 0;
3680  if (T::isR800()) {
3681  f |= table.ZSP[reg];
3682  f |= getF() & (X_FLAG | Y_FLAG);
3683  } else {
3684  f |= table.ZSPXY[reg];
3685  }
3686  setF(f);
3687  return reg;
3688 }
3689 template<class T> template<int EE> inline byte CPUCore<T>::SRA_X(unsigned x) {
3690  byte res = SRA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3691  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3692  return res;
3693 }
3694 template<class T> template<Reg8 REG> II CPUCore<T>::sra_R() {
3695  set8<REG>(SRA(get8<REG>())); return {1, T::CC_SET_R};
3696 }
3697 template<class T> II CPUCore<T>::sra_xhl() {
3698  SRA_X<0>(getHL()); return {1, T::CC_SET_XHL};
3699 }
3700 template<class T> template<Reg8 REG> II CPUCore<T>::sra_xix_R(unsigned a) {
3701  T::setMemPtr(a);
3702  set8<REG>(SRA_X<T::CC_DD + T::EE_SET_XIX>(a));
3703  return {3, T::CC_DD + T::CC_SET_XIX};
3704 }
3705 
3706 // SRL R
3707 template<class T> inline byte CPUCore<T>::SRL(byte reg) {
3708  byte c = reg & 1;
3709  reg >>= 1;
3710  byte f = c ? C_FLAG : 0;
3711  if (T::isR800()) {
3712  f |= table.ZSP[reg];
3713  f |= getF() & (X_FLAG | Y_FLAG);
3714  } else {
3715  f |= table.ZSPXY[reg];
3716  }
3717  setF(f);
3718  return reg;
3719 }
3720 template<class T> template<int EE> inline byte CPUCore<T>::SRL_X(unsigned x) {
3721  byte res = SRL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3722  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3723  return res;
3724 }
3725 template<class T> template<Reg8 REG> II CPUCore<T>::srl_R() {
3726  set8<REG>(SRL(get8<REG>())); return {1, T::CC_SET_R};
3727 }
3728 template<class T> II CPUCore<T>::srl_xhl() {
3729  SRL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3730 }
3731 template<class T> template<Reg8 REG> II CPUCore<T>::srl_xix_R(unsigned a) {
3732  T::setMemPtr(a);
3733  set8<REG>(SRL_X<T::CC_DD + T::EE_SET_XIX>(a));
3734  return {3, T::CC_DD + T::CC_SET_XIX};
3735 }
3736 
3737 // RLA RLCA RRA RRCA
3738 template<class T> II CPUCore<T>::rla() {
3739  byte c = getF() & C_FLAG;
3740  byte f = (getA() & 0x80) ? C_FLAG : 0;
3741  if (T::isR800()) {
3742  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3743  } else {
3744  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3745  }
3746  setA((getA() << 1) | (c ? 1 : 0));
3747  if (!T::isR800()) {
3748  f |= getA() & (X_FLAG | Y_FLAG);
3749  }
3750  setF(f);
3751  return {1, T::CC_RLA};
3752 }
3753 template<class T> II CPUCore<T>::rlca() {
3754  setA((getA() << 1) | (getA() >> 7));
3755  byte f = 0;
3756  if (T::isR800()) {
3757  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3758  f |= getA() & C_FLAG;
3759  } else {
3760  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3761  f |= getA() & (Y_FLAG | X_FLAG | C_FLAG);
3762  }
3763  setF(f);
3764  return {1, T::CC_RLA};
3765 }
3766 template<class T> II CPUCore<T>::rra() {
3767  byte c = (getF() & C_FLAG) << 7;
3768  byte f = (getA() & 0x01) ? C_FLAG : 0;
3769  if (T::isR800()) {
3770  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3771  } else {
3772  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3773  }
3774  setA((getA() >> 1) | c);
3775  if (!T::isR800()) {
3776  f |= getA() & (X_FLAG | Y_FLAG);
3777  }
3778  setF(f);
3779  return {1, T::CC_RLA};
3780 }
3781 template<class T> II CPUCore<T>::rrca() {
3782  byte f = getA() & C_FLAG;
3783  if (T::isR800()) {
3784  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3785  } else {
3786  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3787  }
3788  setA((getA() >> 1) | (getA() << 7));
3789  if (!T::isR800()) {
3790  f |= getA() & (X_FLAG | Y_FLAG);
3791  }
3792  setF(f);
3793  return {1, T::CC_RLA};
3794 }
3795 
3796 
3797 // RLD
3798 template<class T> II CPUCore<T>::rld() {
3799  byte val = RDMEM(getHL(), T::CC_RLD_1);
3800  T::setMemPtr(getHL() + 1);
3801  WRMEM(getHL(), (val << 4) | (getA() & 0x0F), T::CC_RLD_2);
3802  setA((getA() & 0xF0) | (val >> 4));
3803  byte f = 0;
3804  if (T::isR800()) {
3805  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3806  f |= table.ZSP[getA()];
3807  } else {
3808  f |= getF() & C_FLAG;
3809  f |= table.ZSPXY[getA()];
3810  }
3811  setF(f);
3812  return {1, T::CC_RLD};
3813 }
3814 
3815 // RRD
3816 template<class T> II CPUCore<T>::rrd() {
3817  byte val = RDMEM(getHL(), T::CC_RLD_1);
3818  T::setMemPtr(getHL() + 1);
3819  WRMEM(getHL(), (val >> 4) | (getA() << 4), T::CC_RLD_2);
3820  setA((getA() & 0xF0) | (val & 0x0F));
3821  byte f = 0;
3822  if (T::isR800()) {
3823  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3824  f |= table.ZSP[getA()];
3825  } else {
3826  f |= getF() & C_FLAG;
3827  f |= table.ZSPXY[getA()];
3828  }
3829  setF(f);
3830  return {1, T::CC_RLD};
3831 }
3832 
3833 
3834 // PUSH ss
3835 template<class T> template<int EE> inline void CPUCore<T>::PUSH(unsigned reg) {
3836  setSP(getSP() - 2);
3837  WR_WORD_rev<true, true>(getSP(), reg, T::CC_PUSH_1 + EE);
3838 }
3839 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::push_SS() {
3840  PUSH<EE>(get16<REG>()); return {1, T::CC_PUSH + EE};
3841 }
3842 
3843 // POP ss
3844 template<class T> template<int EE> inline unsigned CPUCore<T>::POP() {
3845  unsigned addr = getSP();
3846  setSP(addr + 2);
3847  if (T::isR800()) {
3848  // handles both POP and RET instructions (RET with condition = true)
3849  if (EE == 0) { // not reti/retn, not pop ix/iy
3850  setCurrentPopRet();
3851  // No need for setSlowInstructions()
3852  // -> this only matters directly after a CALL
3853  // instruction and in that case we're still
3854  // executing slow instructions.
3855  }
3856  }
3857  return RD_WORD(addr, T::CC_POP_1 + EE);
3858 }
3859 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::pop_SS() {
3860  set16<REG>(POP<EE>()); return {1, T::CC_POP + EE};
3861 }
3862 
3863 
3864 // CALL nn / CALL cc,nn
3865 template<class T> template<typename COND> II CPUCore<T>::call(COND cond) {
3866  unsigned addr = RD_WORD_PC<1>(T::CC_CALL_1);
3867  T::setMemPtr(addr);
3868  if (cond(getF())) {
3869  PUSH<T::EE_CALL>(getPC() + 3);
3870  setPC(addr);
3871  if (T::isR800()) {
3872  setCurrentCall();
3873  setSlowInstructions();
3874  }
3875  return {0/*3*/, T::CC_CALL_A};
3876  } else {
3877  return {3, T::CC_CALL_B};
3878  }
3879 }
3880 
3881 
3882 // RST n
3883 template<class T> template<unsigned ADDR> II CPUCore<T>::rst() {
3884  PUSH<0>(getPC() + 1);
3885  T::setMemPtr(ADDR);
3886  setPC(ADDR);
3887  if (T::isR800()) {
3888  setCurrentCall();
3889  setSlowInstructions();
3890  }
3891  return {0/*1*/, T::CC_RST};
3892 }
3893 
3894 
3895 // RET
3896 template<class T> template<int EE, typename COND> inline II CPUCore<T>::RET(COND cond) {
3897  if (cond(getF())) {
3898  unsigned addr = POP<EE>();
3899  T::setMemPtr(addr);
3900  setPC(addr);
3901  return {0/*1*/, T::CC_RET_A + EE};
3902  } else {
3903  return {1, T::CC_RET_B + EE};
3904  }
3905 }
3906 template<class T> template<typename COND> II CPUCore<T>::ret(COND cond) {
3907  return RET<T::EE_RET_C>(cond);
3908 }
3909 template<class T> II CPUCore<T>::ret() {
3910  return RET<0>(CondTrue());
3911 }
3912 template<class T> II CPUCore<T>::retn() { // also reti
3913  setIFF1(getIFF2());
3914  setSlowInstructions();
3915  return RET<T::EE_RETN>(CondTrue());
3916 }
3917 
3918 
3919 // JP ss
3920 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::jp_SS() {
3921  setPC(get16<REG>()); T::R800ForcePageBreak(); return {0/*1*/, T::CC_JP_HL + EE};
3922 }
3923 
3924 // JP nn / JP cc,nn
3925 template<class T> template<typename COND> II CPUCore<T>::jp(COND cond) {
3926  unsigned addr = RD_WORD_PC<1>(T::CC_JP_1);
3927  T::setMemPtr(addr);
3928  if (cond(getF())) {
3929  setPC(addr);
3930  T::R800ForcePageBreak();
3931  return {0/*3*/, T::CC_JP_A};
3932  } else {
3933  return {3, T::CC_JP_B};
3934  }
3935 }
3936 
3937 // JR e
3938 template<class T> template<typename COND> II CPUCore<T>::jr(COND cond) {
3939  int8_t ofst = RDMEM_OPCODE<1>(T::CC_JR_1);
3940  if (cond(getF())) {
3941  if (((getPC() + 2) & 0xFF) == 0) {
3942  // On R800, when this instruction is located in the
3943  // last two byte of a page (a page is a 256-byte
3944  // (aligned) memory block) and even if we jump back,
3945  // thus fetching the next opcode byte does not cause a
3946  // page-break, there still is one cycle overhead. It's
3947  // as-if there is a page-break.
3948  //
3949  // This could be explained by some (very limited)
3950  // pipeline behaviour in R800: it seems that the
3951  // decision to cause a page-break on the next
3952  // instruction is already made before the jump
3953  // destination address for the current instruction is
3954  // calculated (though a destination address in another
3955  // page is also a reason for a page-break).
3956  //
3957  // It's likely all instructions behave like this, but I
3958  // think we can get away with only explicitly emulating
3959  // this behaviour in the djnz and the jr (conditional
3960  // or not) instructions: all other instructions that
3961  // cause the PC to change in a non-incremental way do
3962  // already force a pagebreak for another reason, so
3963  // this effect is masked. Examples of such instructions
3964  // are: JP, RET, CALL, RST, all repeated block
3965  // instructions, accepting an IRQ, (are there more
3966  // instructions or events that change PC?)
3967  //
3968  // See doc/r800-djnz.txt for more details.
3969  T::R800ForcePageBreak();
3970  }
3971  setPC((getPC() + 2 + ofst) & 0xFFFF);
3972  T::setMemPtr(getPC());
3973  return {0/*2*/, T::CC_JR_A};
3974  } else {
3975  return {2, T::CC_JR_B};
3976  }
3977 }
3978 
3979 // DJNZ e
3980 template<class T> II CPUCore<T>::djnz() {
3981  byte b = getB() - 1;
3982  setB(b);
3983  int8_t ofst = RDMEM_OPCODE<1>(T::CC_JR_1 + T::EE_DJNZ);
3984  if (b) {
3985  if (((getPC() + 2) & 0xFF) == 0) {
3986  // See comment in jr()
3987  T::R800ForcePageBreak();
3988  }
3989  setPC((getPC() + 2 + ofst) & 0xFFFF);
3990  T::setMemPtr(getPC());
3991  return {0/*2*/, T::CC_JR_A + T::EE_DJNZ};
3992  } else {
3993  return {2, T::CC_JR_B + T::EE_DJNZ};
3994  }
3995 }
3996 
3997 // EX (SP),ss
3998 template<class T> template<Reg16 REG, int EE> II CPUCore<T>::ex_xsp_SS() {
3999  unsigned res = RD_WORD_impl<true, false>(getSP(), T::CC_EX_SP_HL_1 + EE);
4000  T::setMemPtr(res);
4001  WR_WORD_rev<false, true>(getSP(), get16<REG>(), T::CC_EX_SP_HL_2 + EE);
4002  set16<REG>(res);
4003  return {1, T::CC_EX_SP_HL + EE};
4004 }
4005 
4006 // IN r,(c)
4007 template<class T> template<Reg8 REG> II CPUCore<T>::in_R_c() {
4008  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_R_C_1);
4009  T::setMemPtr(getBC() + 1);
4010  byte res = READ_PORT(getBC(), T::CC_IN_R_C_1);
4011  byte f = 0;
4012  if (T::isR800()) {
4013  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4014  f |= table.ZSP[res];
4015  } else {
4016  f |= getF() & C_FLAG;
4017  f |= table.ZSPXY[res];
4018  }
4019  setF(f);
4020  set8<REG>(res);
4021  return {1, T::CC_IN_R_C};
4022 }
4023 
4024 // IN a,(n)
4025 template<class T> II CPUCore<T>::in_a_byte() {
4026  unsigned y = RDMEM_OPCODE<1>(T::CC_IN_A_N_1) + 256 * getA();
4027  T::setMemPtr(y + 1);
4028  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_A_N_2);
4029  setA(READ_PORT(y, T::CC_IN_A_N_2));
4030  return {2, T::CC_IN_A_N};
4031 }
4032 
4033 // OUT (c),r
4034 template<class T> template<Reg8 REG> II CPUCore<T>::out_c_R() {
4035  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4036  T::setMemPtr(getBC() + 1);
4037  WRITE_PORT(getBC(), get8<REG>(), T::CC_OUT_C_R_1);
4038  return {1, T::CC_OUT_C_R};
4039 }
4040 template<class T> II CPUCore<T>::out_c_0() {
4041  // TODO not on R800
4042  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4043  T::setMemPtr(getBC() + 1);
4044  byte out_c_x = isTurboR ? 255 : 0;
4045  WRITE_PORT(getBC(), out_c_x, T::CC_OUT_C_R_1);
4046  return {1, T::CC_OUT_C_R};
4047 }
4048 
4049 // OUT (n),a
4050 template<class T> II CPUCore<T>::out_byte_a() {
4051  byte port = RDMEM_OPCODE<1>(T::CC_OUT_N_A_1);
4052  unsigned y = (getA() << 8) | port;
4053  T::setMemPtr((getA() << 8) | ((port + 1) & 255));
4054  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_N_A_2);
4055  WRITE_PORT(y, getA(), T::CC_OUT_N_A_2);
4056  return {2, T::CC_OUT_N_A};
4057 }
4058 
4059 
4060 // block CP
4061 template<class T> inline II CPUCore<T>::BLOCK_CP(int increase, bool repeat) {
4062  T::setMemPtr(T::getMemPtr() + increase);
4063  byte val = RDMEM(getHL(), T::CC_CPI_1);
4064  byte res = getA() - val;
4065  setHL(getHL() + increase);
4066  setBC(getBC() - 1);
4067  byte f = ((getA() ^ val ^ res) & H_FLAG) |
4068  table.ZS[res] |
4069  N_FLAG |
4070  (getBC() ? V_FLAG : 0);
4071  if (T::isR800()) {
4072  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4073  } else {
4074  f |= getF() & C_FLAG;
4075  unsigned k = res - ((f & H_FLAG) >> 4);
4076  f |= (k << 4) & Y_FLAG; // bit 1 -> flag 5
4077  f |= k & X_FLAG; // bit 3 -> flag 3
4078  }
4079  setF(f);
4080  if (repeat && getBC() && res) {
4081  //setPC(getPC() - 2);
4082  T::setMemPtr(getPC() + 1);
4083  return {-1/*1*/, T::CC_CPIR};
4084  } else {
4085  return {1, T::CC_CPI};
4086  }
4087 }
4088 template<class T> II CPUCore<T>::cpd() { return BLOCK_CP(-1, false); }
4089 template<class T> II CPUCore<T>::cpi() { return BLOCK_CP( 1, false); }
4090 template<class T> II CPUCore<T>::cpdr() { return BLOCK_CP(-1, true ); }
4091 template<class T> II CPUCore<T>::cpir() { return BLOCK_CP( 1, true ); }
4092 
4093 
4094 // block LD
4095 template<class T> inline II CPUCore<T>::BLOCK_LD(int increase, bool repeat) {
4096  byte val = RDMEM(getHL(), T::CC_LDI_1);
4097  WRMEM(getDE(), val, T::CC_LDI_2);
4098  setHL(getHL() + increase);
4099  setDE(getDE() + increase);
4100  setBC(getBC() - 1);
4101  byte f = getBC() ? V_FLAG : 0;
4102  if (T::isR800()) {
4103  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG | X_FLAG | Y_FLAG);
4104  } else {
4105  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG);
4106  f |= ((getA() + val) << 4) & Y_FLAG; // bit 1 -> flag 5
4107  f |= (getA() + val) & X_FLAG; // bit 3 -> flag 3
4108  }
4109  setF(f);
4110  if (repeat && getBC()) {
4111  //setPC(getPC() - 2);
4112  T::setMemPtr(getPC() + 1);
4113  return {-1/*1*/, T::CC_LDIR};
4114  } else {
4115  return {1, T::CC_LDI};
4116  }
4117 }
4118 template<class T> II CPUCore<T>::ldd() { return BLOCK_LD(-1, false); }
4119 template<class T> II CPUCore<T>::ldi() { return BLOCK_LD( 1, false); }
4120 template<class T> II CPUCore<T>::lddr() { return BLOCK_LD(-1, true ); }
4121 template<class T> II CPUCore<T>::ldir() { return BLOCK_LD( 1, true ); }
4122 
4123 
4124 // block IN
4125 template<class T> inline II CPUCore<T>::BLOCK_IN(int increase, bool repeat) {
4126  // TODO R800 flags
4127  if (T::isR800()) T::waitForEvenCycle(T::CC_INI_1);
4128  T::setMemPtr(getBC() + increase);
4129  setBC(getBC() - 0x100); // decr before use
4130  byte val = READ_PORT(getBC(), T::CC_INI_1);
4131  WRMEM(getHL(), val, T::CC_INI_2);
4132  setHL(getHL() + increase);
4133  unsigned k = val + ((getC() + increase) & 0xFF);
4134  byte b = getB();
4135  setF(((val & S_FLAG) >> 6) | // N_FLAG
4136  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4137  table.ZSXY[b] |
4138  (table.ZSPXY[(k & 0x07) ^ b] & P_FLAG));
4139  if (repeat && b) {
4140  //setPC(getPC() - 2);
4141  return {-1/*1*/, T::CC_INIR};
4142  } else {
4143  return {1, T::CC_INI};
4144  }
4145 }
4146 template<class T> II CPUCore<T>::ind() { return BLOCK_IN(-1, false); }
4147 template<class T> II CPUCore<T>::ini() { return BLOCK_IN( 1, false); }
4148 template<class T> II CPUCore<T>::indr() { return BLOCK_IN(-1, true ); }
4149 template<class T> II CPUCore<T>::inir() { return BLOCK_IN( 1, true ); }
4150 
4151 
4152 // block OUT
4153 template<class T> inline II CPUCore<T>::BLOCK_OUT(int increase, bool repeat) {
4154  // TODO R800 flags
4155  byte val = RDMEM(getHL(), T::CC_OUTI_1);
4156  setHL(getHL() + increase);
4157  if (T::isR800()) T::waitForEvenCycle(T::CC_OUTI_2);
4158  WRITE_PORT(getBC(), val, T::CC_OUTI_2);
4159  setBC(getBC() - 0x100); // decr after use
4160  T::setMemPtr(getBC() + increase);
4161  unsigned k = val + getL();
4162  byte b = getB();
4163  setF(((val & S_FLAG) >> 6) | // N_FLAG
4164  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4165  table.ZSXY[b] |
4166  (table.ZSPXY[(k & 0x07) ^ b] & P_FLAG));
4167  if (repeat && b) {
4168  //setPC(getPC() - 2);
4169  return {-1/*1*/, T::CC_OTIR};
4170  } else {
4171  return {1, T::CC_OUTI};
4172  }
4173 }
4174 template<class T> II CPUCore<T>::outd() { return BLOCK_OUT(-1, false); }
4175 template<class T> II CPUCore<T>::outi() { return BLOCK_OUT( 1, false); }
4176 template<class T> II CPUCore<T>::otdr() { return BLOCK_OUT(-1, true ); }
4177 template<class T> II CPUCore<T>::otir() { return BLOCK_OUT( 1, true ); }
4178 
4179 
4180 // various
4181 template<class T> II CPUCore<T>::nop() { return {1, T::CC_NOP}; }
4182 template<class T> II CPUCore<T>::ccf() {
4183  byte f = 0;
4184  if (T::isR800()) {
4185  // H flag is different from Z80 (and as always XY flags as well)
4186  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | X_FLAG | Y_FLAG | H_FLAG);
4187  } else {
4188  f |= (getF() & C_FLAG) << 4; // H_FLAG
4189  // only set X(Y) flag (don't reset if already set)
4190  if (isTurboR) {
4191  // Y flag is not changed on a turboR-Z80
4192  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | Y_FLAG);
4193  f |= (getF() | getA()) & X_FLAG;
4194  } else {
4195  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4196  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4197  }
4198  }
4199  f ^= C_FLAG;
4200  setF(f);
4201  return {1, T::CC_CCF};
4202 }
4203 template<class T> II CPUCore<T>::cpl() {
4204  setA(getA() ^ 0xFF);
4205  byte f = H_FLAG | N_FLAG;
4206  if (T::isR800()) {
4207  f |= getF();
4208  } else {
4209  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4210  f |= getA() & (X_FLAG | Y_FLAG);
4211  }
4212  setF(f);
4213  return {1, T::CC_CPL};
4214 }
4215 template<class T> II CPUCore<T>::daa() {
4216  byte a = getA();
4217  byte f = getF();
4218  byte adjust = 0;
4219  if ((f & H_FLAG) || ((getA() & 0xf) > 9)) adjust += 6;
4220  if ((f & C_FLAG) || (getA() > 0x99)) adjust += 0x60;
4221  if (f & N_FLAG) a -= adjust; else a += adjust;
4222  if (T::isR800()) {
4223  f &= C_FLAG | N_FLAG | X_FLAG | Y_FLAG;
4224  f |= table.ZSP[a];
4225  } else {
4226  f &= C_FLAG | N_FLAG;
4227  f |= table.ZSPXY[a];
4228  }
4229  f |= (getA() > 0x99) | ((getA() ^ a) & H_FLAG);
4230  setA(a);
4231  setF(f);
4232  return {1, T::CC_DAA};
4233 }
4234 template<class T> II CPUCore<T>::neg() {
4235  // alternative: LUT word negTable[256]
4236  unsigned a = getA();
4237  unsigned res = -signed(a);
4238  byte f = ((res & 0x100) ? C_FLAG : 0) |
4239  N_FLAG |
4240  ((res ^ a) & H_FLAG) |
4241  ((a & res & 0x80) >> 5); // V_FLAG
4242  if (T::isR800()) {
4243  f |= table.ZS[res & 0xFF];
4244  f |= getF() & (X_FLAG | Y_FLAG);
4245  } else {
4246  f |= table.ZSXY[res & 0xFF];
4247  }
4248  setF(f);
4249  setA(res);
4250  return {1, T::CC_NEG};
4251 }
4252 template<class T> II CPUCore<T>::scf() {
4253  byte f = C_FLAG;
4254  if (T::isR800()) {
4255  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
4256  } else {
4257  // only set X(Y) flag (don't reset if already set)
4258  if (isTurboR) {
4259  // Y flag is not changed on a turboR-Z80
4260  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | Y_FLAG);
4261  f |= (getF() | getA()) & X_FLAG;
4262  } else {
4263  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
4264  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4265  }
4266  }
4267  setF(f);
4268  return {1, T::CC_SCF};
4269 }
4270 
4271 template<class T> II CPUCore<T>::ex_af_af() {
4272  unsigned t = getAF2(); setAF2(getAF()); setAF(t);
4273  return {1, T::CC_EX};
4274 }
4275 template<class T> II CPUCore<T>::ex_de_hl() {
4276  unsigned t = getDE(); setDE(getHL()); setHL(t);
4277  return {1, T::CC_EX};
4278 }
4279 template<class T> II CPUCore<T>::exx() {
4280  unsigned t1 = getBC2(); setBC2(getBC()); setBC(t1);
4281  unsigned t2 = getDE2(); setDE2(getDE()); setDE(t2);
4282  unsigned t3 = getHL2(); setHL2(getHL()); setHL(t3);
4283  return {1, T::CC_EX};
4284 }
4285 
4286 template<class T> II CPUCore<T>::di() {
4287  setIFF1(false);
4288  setIFF2(false);
4289  return {1, T::CC_DI};
4290 }
4291 template<class T> II CPUCore<T>::ei() {
4292  setIFF1(true);
4293  setIFF2(true);
4294  setCurrentEI(); // no ints directly after this instr
4295  setSlowInstructions();
4296  return {1, T::CC_EI};
4297 }
4298 template<class T> II CPUCore<T>::halt() {
4299  setHALT(true);
4300  setSlowInstructions();
4301 
4302  if (!(getIFF1() || getIFF2())) {
4303  diHaltCallback.execute();
4304  }
4305  return {1, T::CC_HALT};
4306 }
4307 template<class T> template<unsigned N> II CPUCore<T>::im_N() {
4308  setIM(N); return {1, T::CC_IM};
4309 }
4310 
4311 // LD A,I/R
4312 template<class T> template<Reg8 REG> II CPUCore<T>::ld_a_IR() {
4313  setA(get8<REG>());
4314  byte f = getIFF2() ? V_FLAG : 0;
4315  if (T::isR800()) {
4316  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4317  f |= table.ZS[getA()];
4318  } else {
4319  f |= getF() & C_FLAG;
4320  f |= table.ZSXY[getA()];
4321  // see comment in the IRQ acceptance part of executeSlow().
4322  setCurrentLDAI(); // only Z80 (not R800) has this quirk
4323  setSlowInstructions();
4324  }
4325  setF(f);
4326  return {1, T::CC_LD_A_I};
4327 }
4328 
4329 // LD I/R,A
4330 template<class T> II CPUCore<T>::ld_r_a() {
4331  // This code sequence:
4332  // XOR A / LD R,A / LD A,R
4333  // gives A=2 for Z80, but A=1 for R800. The difference can possibly be
4334  // explained by a difference in the relative time between writing the
4335  // new value to the R register and increasing the R register per M1
4336  // cycle. Here we implemented the R800 behaviour by storing 'A-1' into
4337  // R, that's good enough for now.
4338  byte val = getA();
4339  if (T::isR800()) val -= 1;
4340  setR(val);
4341  return {1, T::CC_LD_A_I};
4342 }
4343 template<class T> II CPUCore<T>::ld_i_a() {
4344  setI(getA());
4345  return {1, T::CC_LD_A_I};
4346 }
4347 
4348 // MULUB A,r
4349 template<class T> template<Reg8 REG> II CPUCore<T>::mulub_a_R() {
4350  assert(T::isR800()); // this instruction is R800-only
4351  // Verified on real R800:
4352  // YHXN flags are unchanged
4353  // SV flags are reset
4354  // Z flag is set when result is zero
4355  // C flag is set when result doesn't fit in 8-bit
4356  setHL(unsigned(getA()) * get8<REG>());
4357  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4358  0 | // S_FLAG V_FLAG
4359  (getHL() ? 0 : Z_FLAG) |
4360  ((getHL() & 0xFF00) ? C_FLAG : 0));
4361  return {1, T::CC_MULUB};
4362 }
4363 
4364 // MULUW HL,ss
4365 template<class T> template<Reg16 REG> II CPUCore<T>::muluw_hl_SS() {
4366  assert(T::isR800()); // this instruction is R800-only
4367  // Verified on real R800:
4368  // YHXN flags are unchanged
4369  // SV flags are reset
4370  // Z flag is set when result is zero
4371  // C flag is set when result doesn't fit in 16-bit
4372  unsigned res = unsigned(getHL()) * get16<REG>();
4373  setDE(res >> 16);
4374  setHL(res & 0xffff);
4375  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4376  0 | // S_FLAG V_FLAG
4377  (res ? 0 : Z_FLAG) |
4378  ((res & 0xFFFF0000) ? C_FLAG : 0));
4379  return {1, T::CC_MULUW};
4380 }
4381 
4382 
4383 // versions:
4384 // 1 -> initial version
4385 // 2 -> moved memptr from here to Z80TYPE (and not to R800TYPE)
4386 // 3 -> timing of the emulation changed (no changes in serialization)
4387 // 4 -> timing of the emulation changed again (see doc/internal/r800-call.txt)
4388 // 5 -> added serialization of nmiEdge
4389 template<class T> template<typename Archive>
4390 void CPUCore<T>::serialize(Archive& ar, unsigned version)
4391 {
4392  T::serialize(ar, version);
4393  ar.serialize("regs", static_cast<CPURegs&>(*this));
4394  if (ar.versionBelow(version, 2)) {
4395  unsigned mptr = 0; // dummy value (avoid warning)
4396  ar.serialize("memptr", mptr);
4397  T::setMemPtr(mptr);
4398  }
4399 
4400  if (ar.versionBelow(version, 5)) {
4401  // NMI is unused on MSX and even on systems where it is used nmiEdge
4402  // is true only between the moment the NMI request comes in and the
4403  // moment the Z80 jumps to the NMI handler, so defaulting to false
4404  // is pretty safe.
4405  nmiEdge = false;
4406  } else {
4407  // CPU is deserialized after devices, so nmiEdge is restored to the
4408  // saved version even if IRQHelpers set it on deserialization.
4409  ar.serialize("nmiEdge", nmiEdge);
4410  }
4411 
4412  // Don't serialize:
4413  // - IRQStatus, NMIStatus:
4414  // the IRQHelper deserialization makes sure these get the right value
4415  // - slowInstructions, exitLoop:
4416  // serialization happens outside the CPU emulation loop
4417 
4418  if (T::isR800() && ar.versionBelow(version, 4)) {
4419  motherboard.getMSXCliComm().printWarning(
4420  "Loading an old savestate: the timing of the R800 "
4421  "emulation has changed. This may cause synchronization "
4422  "problems in replay.");
4423  }
4424 }
4425 
4426 // Force template instantiation
4427 template class CPUCore<Z80TYPE>;
4428 template class CPUCore<R800TYPE>;
4429 
4432 
4433 } // namespace openmsx
constexpr byte ZSP0
Definition: CPUCore.cc:229
#define CASE(X)
constexpr byte S_FLAG
Definition: CPUCore.cc:208
constexpr byte P_FLAG
Definition: CPUCore.cc:214
#define NEVER_INLINE
Definition: inline.hh:17
#define ALWAYS_INLINE
Definition: inline.hh:16
#define unlikely(x)
Definition: likely.hh:15
Definition: span.hh:34
uint8_t byte
8 bit unsigned integer
Definition: openmsx.hh:26
constexpr unsigned LOW
Definition: CacheLine.hh:9
unsigned dasm(const MSXCPUInterface &interf, word pc, byte buf[4], std::string &dest, EmuTime::param time)
Disassemble.
Definition: Dasm.cc:18
constexpr byte C_FLAG
Definition: CPUCore.cc:216
constexpr unsigned HIGH
Definition: CacheLine.hh:10
CPUCore(MSXMotherBoard &motherboard, const std::string &name, const BooleanSetting &traceSetting, TclCallback &diHaltCallback, EmuTime::param time)
Definition: CPUCore.cc:282
constexpr byte ZS0
Definition: CPUCore.cc:227
constexpr byte Y_FLAG
Definition: CPUCore.cc:210
bool operator()(byte f) const
Definition: CPUCore.cc:272
byte ZS[256]
Definition: CPUCore.cc:220
constexpr byte V_FLAG
Definition: CPUCore.cc:213
constexpr byte ZSXY255
Definition: CPUCore.cc:232
bool operator()(byte f) const
Definition: CPUCore.cc:273
#define NEXT
#define NEXT_STOP
constexpr unsigned BITS
Definition: CacheLine.hh:6
int cycles
Definition: CPUCore.hh:39
constexpr byte X_FLAG
Definition: CPUCore.cc:212
byte ZSPH[256]
Definition: CPUCore.cc:224
bool operator()(byte) const
Definition: CPUCore.cc:280
Thanks to enen for testing this on a real cartridge:
Definition: Autofire.cc:5
constexpr byte ZSPXY0
Definition: CPUCore.cc:230
constexpr byte ZSXY0
Definition: CPUCore.cc:228
constexpr Table table
Definition: CPUCore.cc:263
constexpr byte N_FLAG
Definition: CPUCore.cc:215
bool operator()(byte f) const
Definition: CPUCore.cc:279
uint16_t word
16 bit unsigned integer
Definition: openmsx.hh:29
void addListElement(T t)
Definition: TclObject.hh:121
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
Definition: serialize.hh:981
bool operator()(byte f) const
Definition: CPUCore.cc:276
bool operator()(byte f) const
Definition: CPUCore.cc:278
constexpr unsigned N
Definition: ResampleHQ.cc:224
bool operator()(byte f) const
Definition: CPUCore.cc:274
byte ZSP[256]
Definition: CPUCore.cc:222
#define NEXT_EI
#define likely(x)
Definition: likely.hh:14
constexpr byte H_FLAG
Definition: CPUCore.cc:211
constexpr byte ZS255
Definition: CPUCore.cc:231
constexpr KeyMatrixPosition x
Keyboard bindings.
Definition: Keyboard.cc:1377
std::string strCat(Ts &&...ts)
Definition: strCat.hh:573
bool operator()(byte f) const
Definition: CPUCore.cc:277
byte ZSXY[256]
Definition: CPUCore.cc:221
bool operator()(byte f) const
Definition: CPUCore.cc:275
byte ZSPXY[256]
Definition: CPUCore.cc:223
TclObject t
void serialize(Archive &ar, T &t, unsigned version)
bool isMainThread()
Returns true when called from the main thread.
Definition: Thread.cc:15
constexpr byte Z_FLAG
Definition: CPUCore.cc:209
constexpr AdjustTables adjust
Definition: Y8950.cc:204
#define UNREACHABLE
Definition: unreachable.hh:38