openMSX
CPUCore.cc
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1 // MEMORY EMULATION
2 // ----------------
3 //
4 // Memory access emulation is a very important part of the CPU emulation.
5 // Because they happen so frequently they really need to be executed as fast as
6 // possible otherwise they will completely bring down the speed of the CPU
7 // emulation.
8 //
9 // A very fast way to emulate memory accesses is by simply reading/writing to a
10 // 64kb array (for a 16-bit address space). Unfortunately this doesn't allow
11 // for memory mapped IO (MMIO). These are memory regions where read/writes
12 // trigger side effects, so where we need to execute device-specific code on
13 // read or writes. An alternative that does work with MMIO is for every access
14 // execute a virtual method call, (this is the approach taken by most current
15 // MSX emulators). Unfortunately this is also a lot slower.
16 //
17 // It is possible to combine the speed of array accesses with the flexibility
18 // of virtual methods. In openMSX it's implemened as follows: the 64kb address
19 // space is divided in 256 regions of 256 bytes (called cacheLines in the code
20 // below). For each such region we store a pointer, if this pointer is nullptr
21 // then we have to use the slow way (=virtual method call). If it is not nullptr,
22 // the pointer points to a block of memory that can be directly accessed. In
23 // some contexts accesses via the pointer are known as backdoor accesses while
24 // the accesses directly to the device are known as frontdoor accesses.
25 //
26 // We keep different pointers for read and write accesses. This allows to also
27 // implement ROMs efficiently: read is handled as regular RAM, but writes end
28 // up in some dummy memory region. This region is called 'unmappedWrite' in the
29 // code. There is also a special region 'unmappedRead', this region is filled
30 // with 0xFF and can be used to model (parts of) a device that don't react to
31 // reads (so reads return 0xFF).
32 //
33 // Because of bankswitching (the MSX slot select mechanism, but also e.g.
34 // MegaROM backswitching) the memory map as seen by the Z80 is not static. This
35 // means that the cacheLine pointers also need to change during runtime. To
36 // solve this we made the bankswitch code also responsible for invalidating the
37 // cacheLines of the switched region. These pointers are filled-in again in a
38 // lazy way: the first read or write to a cache line will first get this
39 // pointer (see getReadCacheLine() and getWriteCacheLine() in the code below),
40 // from then on this pointer is used for all further accesses to this region,
41 // until the cache is invalidated again.
42 //
43 //
44 // INSTRUCTION EMULATION
45 // ---------------------
46 //
47 // UPDATE: the 'threaded interpreter model' is not enabled by default
48 // main reason is the huge memory requirement while compiling
49 // and that it doesn't work on non-gcc compilers
50 //
51 // The current implementation is based on a 'threaded interpreter model'. In
52 // the text below I'll call the older implementation the 'traditional
53 // interpreter model'. From a very high level these two models look like this:
54 //
55 // Traditional model:
56 // while (!needExit()) {
57 // byte opcode = fetch(PC++);
58 // switch (opcode) {
59 // case 0x00: nop(); break;
60 // case 0x01: ld_bc_nn(); break;
61 // ...
62 // }
63 // }
64 //
65 // Threaded model:
66 // byte opcode = fetch(PC++); //
67 // goto *(table[opcode]); // fetch-and-dispatch
68 // // note: the goto * syntax is a gcc extension called computed-gotos
69 //
70 // op00: nop(); if (!needExit()) [fetch-and-dispatch];
71 // op01: ld_bc_nn(); if (!needExit()) [fetch-and-dispatch];
72 // ...
73 //
74 // In the first model there is a central place in the code that fetches (the
75 // first byte of) the instruction and based on this byte jumps to the
76 // appropriate routine. In the second model, this fetch-and-dispatch logic is
77 // duplicated at the end of each instruction.
78 //
79 // Typically the 'dispatch' part in above paragraph is implemented (either by
80 // the compiler or manually using computed goto's) via a jump table. Thus on
81 // assembler level via an indirect jump. For the host CPU it's hard to predict
82 // the destination address of such an indirect jump, certainly if there's only
83 // one such jump for all dispatching (the traditional model). If each
84 // instruction has its own indirect jump instruction (the threaded model), it
85 // becomes a bit easier, because often one particular z80 instructions is
86 // followed by a specific other z80 instruction (or one from a small subset).
87 // For example a z80 'cp' instruction is most likely followed by a 'conditional
88 // jump' z80 instruction. Modern CPUs are quite sensitive to
89 // branch-(mis)predictions, so the above optimization helps quite a lot. I
90 // measured a speedup of more than 10%!
91 //
92 // There is another advantage to the threaded model. Because also the
93 // needExit() test is duplicated for each instruction, it becomes possible to
94 // tweak it for individual instructions. But first let me explain this
95 // exit-test in more detail.
96 //
97 // These are the main reasons why the emulator should stop emulating CPU
98 // instructions:
99 // 1) When other devices than the CPU must be emulated (e.g. video frame
100 // rendering). In openMSX this is handled by the Scheduler class and
101 // actually we don't exit the CPU loop (anymore) for this. Instead we
102 // simply execute the device code as a subroutine. Each time right before
103 // we access an IO port or do a frontdoor memory access, there is a check
104 // whether we should emulate device code (search for schedule() in the code
105 // below).
106 // 2) To keep the inner CPU loop as fast as possible we don't check for IRQ,
107 // NMI or HALT status in this loop. Instead this condition is checked only
108 // once at the beginning outside of the loop (if there wasn't a pending IRQ
109 // on the first instruction there also won't be one on the second
110 // instruction, if all we did was emulating cpu instructions). Now when one
111 // of these conditions changes, we must exit the inner loop and re-evaluate
112 // them. For example after an EI instruction we must check the IRQ status
113 // again.
114 // 3) Various reasons like:
115 // * Z80/R800 switch
116 // * executing a Tcl command (could be a cpu-register debug read)
117 // * exit the emulator
118 // 4) 'once-in-a-while': To avoid threading problems and race conditions,
119 // several threads in openMSX only 'schedule' work that will later be
120 // executed by the main emulation thread. The main thread checks for such
121 // task outside of the cpu emulation loop. So once-in-a-while we need to
122 // exit the loop. The exact timing doesn't matter here because anyway the
123 // relative timing between threads is undefined.
124 // So for 1) we don't need to do anything (we don't actually exit). For 2) and
125 // 3) we need the exit the loop as soon as possible (right after the current
126 // instruction is finished). For 4) it's OK to exit 'eventually' (a few hundred
127 // z80 instructions late is still OK).
128 //
129 // Condition 2) is implemented with the 'slowInstructions' mechanism. Condition
130 // 3) via exitCPULoopSync() (may only get called by the main emulation thread)
131 // and condition 4) is implemented via exitCPULoopAsync() (can be called from
132 // any thread).
133 //
134 // Now back to the exit-test optimization: in the threaded model each
135 // instruction ends with:
136 //
137 // if (needExit()) return
138 // byte opcode = fetch(PC++);
139 // goto *(table[opcode]);
140 //
141 // And if we look in more detail at fetch():
142 //
143 // if (canDoBackdoor(addr)) {
144 // doBackdoorAccess(addr);
145 // } else {
146 // doFrontdoorAccess(addr);
147 // }
148 //
149 // So there are in fact two checks per instruction. This can be reduced to only
150 // one check with the following trick:
151 //
152 // !!!WRONG!!!
153 // In the past we optimized this to only check canDoBackdoor() (and make sure
154 // canDoBackdoor() returned false when needExit() would return true). This
155 // worked rather well, except for one case: when we exit the CPU loop we also
156 // check for pending Syncronization points. It is possible such a SyncPoint
157 // raises the IRQ line. So it is important to check for exit after every
158 // instruction, otherwise we would enter the IRQ routine a couple of
159 // instructions too late.
160 
161 #include "CPUCore.hh"
162 #include "MSXCPUInterface.hh"
163 #include "Scheduler.hh"
164 #include "MSXMotherBoard.hh"
165 #include "CliComm.hh"
166 #include "TclCallback.hh"
167 #include "Dasm.hh"
168 #include "Z80.hh"
169 #include "R800.hh"
170 #include "Thread.hh"
171 #include "endian.hh"
172 #include "likely.hh"
173 #include "inline.hh"
174 #include "unreachable.hh"
175 #include <iomanip>
176 #include <iostream>
177 #include <type_traits>
178 #include <cassert>
179 #include <cstring>
180 
181 
182 //
183 // #define USE_COMPUTED_GOTO
184 //
185 // Computed goto's are not enabled by default:
186 // - Computed goto's are a gcc extension, it's not part of the official c++
187 // standard. So this will only work if you use gcc as your compiler (it
188 // won't work with visual c++ for example)
189 // - This is only beneficial on CPUs with branch prediction for indirect jumps
190 // and a reasonable amout of cache. For example it is very benefical for a
191 // intel core2 cpu (10% faster), but not for a ARM920 (a few percent slower)
192 // - Compiling src/cpu/CPUCore.cc with computed goto's enabled is very demanding
193 // on the compiler. On older gcc versions it requires up to 1.5GB of memory.
194 // But even on more recent gcc versions it still requires around 700MB.
195 //
196 // Probably the easiest way to enable this, is to pass the -DUSE_COMPUTED_GOTO
197 // flag to the compiler. This is for example done in the super-opt flavour.
198 // See build/flavour-super-opt.mk
199 
200 
201 using std::string;
202 
203 namespace openmsx {
204 
205 // This actually belongs in Z80.cc and R800.cc (these files don't exist yet).
206 // As a quick hack I put these two lines here because I found it overkill to
207 // create two files each containing only a single line.
208 // Technically these two lines _are_ required according to the c++ standard.
209 // Though usually it works just find without them, but during experiments I did
210 // get a link error when these lines were missing (it only happened during a
211 // debug build with some specific compiler version and only with some
212 // combination of other code changes, but again when strictly following the
213 // language rules, these lines should be here).
214 // ... But visual studio is not fully standard compliant, see also comment
215 // in SectorAccesibleDisk.cc
216 #ifndef _MSC_VER
217 const int Z80TYPE ::CLOCK_FREQ;
218 const int R800TYPE::CLOCK_FREQ;
219 #endif
220 
221 enum Reg8 : int { A, F, B, C, D, E, H, L, IXH, IXL, IYH, IYL, REG_I, REG_R, DUMMY };
222 enum Reg16 : int { AF, BC, DE, HL, IX, IY, SP };
223 
224 // flag positions
225 static const byte S_FLAG = 0x80;
226 static const byte Z_FLAG = 0x40;
227 static const byte Y_FLAG = 0x20;
228 static const byte H_FLAG = 0x10;
229 static const byte X_FLAG = 0x08;
230 static const byte V_FLAG = 0x04;
231 static const byte P_FLAG = V_FLAG;
232 static const byte N_FLAG = 0x02;
233 static const byte C_FLAG = 0x01;
234 
235 // flag-register tables, initialized at run-time
236 static byte ZSTable[256];
237 static byte ZSXYTable[256];
238 static byte ZSPTable[256];
239 static byte ZSPXYTable[256];
240 static byte ZSPHTable[256];
241 
242 static const byte ZS0 = Z_FLAG;
243 static const byte ZSXY0 = Z_FLAG;
244 static const byte ZSP0 = Z_FLAG | V_FLAG;
245 static const byte ZSPXY0 = Z_FLAG | V_FLAG;
246 static const byte ZS255 = S_FLAG;
247 static const byte ZSXY255 = S_FLAG | X_FLAG | Y_FLAG;
248 
249 // Global variable, because it should be shared between Z80 and R800.
250 // It must not be shared between the CPUs of different MSX machines, but
251 // the (logical) lifetime of this variable cannot overlap between execution
252 // of two MSX machines.
253 static word start_pc;
254 
255 // conditions
256 struct CondC { bool operator()(byte f) const { return (f & C_FLAG) != 0; } };
257 struct CondNC { bool operator()(byte f) const { return !(f & C_FLAG); } };
258 struct CondZ { bool operator()(byte f) const { return (f & Z_FLAG) != 0; } };
259 struct CondNZ { bool operator()(byte f) const { return !(f & Z_FLAG); } };
260 struct CondM { bool operator()(byte f) const { return (f & S_FLAG) != 0; } };
261 struct CondP { bool operator()(byte f) const { return !(f & S_FLAG); } };
262 struct CondPE { bool operator()(byte f) const { return (f & V_FLAG) != 0; } };
263 struct CondPO { bool operator()(byte f) const { return !(f & V_FLAG); } };
264 struct CondTrue { bool operator()(byte) const { return true; } };
265 
266 static void initTables()
267 {
268  static bool alreadyInit = false;
269  if (alreadyInit) return;
270  alreadyInit = true;
271 
272  for (int i = 0; i < 256; ++i) {
273  byte zFlag = (i == 0) ? Z_FLAG : 0;
274  byte sFlag = i & S_FLAG;
275  byte xFlag = i & X_FLAG;
276  byte yFlag = i & Y_FLAG;
277  byte vFlag = V_FLAG;
278  for (int v = 128; v != 0; v >>= 1) {
279  if (i & v) vFlag ^= V_FLAG;
280  }
281  ZSTable [i] = zFlag | sFlag;
282  ZSXYTable [i] = zFlag | sFlag | xFlag | yFlag;
283  ZSPTable [i] = zFlag | sFlag | vFlag;
284  ZSPXYTable[i] = zFlag | sFlag | xFlag | yFlag | vFlag;
285  ZSPHTable [i] = zFlag | sFlag | vFlag | H_FLAG;
286  }
287  assert(ZSTable [ 0] == ZS0);
288  assert(ZSXYTable [ 0] == ZSXY0);
289  assert(ZSPTable [ 0] == ZSP0);
290  assert(ZSPXYTable[ 0] == ZSPXY0);
291  assert(ZSTable [255] == ZS255);
292  assert(ZSXYTable [255] == ZSXY255);
293 }
294 
295 template<class T> CPUCore<T>::CPUCore(
296  MSXMotherBoard& motherboard_, const string& name,
297  const BooleanSetting& traceSetting_,
298  TclCallback& diHaltCallback_, EmuTime::param time)
299  : CPURegs(T::isR800())
300  , T(time, motherboard_.getScheduler())
301  , motherboard(motherboard_)
302  , scheduler(motherboard.getScheduler())
303  , interface(nullptr)
304  , traceSetting(traceSetting_)
305  , diHaltCallback(diHaltCallback_)
306  , IRQStatus(motherboard.getDebugger(), name + ".pendingIRQ",
307  "Non-zero if there are pending IRQs (thus CPU would enter "
308  "interrupt routine in EI mode).",
309  0)
310  , IRQAccept(motherboard.getDebugger(), name + ".acceptIRQ",
311  "This probe is only useful to set a breakpoint on (the value "
312  "return by read is meaningless). The breakpoint gets triggered "
313  "right after the CPU accepted an IRQ.")
314  , freqLocked(
315  motherboard.getCommandController(), name + "_freq_locked",
316  "real (locked) or custom (unlocked) " + name + " frequency",
317  true)
318  , freqValue(
319  motherboard.getCommandController(), name + "_freq",
320  "custom " + name + " frequency (only valid when unlocked)",
321  T::CLOCK_FREQ, 1000000, 1000000000)
322  , freq(T::CLOCK_FREQ)
323  , NMIStatus(0)
324  , nmiEdge(false)
325  , exitLoop(false)
326  , tracingEnabled(traceSetting.getBoolean())
327  , isTurboR(motherboard.isTurboR())
328 {
329  static_assert(!std::is_polymorphic<CPUCore<T>>::value,
330  "keep CPUCore non-virtual to keep PC at offset 0");
331  doSetFreq();
332  doReset(time);
333 
334  initTables();
335 }
336 
337 template<class T> void CPUCore<T>::warp(EmuTime::param time)
338 {
339  assert(T::getTimeFast() <= time);
340  T::setTime(time);
341 }
342 
344 {
345  return T::getTime();
346 }
347 
348 template<class T> void CPUCore<T>::invalidateMemCache(unsigned start, unsigned size)
349 {
350  unsigned first = start / CacheLine::SIZE;
351  unsigned num = (size + CacheLine::SIZE - 1) / CacheLine::SIZE;
352  memset(&readCacheLine [first], 0, num * sizeof(byte*)); // nullptr
353  memset(&writeCacheLine [first], 0, num * sizeof(byte*)); //
354  memset(&readCacheTried [first], 0, num * sizeof(bool)); // FALSE
355  memset(&writeCacheTried[first], 0, num * sizeof(bool)); //
356 }
357 
358 template<class T> void CPUCore<T>::doReset(EmuTime::param time)
359 {
360  // AF and SP are 0xFFFF
361  // PC, R, IFF1, IFF2, HALT and IM are 0x0
362  // all others are random
363  setAF(0xFFFF);
364  setBC(0xFFFF);
365  setDE(0xFFFF);
366  setHL(0xFFFF);
367  setIX(0xFFFF);
368  setIY(0xFFFF);
369  setPC(0x0000);
370  setSP(0xFFFF);
371  setAF2(0xFFFF);
372  setBC2(0xFFFF);
373  setDE2(0xFFFF);
374  setHL2(0xFFFF);
375  setIFF1(false);
376  setIFF2(false);
377  setHALT(false);
378  setExtHALT(false);
379  setIM(0);
380  setI(0x00);
381  setR(0x00);
382  T::setMemPtr(0xFFFF);
383  clearPrevious();
384  invalidateMemCache(0x0000, 0x10000);
385 
386  // We expect this assert to be valid
387  // assert(T::getTimeFast() <= time); // time shouldn't go backwards
388  // But it's disabled for the following reason:
389  // 'motion' (IRC nickname) managed to create a replay file that
390  // contains a reset command that falls in the middle of a Z80
391  // instruction. Replayed commands go via the Scheduler, and are
392  // (typically) executed right after a complete CPU instruction. So
393  // the CPU is (slightly) ahead in time of the about to be executed
394  // reset command.
395  // Normally this situation should never occur: console commands,
396  // hotkeys, commands over clicomm, ... are all handled via the global
397  // event mechanism. Such global events are scheduled between CPU
398  // instructions, so also in a replay they should fall between CPU
399  // instructions.
400  // However if for some reason the timing of the emulation changed
401  // (improved emulation accuracy or a bug so that emulation isn't
402  // deterministic or the replay file was edited, ...), then the above
403  // reasoning no longer holds and the assert can trigger.
404  // We need to be robust against loading older replays (when emulation
405  // timing has changed). So in that respect disabling the assert is
406  // good. Though in the example above (motion's replay) it's not clear
407  // whether the assert is really triggered by mixing an old replay
408  // with a newer openMSX version. In any case so far we haven't been
409  // able to reproduce this assert by recording and replaying using a
410  // single openMSX version.
411  T::setTime(time);
412 
413  assert(NMIStatus == 0); // other devices must reset their NMI source
414  assert(IRQStatus == 0); // other devices must reset their IRQ source
415 }
416 
417 // I believe the following two methods are thread safe even without any
418 // locking. The worst that can happen is that we occasionally needlessly
419 // exit the CPU loop, but that's harmless
420 // TODO thread issues are always tricky, can someone confirm this really
421 // is thread safe
422 template<class T> void CPUCore<T>::exitCPULoopAsync()
423 {
424  // can get called from non-main threads
425  exitLoop = true;
426 }
427 template<class T> void CPUCore<T>::exitCPULoopSync()
428 {
429  assert(Thread::isMainThread());
430  exitLoop = true;
431  T::disableLimit();
432 }
433 template<class T> inline bool CPUCore<T>::needExitCPULoop()
434 {
435  // always executed in main thread
436  if (unlikely(exitLoop)) {
437  // Note: The test-and-set is _not_ atomic! But that's fine.
438  // An atomic implementation is trivial (see below), but
439  // this version (at least on x86) avoids the more expensive
440  // instructions on the likely path.
441  exitLoop = false;
442  return true;
443  }
444  return false;
445 
446  // Alternative implementation:
447  // atomically set to false and return the old value
448  //return exitLoop.exchange(false);
449 }
450 
451 template<class T> void CPUCore<T>::setSlowInstructions()
452 {
453  slowInstructions = 2;
454  T::disableLimit();
455 }
456 
457 template<class T> void CPUCore<T>::raiseIRQ()
458 {
459  assert(IRQStatus >= 0);
460  if (IRQStatus == 0) {
461  setSlowInstructions();
462  }
463  IRQStatus = IRQStatus + 1;
464 }
465 
466 template<class T> void CPUCore<T>::lowerIRQ()
467 {
468  IRQStatus = IRQStatus - 1;
469  assert(IRQStatus >= 0);
470 }
471 
472 template<class T> void CPUCore<T>::raiseNMI()
473 {
474  // NMIs are currently disabled, they are anyway not used in MSX and
475  // not having to check for them allows to emulate slightly faster
476  UNREACHABLE;
477  assert(NMIStatus >= 0);
478  if (NMIStatus == 0) {
479  nmiEdge = true;
480  setSlowInstructions();
481  }
482  NMIStatus++;
483 }
484 
485 template<class T> void CPUCore<T>::lowerNMI()
486 {
487  NMIStatus--;
488  assert(NMIStatus >= 0);
489 }
490 
491 template<class T> bool CPUCore<T>::isM1Cycle(unsigned address) const
492 {
493  // PC was already increased, so decrease again
494  return address == ((getPC() - 1) & 0xFFFF);
495 }
496 
497 template<class T> void CPUCore<T>::wait(EmuTime::param time)
498 {
499  assert(time >= getCurrentTime());
500  scheduler.schedule(time);
501  T::advanceTime(time);
502 }
503 
504 template<class T> EmuTime CPUCore<T>::waitCycles(EmuTime::param time, unsigned cycles)
505 {
506  T::add(cycles);
507  EmuTime time2 = T::calcTime(time, cycles);
508  // note: time2 is not necessarily equal to T::getTime() because of the
509  // way how WRITE_PORT() is implemented.
510  scheduler.schedule(time2);
511  return time2;
512 }
513 
514 template<class T> void CPUCore<T>::setNextSyncPoint(EmuTime::param time)
515 {
516  T::setLimit(time);
517 }
518 
519 
520 static inline char toHex(byte x)
521 {
522  return (x < 10) ? (x + '0') : (x - 10 + 'A');
523 }
524 static void toHex(byte x, char* buf)
525 {
526  buf[0] = toHex(x / 16);
527  buf[1] = toHex(x & 15);
528 }
529 
530 template<class T> void CPUCore<T>::disasmCommand(
531  Interpreter& interp, array_ref<TclObject> tokens, TclObject& result) const
532 {
533  word address = (tokens.size() < 3) ? getPC() : tokens[2].getInt(interp);
534  byte outBuf[4];
535  std::string dasmOutput;
536  unsigned len = dasm(*interface, address, outBuf, dasmOutput,
537  T::getTimeFast());
538  result.addListElement(dasmOutput);
539  char tmp[3]; tmp[2] = 0;
540  for (unsigned i = 0; i < len; ++i) {
541  toHex(outBuf[i], tmp);
542  result.addListElement(tmp);
543  }
544 }
545 
546 template<class T> void CPUCore<T>::update(const Setting& setting)
547 {
548  if (&setting == &freqLocked) {
549  doSetFreq();
550  } else if (&setting == &freqValue) {
551  doSetFreq();
552  } else if (&setting == &traceSetting) {
553  tracingEnabled = traceSetting.getBoolean();
554  }
555 }
556 
557 template<class T> void CPUCore<T>::setFreq(unsigned freq_)
558 {
559  freq = freq_;
560  doSetFreq();
561 }
562 
563 template<class T> void CPUCore<T>::doSetFreq()
564 {
565  if (freqLocked.getBoolean()) {
566  // locked, use value set via setFreq()
567  T::setFreq(freq);
568  } else {
569  // unlocked, use value set by user
570  T::setFreq(freqValue.getInt());
571  }
572 }
573 
574 
575 template<class T> inline byte CPUCore<T>::READ_PORT(unsigned port, unsigned cc)
576 {
577  EmuTime time = T::getTimeFast(cc);
578  scheduler.schedule(time);
579  byte result = interface->readIO(port, time);
580  // note: no forced page-break after IO
581  return result;
582 }
583 
584 template<class T> inline void CPUCore<T>::WRITE_PORT(unsigned port, byte value, unsigned cc)
585 {
586  EmuTime time = T::getTimeFast(cc);
587  scheduler.schedule(time);
588  interface->writeIO(port, value, time);
589  // note: no forced page-break after IO
590 }
591 
592 template<class T> template<bool PRE_PB, bool POST_PB>
593 NEVER_INLINE byte CPUCore<T>::RDMEMslow(unsigned address, unsigned cc)
594 {
595  // not cached
596  unsigned high = address >> CacheLine::BITS;
597  if (!readCacheTried[high]) {
598  // try to cache now
599  unsigned addrBase = address & CacheLine::HIGH;
600  if (const byte* line = interface->getReadCacheLine(addrBase)) {
601  // cached ok
602  T::template PRE_MEM<PRE_PB, POST_PB>(address);
603  T::template POST_MEM< POST_PB>(address);
604  readCacheLine[high] = line - addrBase;
605  return readCacheLine[high][address];
606  }
607  }
608  // uncacheable
609  readCacheTried[high] = true;
610  T::template PRE_MEM<PRE_PB, POST_PB>(address);
611  EmuTime time = T::getTimeFast(cc);
612  scheduler.schedule(time);
613  byte result = interface->readMem(address, time);
614  T::template POST_MEM<POST_PB>(address);
615  return result;
616 }
617 template<class T> template<bool PRE_PB, bool POST_PB>
618 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl2(unsigned address, unsigned cc)
619 {
620  const byte* line = readCacheLine[address >> CacheLine::BITS];
621  if (likely(line != nullptr)) {
622  // cached, fast path
623  T::template PRE_MEM<PRE_PB, POST_PB>(address);
624  T::template POST_MEM< POST_PB>(address);
625  return line[address];
626  } else {
627  return RDMEMslow<PRE_PB, POST_PB>(address, cc); // not inlined
628  }
629 }
630 template<class T> template<bool PRE_PB, bool POST_PB>
631 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl(unsigned address, unsigned cc)
632 {
633  static const bool PRE = T::template Normalize<PRE_PB >::value;
634  static const bool POST = T::template Normalize<POST_PB>::value;
635  return RDMEM_impl2<PRE, POST>(address, cc);
636 }
637 template<class T> ALWAYS_INLINE byte CPUCore<T>::RDMEM_OPCODE(unsigned cc)
638 {
639  unsigned address = getPC();
640  setPC(address + 1);
641  return RDMEM_impl<false, false>(address, cc);
642 }
643 template<class T> ALWAYS_INLINE byte CPUCore<T>::RDMEM(unsigned address, unsigned cc)
644 {
645  return RDMEM_impl<true, true>(address, cc);
646 }
647 
648 template<class T> template<bool PRE_PB, bool POST_PB>
649 NEVER_INLINE unsigned CPUCore<T>::RD_WORD_slow(unsigned address, unsigned cc)
650 {
651  unsigned res = RDMEM_impl<PRE_PB, false>(address, cc);
652  res += RDMEM_impl<false, POST_PB>((address + 1) & 0xFFFF, cc + T::CC_RDMEM) << 8;
653  return res;
654 }
655 template<class T> template<bool PRE_PB, bool POST_PB>
656 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl2(unsigned address, unsigned cc)
657 {
658  const byte* line = readCacheLine[address >> CacheLine::BITS];
659  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
660  // fast path: cached and two bytes in same cache line
661  T::template PRE_WORD<PRE_PB, POST_PB>(address);
662  T::template POST_WORD< POST_PB>(address);
663  return Endian::read_UA_L16(&line[address]);
664  } else {
665  // slow path, not inline
666  return RD_WORD_slow<PRE_PB, POST_PB>(address, cc);
667  }
668 }
669 template<class T> template<bool PRE_PB, bool POST_PB>
670 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl(unsigned address, unsigned cc)
671 {
672  static const bool PRE = T::template Normalize<PRE_PB >::value;
673  static const bool POST = T::template Normalize<POST_PB>::value;
674  return RD_WORD_impl2<PRE, POST>(address, cc);
675 }
676 template<class T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_PC(unsigned cc)
677 {
678  unsigned addr = getPC();
679  setPC(addr + 2);
680  return RD_WORD_impl<false, false>(addr, cc);
681 }
682 template<class T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD(
683  unsigned address, unsigned cc)
684 {
685  return RD_WORD_impl<true, true>(address, cc);
686 }
687 
688 template<class T> template<bool PRE_PB, bool POST_PB>
689 NEVER_INLINE void CPUCore<T>::WRMEMslow(unsigned address, byte value, unsigned cc)
690 {
691  // not cached
692  unsigned high = address >> CacheLine::BITS;
693  if (!writeCacheTried[high]) {
694  // try to cache now
695  unsigned addrBase = address & CacheLine::HIGH;
696  if (byte* line = interface->getWriteCacheLine(addrBase)) {
697  // cached ok
698  T::template PRE_MEM<PRE_PB, POST_PB>(address);
699  T::template POST_MEM< POST_PB>(address);
700  writeCacheLine[high] = line - addrBase;
701  writeCacheLine[high][address] = value;
702  return;
703  }
704  }
705  // uncacheable
706  writeCacheTried[high] = true;
707  T::template PRE_MEM<PRE_PB, POST_PB>(address);
708  EmuTime time = T::getTimeFast(cc);
709  scheduler.schedule(time);
710  interface->writeMem(address, value, time);
711  T::template POST_MEM<POST_PB>(address);
712 }
713 template<class T> template<bool PRE_PB, bool POST_PB>
715  unsigned address, byte value, unsigned cc)
716 {
717  byte* line = writeCacheLine[address >> CacheLine::BITS];
718  if (likely(line != nullptr)) {
719  // cached, fast path
720  T::template PRE_MEM<PRE_PB, POST_PB>(address);
721  T::template POST_MEM< POST_PB>(address);
722  line[address] = value;
723  } else {
724  WRMEMslow<PRE_PB, POST_PB>(address, value, cc); // not inlined
725  }
726 }
727 template<class T> template<bool PRE_PB, bool POST_PB>
729  unsigned address, byte value, unsigned cc)
730 {
731  static const bool PRE = T::template Normalize<PRE_PB >::value;
732  static const bool POST = T::template Normalize<POST_PB>::value;
733  WRMEM_impl2<PRE, POST>(address, value, cc);
734 }
735 template<class T> ALWAYS_INLINE void CPUCore<T>::WRMEM(
736  unsigned address, byte value, unsigned cc)
737 {
738  WRMEM_impl<true, true>(address, value, cc);
739 }
740 
741 template<class T> NEVER_INLINE void CPUCore<T>::WR_WORD_slow(
742  unsigned address, unsigned value, unsigned cc)
743 {
744  WRMEM_impl<true, false>( address, value & 255, cc);
745  WRMEM_impl<false, true>((address + 1) & 0xFFFF, value >> 8, cc + T::CC_WRMEM);
746 }
747 template<class T> ALWAYS_INLINE void CPUCore<T>::WR_WORD(
748  unsigned address, unsigned value, unsigned cc)
749 {
750  byte* line = writeCacheLine[address >> CacheLine::BITS];
751  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
752  // fast path: cached and two bytes in same cache line
753  T::template PRE_WORD<true, true>(address);
754  T::template POST_WORD< true>(address);
755  Endian::write_UA_L16(&line[address], value);
756  } else {
757  // slow path, not inline
758  WR_WORD_slow(address, value, cc);
759  }
760 }
761 
762 // same as WR_WORD, but writes high byte first
763 template<class T> template<bool PRE_PB, bool POST_PB>
765  unsigned address, unsigned value, unsigned cc)
766 {
767  WRMEM_impl<PRE_PB, false>((address + 1) & 0xFFFF, value >> 8, cc);
768  WRMEM_impl<false, POST_PB>( address, value & 255, cc + T::CC_WRMEM);
769 }
770 template<class T> template<bool PRE_PB, bool POST_PB>
772  unsigned address, unsigned value, unsigned cc)
773 {
774  byte* line = writeCacheLine[address >> CacheLine::BITS];
775  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
776  // fast path: cached and two bytes in same cache line
777  T::template PRE_WORD<PRE_PB, POST_PB>(address);
778  T::template POST_WORD< POST_PB>(address);
779  Endian::write_UA_L16(&line[address], value);
780  } else {
781  // slow path, not inline
782  WR_WORD_rev_slow<PRE_PB, POST_PB>(address, value, cc);
783  }
784 }
785 template<class T> template<bool PRE_PB, bool POST_PB>
787  unsigned address, unsigned value, unsigned cc)
788 {
789  static const bool PRE = T::template Normalize<PRE_PB >::value;
790  static const bool POST = T::template Normalize<POST_PB>::value;
791  WR_WORD_rev2<PRE, POST>(address, value, cc);
792 }
793 
794 
795 // NMI interrupt
796 template<class T> inline void CPUCore<T>::nmi()
797 {
798  incR(1);
799  setHALT(false);
800  setIFF1(false);
801  PUSH<T::EE_NMI_1>(getPC());
802  setPC(0x0066);
803  T::add(T::CC_NMI);
804 }
805 
806 // IM0 interrupt
807 template<class T> inline void CPUCore<T>::irq0()
808 {
809  // TODO current implementation only works for 1-byte instructions
810  // ok for MSX
811  assert(interface->readIRQVector() == 0xFF);
812  incR(1);
813  setHALT(false);
814  setIFF1(false);
815  setIFF2(false);
816  PUSH<T::EE_IRQ0_1>(getPC());
817  setPC(0x0038);
818  T::setMemPtr(getPC());
819  T::add(T::CC_IRQ0);
820 }
821 
822 // IM1 interrupt
823 template<class T> inline void CPUCore<T>::irq1()
824 {
825  incR(1);
826  setHALT(false);
827  setIFF1(false);
828  setIFF2(false);
829  PUSH<T::EE_IRQ1_1>(getPC());
830  setPC(0x0038);
831  T::setMemPtr(getPC());
832  T::add(T::CC_IRQ1);
833 }
834 
835 // IM2 interrupt
836 template<class T> inline void CPUCore<T>::irq2()
837 {
838  incR(1);
839  setHALT(false);
840  setIFF1(false);
841  setIFF2(false);
842  PUSH<T::EE_IRQ2_1>(getPC());
843  unsigned x = interface->readIRQVector() | (getI() << 8);
844  setPC(RD_WORD(x, T::CC_IRQ2_2));
845  T::setMemPtr(getPC());
846  T::add(T::CC_IRQ2);
847 }
848 
849 template<class T>
851 {
853 #ifdef USE_COMPUTED_GOTO
854  // Addresses of all main-opcode routines,
855  // Note that 40/49/53/5B/64/6D/7F is replaced by 00 (ld r,r == nop)
856  static void* opcodeTable[256] = {
857  &&op00, &&op01, &&op02, &&op03, &&op04, &&op05, &&op06, &&op07,
858  &&op08, &&op09, &&op0A, &&op0B, &&op0C, &&op0D, &&op0E, &&op0F,
859  &&op10, &&op11, &&op12, &&op13, &&op14, &&op15, &&op16, &&op17,
860  &&op18, &&op19, &&op1A, &&op1B, &&op1C, &&op1D, &&op1E, &&op1F,
861  &&op20, &&op21, &&op22, &&op23, &&op24, &&op25, &&op26, &&op27,
862  &&op28, &&op29, &&op2A, &&op2B, &&op2C, &&op2D, &&op2E, &&op2F,
863  &&op30, &&op31, &&op32, &&op33, &&op34, &&op35, &&op36, &&op37,
864  &&op38, &&op39, &&op3A, &&op3B, &&op3C, &&op3D, &&op3E, &&op3F,
865  &&op00, &&op41, &&op42, &&op43, &&op44, &&op45, &&op46, &&op47,
866  &&op48, &&op00, &&op4A, &&op4B, &&op4C, &&op4D, &&op4E, &&op4F,
867  &&op50, &&op51, &&op00, &&op53, &&op54, &&op55, &&op56, &&op57,
868  &&op58, &&op59, &&op5A, &&op00, &&op5C, &&op5D, &&op5E, &&op5F,
869  &&op60, &&op61, &&op62, &&op63, &&op00, &&op65, &&op66, &&op67,
870  &&op68, &&op69, &&op6A, &&op6B, &&op6C, &&op00, &&op6E, &&op6F,
871  &&op70, &&op71, &&op72, &&op73, &&op74, &&op75, &&op76, &&op77,
872  &&op78, &&op79, &&op7A, &&op7B, &&op7C, &&op7D, &&op7E, &&op00,
873  &&op80, &&op81, &&op82, &&op83, &&op84, &&op85, &&op86, &&op87,
874  &&op88, &&op89, &&op8A, &&op8B, &&op8C, &&op8D, &&op8E, &&op8F,
875  &&op90, &&op91, &&op92, &&op93, &&op94, &&op95, &&op96, &&op97,
876  &&op98, &&op99, &&op9A, &&op9B, &&op9C, &&op9D, &&op9E, &&op9F,
877  &&opA0, &&opA1, &&opA2, &&opA3, &&opA4, &&opA5, &&opA6, &&opA7,
878  &&opA8, &&opA9, &&opAA, &&opAB, &&opAC, &&opAD, &&opAE, &&opAF,
879  &&opB0, &&opB1, &&opB2, &&opB3, &&opB4, &&opB5, &&opB6, &&opB7,
880  &&opB8, &&opB9, &&opBA, &&opBB, &&opBC, &&opBD, &&opBE, &&opBF,
881  &&opC0, &&opC1, &&opC2, &&opC3, &&opC4, &&opC5, &&opC6, &&opC7,
882  &&opC8, &&opC9, &&opCA, &&opCB, &&opCC, &&opCD, &&opCE, &&opCF,
883  &&opD0, &&opD1, &&opD2, &&opD3, &&opD4, &&opD5, &&opD6, &&opD7,
884  &&opD8, &&opD9, &&opDA, &&opDB, &&opDC, &&opDD, &&opDE, &&opDF,
885  &&opE0, &&opE1, &&opE2, &&opE3, &&opE4, &&opE5, &&opE6, &&opE7,
886  &&opE8, &&opE9, &&opEA, &&opEB, &&opEC, &&opED, &&opEE, &&opEF,
887  &&opF0, &&opF1, &&opF2, &&opF3, &&opF4, &&opF5, &&opF6, &&opF7,
888  &&opF8, &&opF9, &&opFA, &&opFB, &&opFC, &&opFD, &&opFE, &&opFF,
889  };
890 
891 // Check T::limitReached(). If it's OK to continue,
892 // fetch and execute next instruction.
893 #define NEXT \
894  T::add(c); \
895  T::R800Refresh(*this); \
896  if (likely(!T::limitReached())) { \
897  incR(1); \
898  unsigned address = getPC(); \
899  const byte* line = readCacheLine[address >> CacheLine::BITS]; \
900  if (likely(line != nullptr)) { \
901  setPC(address + 1); \
902  T::template PRE_MEM<false, false>(address); \
903  T::template POST_MEM< false>(address); \
904  byte op = line[address]; \
905  goto *(opcodeTable[op]); \
906  } else { \
907  goto fetchSlow; \
908  } \
909  } \
910  return;
911 
912 // After some instructions we must always exit the CPU loop (ei, halt, retn)
913 #define NEXT_STOP \
914  T::add(c); \
915  T::R800Refresh(*this); \
916  assert(T::limitReached()); \
917  return;
918 
919 #define NEXT_EI \
920  T::add(c); \
921  /* !! NO T::R800Refresh(*this); !! */ \
922  assert(T::limitReached()); \
923  return;
924 
925 // Define a label (instead of case in a switch statement)
926 #define CASE(X) op##X:
927 
928 #else // USE_COMPUTED_GOTO
929 
930 #define NEXT \
931  T::add(c); \
932  T::R800Refresh(*this); \
933  if (likely(!T::limitReached())) { \
934  goto start; \
935  } \
936  return;
937 
938 #define NEXT_STOP \
939  T::add(c); \
940  T::R800Refresh(*this); \
941  assert(T::limitReached()); \
942  return;
943 
944 #define NEXT_EI \
945  T::add(c); \
946  /* !! NO T::R800Refresh(*this); !! */ \
947  assert(T::limitReached()); \
948  return;
949 
950 #define CASE(X) case 0x##X:
951 
952 #endif // USE_COMPUTED_GOTO
953 
954 #ifndef USE_COMPUTED_GOTO
955 start:
956 #endif
957  unsigned ixy; // for dd_cb/fd_cb
958  byte opcodeMain = RDMEM_OPCODE(T::CC_MAIN);
959  incR(1);
960 #ifdef USE_COMPUTED_GOTO
961  goto *(opcodeTable[opcodeMain]);
962 
963 fetchSlow: {
964  unsigned address = getPC();
965  setPC(address + 1);
966  byte opcodeSlow = RDMEMslow<false, false>(address, T::CC_MAIN);
967  goto *(opcodeTable[opcodeSlow]);
968 }
969 #endif
970 
971 #ifndef USE_COMPUTED_GOTO
972 switchopcode:
973  switch (opcodeMain) {
974 CASE(40) // ld b,b
975 CASE(49) // ld c,c
976 CASE(52) // ld d,d
977 CASE(5B) // ld e,e
978 CASE(64) // ld h,h
979 CASE(6D) // ld l,l
980 CASE(7F) // ld a,a
981 #endif
982 CASE(00) { int c = nop(); NEXT; }
983 CASE(07) { int c = rlca(); NEXT; }
984 CASE(0F) { int c = rrca(); NEXT; }
985 CASE(17) { int c = rla(); NEXT; }
986 CASE(1F) { int c = rra(); NEXT; }
987 CASE(08) { int c = ex_af_af(); NEXT; }
988 CASE(27) { int c = daa(); NEXT; }
989 CASE(2F) { int c = cpl(); NEXT; }
990 CASE(37) { int c = scf(); NEXT; }
991 CASE(3F) { int c = ccf(); NEXT; }
992 CASE(20) { int c = jr(CondNZ()); NEXT; }
993 CASE(28) { int c = jr(CondZ ()); NEXT; }
994 CASE(30) { int c = jr(CondNC()); NEXT; }
995 CASE(38) { int c = jr(CondC ()); NEXT; }
996 CASE(18) { int c = jr(CondTrue()); NEXT; }
997 CASE(10) { int c = djnz(); NEXT; }
998 CASE(32) { int c = ld_xbyte_a(); NEXT; }
999 CASE(3A) { int c = ld_a_xbyte(); NEXT; }
1000 CASE(22) { int c = ld_xword_SS<HL,0>(); NEXT; }
1001 CASE(2A) { int c = ld_SS_xword<HL,0>(); NEXT; }
1002 CASE(02) { int c = ld_SS_a<BC>(); NEXT; }
1003 CASE(12) { int c = ld_SS_a<DE>(); NEXT; }
1004 CASE(1A) { int c = ld_a_SS<DE>(); NEXT; }
1005 CASE(0A) { int c = ld_a_SS<BC>(); NEXT; }
1006 CASE(03) { int c = inc_SS<BC,0>(); NEXT; }
1007 CASE(13) { int c = inc_SS<DE,0>(); NEXT; }
1008 CASE(23) { int c = inc_SS<HL,0>(); NEXT; }
1009 CASE(33) { int c = inc_SS<SP,0>(); NEXT; }
1010 CASE(0B) { int c = dec_SS<BC,0>(); NEXT; }
1011 CASE(1B) { int c = dec_SS<DE,0>(); NEXT; }
1012 CASE(2B) { int c = dec_SS<HL,0>(); NEXT; }
1013 CASE(3B) { int c = dec_SS<SP,0>(); NEXT; }
1014 CASE(09) { int c = add_SS_TT<HL,BC,0>(); NEXT; }
1015 CASE(19) { int c = add_SS_TT<HL,DE,0>(); NEXT; }
1016 CASE(29) { int c = add_SS_SS<HL ,0>(); NEXT; }
1017 CASE(39) { int c = add_SS_TT<HL,SP,0>(); NEXT; }
1018 CASE(01) { int c = ld_SS_word<BC,0>(); NEXT; }
1019 CASE(11) { int c = ld_SS_word<DE,0>(); NEXT; }
1020 CASE(21) { int c = ld_SS_word<HL,0>(); NEXT; }
1021 CASE(31) { int c = ld_SS_word<SP,0>(); NEXT; }
1022 CASE(04) { int c = inc_R<B,0>(); NEXT; }
1023 CASE(0C) { int c = inc_R<C,0>(); NEXT; }
1024 CASE(14) { int c = inc_R<D,0>(); NEXT; }
1025 CASE(1C) { int c = inc_R<E,0>(); NEXT; }
1026 CASE(24) { int c = inc_R<H,0>(); NEXT; }
1027 CASE(2C) { int c = inc_R<L,0>(); NEXT; }
1028 CASE(3C) { int c = inc_R<A,0>(); NEXT; }
1029 CASE(34) { int c = inc_xhl(); NEXT; }
1030 CASE(05) { int c = dec_R<B,0>(); NEXT; }
1031 CASE(0D) { int c = dec_R<C,0>(); NEXT; }
1032 CASE(15) { int c = dec_R<D,0>(); NEXT; }
1033 CASE(1D) { int c = dec_R<E,0>(); NEXT; }
1034 CASE(25) { int c = dec_R<H,0>(); NEXT; }
1035 CASE(2D) { int c = dec_R<L,0>(); NEXT; }
1036 CASE(3D) { int c = dec_R<A,0>(); NEXT; }
1037 CASE(35) { int c = dec_xhl(); NEXT; }
1038 CASE(06) { int c = ld_R_byte<B,0>(); NEXT; }
1039 CASE(0E) { int c = ld_R_byte<C,0>(); NEXT; }
1040 CASE(16) { int c = ld_R_byte<D,0>(); NEXT; }
1041 CASE(1E) { int c = ld_R_byte<E,0>(); NEXT; }
1042 CASE(26) { int c = ld_R_byte<H,0>(); NEXT; }
1043 CASE(2E) { int c = ld_R_byte<L,0>(); NEXT; }
1044 CASE(3E) { int c = ld_R_byte<A,0>(); NEXT; }
1045 CASE(36) { int c = ld_xhl_byte(); NEXT; }
1046 
1047 CASE(41) { int c = ld_R_R<B,C,0>(); NEXT; }
1048 CASE(42) { int c = ld_R_R<B,D,0>(); NEXT; }
1049 CASE(43) { int c = ld_R_R<B,E,0>(); NEXT; }
1050 CASE(44) { int c = ld_R_R<B,H,0>(); NEXT; }
1051 CASE(45) { int c = ld_R_R<B,L,0>(); NEXT; }
1052 CASE(47) { int c = ld_R_R<B,A,0>(); NEXT; }
1053 CASE(48) { int c = ld_R_R<C,B,0>(); NEXT; }
1054 CASE(4A) { int c = ld_R_R<C,D,0>(); NEXT; }
1055 CASE(4B) { int c = ld_R_R<C,E,0>(); NEXT; }
1056 CASE(4C) { int c = ld_R_R<C,H,0>(); NEXT; }
1057 CASE(4D) { int c = ld_R_R<C,L,0>(); NEXT; }
1058 CASE(4F) { int c = ld_R_R<C,A,0>(); NEXT; }
1059 CASE(50) { int c = ld_R_R<D,B,0>(); NEXT; }
1060 CASE(51) { int c = ld_R_R<D,C,0>(); NEXT; }
1061 CASE(53) { int c = ld_R_R<D,E,0>(); NEXT; }
1062 CASE(54) { int c = ld_R_R<D,H,0>(); NEXT; }
1063 CASE(55) { int c = ld_R_R<D,L,0>(); NEXT; }
1064 CASE(57) { int c = ld_R_R<D,A,0>(); NEXT; }
1065 CASE(58) { int c = ld_R_R<E,B,0>(); NEXT; }
1066 CASE(59) { int c = ld_R_R<E,C,0>(); NEXT; }
1067 CASE(5A) { int c = ld_R_R<E,D,0>(); NEXT; }
1068 CASE(5C) { int c = ld_R_R<E,H,0>(); NEXT; }
1069 CASE(5D) { int c = ld_R_R<E,L,0>(); NEXT; }
1070 CASE(5F) { int c = ld_R_R<E,A,0>(); NEXT; }
1071 CASE(60) { int c = ld_R_R<H,B,0>(); NEXT; }
1072 CASE(61) { int c = ld_R_R<H,C,0>(); NEXT; }
1073 CASE(62) { int c = ld_R_R<H,D,0>(); NEXT; }
1074 CASE(63) { int c = ld_R_R<H,E,0>(); NEXT; }
1075 CASE(65) { int c = ld_R_R<H,L,0>(); NEXT; }
1076 CASE(67) { int c = ld_R_R<H,A,0>(); NEXT; }
1077 CASE(68) { int c = ld_R_R<L,B,0>(); NEXT; }
1078 CASE(69) { int c = ld_R_R<L,C,0>(); NEXT; }
1079 CASE(6A) { int c = ld_R_R<L,D,0>(); NEXT; }
1080 CASE(6B) { int c = ld_R_R<L,E,0>(); NEXT; }
1081 CASE(6C) { int c = ld_R_R<L,H,0>(); NEXT; }
1082 CASE(6F) { int c = ld_R_R<L,A,0>(); NEXT; }
1083 CASE(78) { int c = ld_R_R<A,B,0>(); NEXT; }
1084 CASE(79) { int c = ld_R_R<A,C,0>(); NEXT; }
1085 CASE(7A) { int c = ld_R_R<A,D,0>(); NEXT; }
1086 CASE(7B) { int c = ld_R_R<A,E,0>(); NEXT; }
1087 CASE(7C) { int c = ld_R_R<A,H,0>(); NEXT; }
1088 CASE(7D) { int c = ld_R_R<A,L,0>(); NEXT; }
1089 CASE(70) { int c = ld_xhl_R<B>(); NEXT; }
1090 CASE(71) { int c = ld_xhl_R<C>(); NEXT; }
1091 CASE(72) { int c = ld_xhl_R<D>(); NEXT; }
1092 CASE(73) { int c = ld_xhl_R<E>(); NEXT; }
1093 CASE(74) { int c = ld_xhl_R<H>(); NEXT; }
1094 CASE(75) { int c = ld_xhl_R<L>(); NEXT; }
1095 CASE(77) { int c = ld_xhl_R<A>(); NEXT; }
1096 CASE(46) { int c = ld_R_xhl<B>(); NEXT; }
1097 CASE(4E) { int c = ld_R_xhl<C>(); NEXT; }
1098 CASE(56) { int c = ld_R_xhl<D>(); NEXT; }
1099 CASE(5E) { int c = ld_R_xhl<E>(); NEXT; }
1100 CASE(66) { int c = ld_R_xhl<H>(); NEXT; }
1101 CASE(6E) { int c = ld_R_xhl<L>(); NEXT; }
1102 CASE(7E) { int c = ld_R_xhl<A>(); NEXT; }
1103 CASE(76) { int c = halt(); NEXT_STOP; }
1104 
1105 CASE(80) { int c = add_a_R<B,0>(); NEXT; }
1106 CASE(81) { int c = add_a_R<C,0>(); NEXT; }
1107 CASE(82) { int c = add_a_R<D,0>(); NEXT; }
1108 CASE(83) { int c = add_a_R<E,0>(); NEXT; }
1109 CASE(84) { int c = add_a_R<H,0>(); NEXT; }
1110 CASE(85) { int c = add_a_R<L,0>(); NEXT; }
1111 CASE(86) { int c = add_a_xhl(); NEXT; }
1112 CASE(87) { int c = add_a_a(); NEXT; }
1113 CASE(88) { int c = adc_a_R<B,0>(); NEXT; }
1114 CASE(89) { int c = adc_a_R<C,0>(); NEXT; }
1115 CASE(8A) { int c = adc_a_R<D,0>(); NEXT; }
1116 CASE(8B) { int c = adc_a_R<E,0>(); NEXT; }
1117 CASE(8C) { int c = adc_a_R<H,0>(); NEXT; }
1118 CASE(8D) { int c = adc_a_R<L,0>(); NEXT; }
1119 CASE(8E) { int c = adc_a_xhl(); NEXT; }
1120 CASE(8F) { int c = adc_a_a(); NEXT; }
1121 CASE(90) { int c = sub_R<B,0>(); NEXT; }
1122 CASE(91) { int c = sub_R<C,0>(); NEXT; }
1123 CASE(92) { int c = sub_R<D,0>(); NEXT; }
1124 CASE(93) { int c = sub_R<E,0>(); NEXT; }
1125 CASE(94) { int c = sub_R<H,0>(); NEXT; }
1126 CASE(95) { int c = sub_R<L,0>(); NEXT; }
1127 CASE(96) { int c = sub_xhl(); NEXT; }
1128 CASE(97) { int c = sub_a(); NEXT; }
1129 CASE(98) { int c = sbc_a_R<B,0>(); NEXT; }
1130 CASE(99) { int c = sbc_a_R<C,0>(); NEXT; }
1131 CASE(9A) { int c = sbc_a_R<D,0>(); NEXT; }
1132 CASE(9B) { int c = sbc_a_R<E,0>(); NEXT; }
1133 CASE(9C) { int c = sbc_a_R<H,0>(); NEXT; }
1134 CASE(9D) { int c = sbc_a_R<L,0>(); NEXT; }
1135 CASE(9E) { int c = sbc_a_xhl(); NEXT; }
1136 CASE(9F) { int c = sbc_a_a(); NEXT; }
1137 CASE(A0) { int c = and_R<B,0>(); NEXT; }
1138 CASE(A1) { int c = and_R<C,0>(); NEXT; }
1139 CASE(A2) { int c = and_R<D,0>(); NEXT; }
1140 CASE(A3) { int c = and_R<E,0>(); NEXT; }
1141 CASE(A4) { int c = and_R<H,0>(); NEXT; }
1142 CASE(A5) { int c = and_R<L,0>(); NEXT; }
1143 CASE(A6) { int c = and_xhl(); NEXT; }
1144 CASE(A7) { int c = and_a(); NEXT; }
1145 CASE(A8) { int c = xor_R<B,0>(); NEXT; }
1146 CASE(A9) { int c = xor_R<C,0>(); NEXT; }
1147 CASE(AA) { int c = xor_R<D,0>(); NEXT; }
1148 CASE(AB) { int c = xor_R<E,0>(); NEXT; }
1149 CASE(AC) { int c = xor_R<H,0>(); NEXT; }
1150 CASE(AD) { int c = xor_R<L,0>(); NEXT; }
1151 CASE(AE) { int c = xor_xhl(); NEXT; }
1152 CASE(AF) { int c = xor_a(); NEXT; }
1153 CASE(B0) { int c = or_R<B,0>(); NEXT; }
1154 CASE(B1) { int c = or_R<C,0>(); NEXT; }
1155 CASE(B2) { int c = or_R<D,0>(); NEXT; }
1156 CASE(B3) { int c = or_R<E,0>(); NEXT; }
1157 CASE(B4) { int c = or_R<H,0>(); NEXT; }
1158 CASE(B5) { int c = or_R<L,0>(); NEXT; }
1159 CASE(B6) { int c = or_xhl(); NEXT; }
1160 CASE(B7) { int c = or_a(); NEXT; }
1161 CASE(B8) { int c = cp_R<B,0>(); NEXT; }
1162 CASE(B9) { int c = cp_R<C,0>(); NEXT; }
1163 CASE(BA) { int c = cp_R<D,0>(); NEXT; }
1164 CASE(BB) { int c = cp_R<E,0>(); NEXT; }
1165 CASE(BC) { int c = cp_R<H,0>(); NEXT; }
1166 CASE(BD) { int c = cp_R<L,0>(); NEXT; }
1167 CASE(BE) { int c = cp_xhl(); NEXT; }
1168 CASE(BF) { int c = cp_a(); NEXT; }
1169 
1170 CASE(D3) { int c = out_byte_a(); NEXT; }
1171 CASE(DB) { int c = in_a_byte(); NEXT; }
1172 CASE(D9) { int c = exx(); NEXT; }
1173 CASE(E3) { int c = ex_xsp_SS<HL,0>(); NEXT; }
1174 CASE(EB) { int c = ex_de_hl(); NEXT; }
1175 CASE(E9) { int c = jp_SS<HL,0>(); NEXT; }
1176 CASE(F9) { int c = ld_sp_SS<HL,0>(); NEXT; }
1177 CASE(F3) { int c = di(); NEXT; }
1178 CASE(FB) { int c = ei(); NEXT_EI; }
1179 CASE(C6) { int c = add_a_byte(); NEXT; }
1180 CASE(CE) { int c = adc_a_byte(); NEXT; }
1181 CASE(D6) { int c = sub_byte(); NEXT; }
1182 CASE(DE) { int c = sbc_a_byte(); NEXT; }
1183 CASE(E6) { int c = and_byte(); NEXT; }
1184 CASE(EE) { int c = xor_byte(); NEXT; }
1185 CASE(F6) { int c = or_byte(); NEXT; }
1186 CASE(FE) { int c = cp_byte(); NEXT; }
1187 CASE(C0) { int c = ret(CondNZ()); NEXT; }
1188 CASE(C8) { int c = ret(CondZ ()); NEXT; }
1189 CASE(D0) { int c = ret(CondNC()); NEXT; }
1190 CASE(D8) { int c = ret(CondC ()); NEXT; }
1191 CASE(E0) { int c = ret(CondPO()); NEXT; }
1192 CASE(E8) { int c = ret(CondPE()); NEXT; }
1193 CASE(F0) { int c = ret(CondP ()); NEXT; }
1194 CASE(F8) { int c = ret(CondM ()); NEXT; }
1195 CASE(C9) { int c = ret(); NEXT; }
1196 CASE(C2) { int c = jp(CondNZ()); NEXT; }
1197 CASE(CA) { int c = jp(CondZ ()); NEXT; }
1198 CASE(D2) { int c = jp(CondNC()); NEXT; }
1199 CASE(DA) { int c = jp(CondC ()); NEXT; }
1200 CASE(E2) { int c = jp(CondPO()); NEXT; }
1201 CASE(EA) { int c = jp(CondPE()); NEXT; }
1202 CASE(F2) { int c = jp(CondP ()); NEXT; }
1203 CASE(FA) { int c = jp(CondM ()); NEXT; }
1204 CASE(C3) { int c = jp(CondTrue()); NEXT; }
1205 CASE(C4) { int c = call(CondNZ()); NEXT; }
1206 CASE(CC) { int c = call(CondZ ()); NEXT; }
1207 CASE(D4) { int c = call(CondNC()); NEXT; }
1208 CASE(DC) { int c = call(CondC ()); NEXT; }
1209 CASE(E4) { int c = call(CondPO()); NEXT; }
1210 CASE(EC) { int c = call(CondPE()); NEXT; }
1211 CASE(F4) { int c = call(CondP ()); NEXT; }
1212 CASE(FC) { int c = call(CondM ()); NEXT; }
1213 CASE(CD) { int c = call(CondTrue()); NEXT; }
1214 CASE(C1) { int c = pop_SS <BC,0>(); NEXT; }
1215 CASE(D1) { int c = pop_SS <DE,0>(); NEXT; }
1216 CASE(E1) { int c = pop_SS <HL,0>(); NEXT; }
1217 CASE(F1) { int c = pop_SS <AF,0>(); NEXT; }
1218 CASE(C5) { int c = push_SS<BC,0>(); NEXT; }
1219 CASE(D5) { int c = push_SS<DE,0>(); NEXT; }
1220 CASE(E5) { int c = push_SS<HL,0>(); NEXT; }
1221 CASE(F5) { int c = push_SS<AF,0>(); NEXT; }
1222 CASE(C7) { int c = rst<0x00>(); NEXT; }
1223 CASE(CF) { int c = rst<0x08>(); NEXT; }
1224 CASE(D7) { int c = rst<0x10>(); NEXT; }
1225 CASE(DF) { int c = rst<0x18>(); NEXT; }
1226 CASE(E7) { int c = rst<0x20>(); NEXT; }
1227 CASE(EF) { int c = rst<0x28>(); NEXT; }
1228 CASE(F7) { int c = rst<0x30>(); NEXT; }
1229 CASE(FF) { int c = rst<0x38>(); NEXT; }
1230 CASE(CB) {
1231  byte cb_opcode = RDMEM_OPCODE(T::CC_PREFIX);
1232  incR(1);
1233  switch (cb_opcode) {
1234  case 0x00: { int c = rlc_R<B>(); NEXT; }
1235  case 0x01: { int c = rlc_R<C>(); NEXT; }
1236  case 0x02: { int c = rlc_R<D>(); NEXT; }
1237  case 0x03: { int c = rlc_R<E>(); NEXT; }
1238  case 0x04: { int c = rlc_R<H>(); NEXT; }
1239  case 0x05: { int c = rlc_R<L>(); NEXT; }
1240  case 0x07: { int c = rlc_R<A>(); NEXT; }
1241  case 0x06: { int c = rlc_xhl(); NEXT; }
1242  case 0x08: { int c = rrc_R<B>(); NEXT; }
1243  case 0x09: { int c = rrc_R<C>(); NEXT; }
1244  case 0x0a: { int c = rrc_R<D>(); NEXT; }
1245  case 0x0b: { int c = rrc_R<E>(); NEXT; }
1246  case 0x0c: { int c = rrc_R<H>(); NEXT; }
1247  case 0x0d: { int c = rrc_R<L>(); NEXT; }
1248  case 0x0f: { int c = rrc_R<A>(); NEXT; }
1249  case 0x0e: { int c = rrc_xhl(); NEXT; }
1250  case 0x10: { int c = rl_R<B>(); NEXT; }
1251  case 0x11: { int c = rl_R<C>(); NEXT; }
1252  case 0x12: { int c = rl_R<D>(); NEXT; }
1253  case 0x13: { int c = rl_R<E>(); NEXT; }
1254  case 0x14: { int c = rl_R<H>(); NEXT; }
1255  case 0x15: { int c = rl_R<L>(); NEXT; }
1256  case 0x17: { int c = rl_R<A>(); NEXT; }
1257  case 0x16: { int c = rl_xhl(); NEXT; }
1258  case 0x18: { int c = rr_R<B>(); NEXT; }
1259  case 0x19: { int c = rr_R<C>(); NEXT; }
1260  case 0x1a: { int c = rr_R<D>(); NEXT; }
1261  case 0x1b: { int c = rr_R<E>(); NEXT; }
1262  case 0x1c: { int c = rr_R<H>(); NEXT; }
1263  case 0x1d: { int c = rr_R<L>(); NEXT; }
1264  case 0x1f: { int c = rr_R<A>(); NEXT; }
1265  case 0x1e: { int c = rr_xhl(); NEXT; }
1266  case 0x20: { int c = sla_R<B>(); NEXT; }
1267  case 0x21: { int c = sla_R<C>(); NEXT; }
1268  case 0x22: { int c = sla_R<D>(); NEXT; }
1269  case 0x23: { int c = sla_R<E>(); NEXT; }
1270  case 0x24: { int c = sla_R<H>(); NEXT; }
1271  case 0x25: { int c = sla_R<L>(); NEXT; }
1272  case 0x27: { int c = sla_R<A>(); NEXT; }
1273  case 0x26: { int c = sla_xhl(); NEXT; }
1274  case 0x28: { int c = sra_R<B>(); NEXT; }
1275  case 0x29: { int c = sra_R<C>(); NEXT; }
1276  case 0x2a: { int c = sra_R<D>(); NEXT; }
1277  case 0x2b: { int c = sra_R<E>(); NEXT; }
1278  case 0x2c: { int c = sra_R<H>(); NEXT; }
1279  case 0x2d: { int c = sra_R<L>(); NEXT; }
1280  case 0x2f: { int c = sra_R<A>(); NEXT; }
1281  case 0x2e: { int c = sra_xhl(); NEXT; }
1282  case 0x30: { int c = T::isR800() ? sla_R<B>() : sll_R<B>(); NEXT; }
1283  case 0x31: { int c = T::isR800() ? sla_R<C>() : sll_R<C>(); NEXT; }
1284  case 0x32: { int c = T::isR800() ? sla_R<D>() : sll_R<D>(); NEXT; }
1285  case 0x33: { int c = T::isR800() ? sla_R<E>() : sll_R<E>(); NEXT; }
1286  case 0x34: { int c = T::isR800() ? sla_R<H>() : sll_R<H>(); NEXT; }
1287  case 0x35: { int c = T::isR800() ? sla_R<L>() : sll_R<L>(); NEXT; }
1288  case 0x37: { int c = T::isR800() ? sla_R<A>() : sll_R<A>(); NEXT; }
1289  case 0x36: { int c = T::isR800() ? sla_xhl() : sll_xhl(); NEXT; }
1290  case 0x38: { int c = srl_R<B>(); NEXT; }
1291  case 0x39: { int c = srl_R<C>(); NEXT; }
1292  case 0x3a: { int c = srl_R<D>(); NEXT; }
1293  case 0x3b: { int c = srl_R<E>(); NEXT; }
1294  case 0x3c: { int c = srl_R<H>(); NEXT; }
1295  case 0x3d: { int c = srl_R<L>(); NEXT; }
1296  case 0x3f: { int c = srl_R<A>(); NEXT; }
1297  case 0x3e: { int c = srl_xhl(); NEXT; }
1298 
1299  case 0x40: { int c = bit_N_R<0,B>(); NEXT; }
1300  case 0x41: { int c = bit_N_R<0,C>(); NEXT; }
1301  case 0x42: { int c = bit_N_R<0,D>(); NEXT; }
1302  case 0x43: { int c = bit_N_R<0,E>(); NEXT; }
1303  case 0x44: { int c = bit_N_R<0,H>(); NEXT; }
1304  case 0x45: { int c = bit_N_R<0,L>(); NEXT; }
1305  case 0x47: { int c = bit_N_R<0,A>(); NEXT; }
1306  case 0x48: { int c = bit_N_R<1,B>(); NEXT; }
1307  case 0x49: { int c = bit_N_R<1,C>(); NEXT; }
1308  case 0x4a: { int c = bit_N_R<1,D>(); NEXT; }
1309  case 0x4b: { int c = bit_N_R<1,E>(); NEXT; }
1310  case 0x4c: { int c = bit_N_R<1,H>(); NEXT; }
1311  case 0x4d: { int c = bit_N_R<1,L>(); NEXT; }
1312  case 0x4f: { int c = bit_N_R<1,A>(); NEXT; }
1313  case 0x50: { int c = bit_N_R<2,B>(); NEXT; }
1314  case 0x51: { int c = bit_N_R<2,C>(); NEXT; }
1315  case 0x52: { int c = bit_N_R<2,D>(); NEXT; }
1316  case 0x53: { int c = bit_N_R<2,E>(); NEXT; }
1317  case 0x54: { int c = bit_N_R<2,H>(); NEXT; }
1318  case 0x55: { int c = bit_N_R<2,L>(); NEXT; }
1319  case 0x57: { int c = bit_N_R<2,A>(); NEXT; }
1320  case 0x58: { int c = bit_N_R<3,B>(); NEXT; }
1321  case 0x59: { int c = bit_N_R<3,C>(); NEXT; }
1322  case 0x5a: { int c = bit_N_R<3,D>(); NEXT; }
1323  case 0x5b: { int c = bit_N_R<3,E>(); NEXT; }
1324  case 0x5c: { int c = bit_N_R<3,H>(); NEXT; }
1325  case 0x5d: { int c = bit_N_R<3,L>(); NEXT; }
1326  case 0x5f: { int c = bit_N_R<3,A>(); NEXT; }
1327  case 0x60: { int c = bit_N_R<4,B>(); NEXT; }
1328  case 0x61: { int c = bit_N_R<4,C>(); NEXT; }
1329  case 0x62: { int c = bit_N_R<4,D>(); NEXT; }
1330  case 0x63: { int c = bit_N_R<4,E>(); NEXT; }
1331  case 0x64: { int c = bit_N_R<4,H>(); NEXT; }
1332  case 0x65: { int c = bit_N_R<4,L>(); NEXT; }
1333  case 0x67: { int c = bit_N_R<4,A>(); NEXT; }
1334  case 0x68: { int c = bit_N_R<5,B>(); NEXT; }
1335  case 0x69: { int c = bit_N_R<5,C>(); NEXT; }
1336  case 0x6a: { int c = bit_N_R<5,D>(); NEXT; }
1337  case 0x6b: { int c = bit_N_R<5,E>(); NEXT; }
1338  case 0x6c: { int c = bit_N_R<5,H>(); NEXT; }
1339  case 0x6d: { int c = bit_N_R<5,L>(); NEXT; }
1340  case 0x6f: { int c = bit_N_R<5,A>(); NEXT; }
1341  case 0x70: { int c = bit_N_R<6,B>(); NEXT; }
1342  case 0x71: { int c = bit_N_R<6,C>(); NEXT; }
1343  case 0x72: { int c = bit_N_R<6,D>(); NEXT; }
1344  case 0x73: { int c = bit_N_R<6,E>(); NEXT; }
1345  case 0x74: { int c = bit_N_R<6,H>(); NEXT; }
1346  case 0x75: { int c = bit_N_R<6,L>(); NEXT; }
1347  case 0x77: { int c = bit_N_R<6,A>(); NEXT; }
1348  case 0x78: { int c = bit_N_R<7,B>(); NEXT; }
1349  case 0x79: { int c = bit_N_R<7,C>(); NEXT; }
1350  case 0x7a: { int c = bit_N_R<7,D>(); NEXT; }
1351  case 0x7b: { int c = bit_N_R<7,E>(); NEXT; }
1352  case 0x7c: { int c = bit_N_R<7,H>(); NEXT; }
1353  case 0x7d: { int c = bit_N_R<7,L>(); NEXT; }
1354  case 0x7f: { int c = bit_N_R<7,A>(); NEXT; }
1355  case 0x46: { int c = bit_N_xhl<0>(); NEXT; }
1356  case 0x4e: { int c = bit_N_xhl<1>(); NEXT; }
1357  case 0x56: { int c = bit_N_xhl<2>(); NEXT; }
1358  case 0x5e: { int c = bit_N_xhl<3>(); NEXT; }
1359  case 0x66: { int c = bit_N_xhl<4>(); NEXT; }
1360  case 0x6e: { int c = bit_N_xhl<5>(); NEXT; }
1361  case 0x76: { int c = bit_N_xhl<6>(); NEXT; }
1362  case 0x7e: { int c = bit_N_xhl<7>(); NEXT; }
1363 
1364  case 0x80: { int c = res_N_R<0,B>(); NEXT; }
1365  case 0x81: { int c = res_N_R<0,C>(); NEXT; }
1366  case 0x82: { int c = res_N_R<0,D>(); NEXT; }
1367  case 0x83: { int c = res_N_R<0,E>(); NEXT; }
1368  case 0x84: { int c = res_N_R<0,H>(); NEXT; }
1369  case 0x85: { int c = res_N_R<0,L>(); NEXT; }
1370  case 0x87: { int c = res_N_R<0,A>(); NEXT; }
1371  case 0x88: { int c = res_N_R<1,B>(); NEXT; }
1372  case 0x89: { int c = res_N_R<1,C>(); NEXT; }
1373  case 0x8a: { int c = res_N_R<1,D>(); NEXT; }
1374  case 0x8b: { int c = res_N_R<1,E>(); NEXT; }
1375  case 0x8c: { int c = res_N_R<1,H>(); NEXT; }
1376  case 0x8d: { int c = res_N_R<1,L>(); NEXT; }
1377  case 0x8f: { int c = res_N_R<1,A>(); NEXT; }
1378  case 0x90: { int c = res_N_R<2,B>(); NEXT; }
1379  case 0x91: { int c = res_N_R<2,C>(); NEXT; }
1380  case 0x92: { int c = res_N_R<2,D>(); NEXT; }
1381  case 0x93: { int c = res_N_R<2,E>(); NEXT; }
1382  case 0x94: { int c = res_N_R<2,H>(); NEXT; }
1383  case 0x95: { int c = res_N_R<2,L>(); NEXT; }
1384  case 0x97: { int c = res_N_R<2,A>(); NEXT; }
1385  case 0x98: { int c = res_N_R<3,B>(); NEXT; }
1386  case 0x99: { int c = res_N_R<3,C>(); NEXT; }
1387  case 0x9a: { int c = res_N_R<3,D>(); NEXT; }
1388  case 0x9b: { int c = res_N_R<3,E>(); NEXT; }
1389  case 0x9c: { int c = res_N_R<3,H>(); NEXT; }
1390  case 0x9d: { int c = res_N_R<3,L>(); NEXT; }
1391  case 0x9f: { int c = res_N_R<3,A>(); NEXT; }
1392  case 0xa0: { int c = res_N_R<4,B>(); NEXT; }
1393  case 0xa1: { int c = res_N_R<4,C>(); NEXT; }
1394  case 0xa2: { int c = res_N_R<4,D>(); NEXT; }
1395  case 0xa3: { int c = res_N_R<4,E>(); NEXT; }
1396  case 0xa4: { int c = res_N_R<4,H>(); NEXT; }
1397  case 0xa5: { int c = res_N_R<4,L>(); NEXT; }
1398  case 0xa7: { int c = res_N_R<4,A>(); NEXT; }
1399  case 0xa8: { int c = res_N_R<5,B>(); NEXT; }
1400  case 0xa9: { int c = res_N_R<5,C>(); NEXT; }
1401  case 0xaa: { int c = res_N_R<5,D>(); NEXT; }
1402  case 0xab: { int c = res_N_R<5,E>(); NEXT; }
1403  case 0xac: { int c = res_N_R<5,H>(); NEXT; }
1404  case 0xad: { int c = res_N_R<5,L>(); NEXT; }
1405  case 0xaf: { int c = res_N_R<5,A>(); NEXT; }
1406  case 0xb0: { int c = res_N_R<6,B>(); NEXT; }
1407  case 0xb1: { int c = res_N_R<6,C>(); NEXT; }
1408  case 0xb2: { int c = res_N_R<6,D>(); NEXT; }
1409  case 0xb3: { int c = res_N_R<6,E>(); NEXT; }
1410  case 0xb4: { int c = res_N_R<6,H>(); NEXT; }
1411  case 0xb5: { int c = res_N_R<6,L>(); NEXT; }
1412  case 0xb7: { int c = res_N_R<6,A>(); NEXT; }
1413  case 0xb8: { int c = res_N_R<7,B>(); NEXT; }
1414  case 0xb9: { int c = res_N_R<7,C>(); NEXT; }
1415  case 0xba: { int c = res_N_R<7,D>(); NEXT; }
1416  case 0xbb: { int c = res_N_R<7,E>(); NEXT; }
1417  case 0xbc: { int c = res_N_R<7,H>(); NEXT; }
1418  case 0xbd: { int c = res_N_R<7,L>(); NEXT; }
1419  case 0xbf: { int c = res_N_R<7,A>(); NEXT; }
1420  case 0x86: { int c = res_N_xhl<0>(); NEXT; }
1421  case 0x8e: { int c = res_N_xhl<1>(); NEXT; }
1422  case 0x96: { int c = res_N_xhl<2>(); NEXT; }
1423  case 0x9e: { int c = res_N_xhl<3>(); NEXT; }
1424  case 0xa6: { int c = res_N_xhl<4>(); NEXT; }
1425  case 0xae: { int c = res_N_xhl<5>(); NEXT; }
1426  case 0xb6: { int c = res_N_xhl<6>(); NEXT; }
1427  case 0xbe: { int c = res_N_xhl<7>(); NEXT; }
1428 
1429  case 0xc0: { int c = set_N_R<0,B>(); NEXT; }
1430  case 0xc1: { int c = set_N_R<0,C>(); NEXT; }
1431  case 0xc2: { int c = set_N_R<0,D>(); NEXT; }
1432  case 0xc3: { int c = set_N_R<0,E>(); NEXT; }
1433  case 0xc4: { int c = set_N_R<0,H>(); NEXT; }
1434  case 0xc5: { int c = set_N_R<0,L>(); NEXT; }
1435  case 0xc7: { int c = set_N_R<0,A>(); NEXT; }
1436  case 0xc8: { int c = set_N_R<1,B>(); NEXT; }
1437  case 0xc9: { int c = set_N_R<1,C>(); NEXT; }
1438  case 0xca: { int c = set_N_R<1,D>(); NEXT; }
1439  case 0xcb: { int c = set_N_R<1,E>(); NEXT; }
1440  case 0xcc: { int c = set_N_R<1,H>(); NEXT; }
1441  case 0xcd: { int c = set_N_R<1,L>(); NEXT; }
1442  case 0xcf: { int c = set_N_R<1,A>(); NEXT; }
1443  case 0xd0: { int c = set_N_R<2,B>(); NEXT; }
1444  case 0xd1: { int c = set_N_R<2,C>(); NEXT; }
1445  case 0xd2: { int c = set_N_R<2,D>(); NEXT; }
1446  case 0xd3: { int c = set_N_R<2,E>(); NEXT; }
1447  case 0xd4: { int c = set_N_R<2,H>(); NEXT; }
1448  case 0xd5: { int c = set_N_R<2,L>(); NEXT; }
1449  case 0xd7: { int c = set_N_R<2,A>(); NEXT; }
1450  case 0xd8: { int c = set_N_R<3,B>(); NEXT; }
1451  case 0xd9: { int c = set_N_R<3,C>(); NEXT; }
1452  case 0xda: { int c = set_N_R<3,D>(); NEXT; }
1453  case 0xdb: { int c = set_N_R<3,E>(); NEXT; }
1454  case 0xdc: { int c = set_N_R<3,H>(); NEXT; }
1455  case 0xdd: { int c = set_N_R<3,L>(); NEXT; }
1456  case 0xdf: { int c = set_N_R<3,A>(); NEXT; }
1457  case 0xe0: { int c = set_N_R<4,B>(); NEXT; }
1458  case 0xe1: { int c = set_N_R<4,C>(); NEXT; }
1459  case 0xe2: { int c = set_N_R<4,D>(); NEXT; }
1460  case 0xe3: { int c = set_N_R<4,E>(); NEXT; }
1461  case 0xe4: { int c = set_N_R<4,H>(); NEXT; }
1462  case 0xe5: { int c = set_N_R<4,L>(); NEXT; }
1463  case 0xe7: { int c = set_N_R<4,A>(); NEXT; }
1464  case 0xe8: { int c = set_N_R<5,B>(); NEXT; }
1465  case 0xe9: { int c = set_N_R<5,C>(); NEXT; }
1466  case 0xea: { int c = set_N_R<5,D>(); NEXT; }
1467  case 0xeb: { int c = set_N_R<5,E>(); NEXT; }
1468  case 0xec: { int c = set_N_R<5,H>(); NEXT; }
1469  case 0xed: { int c = set_N_R<5,L>(); NEXT; }
1470  case 0xef: { int c = set_N_R<5,A>(); NEXT; }
1471  case 0xf0: { int c = set_N_R<6,B>(); NEXT; }
1472  case 0xf1: { int c = set_N_R<6,C>(); NEXT; }
1473  case 0xf2: { int c = set_N_R<6,D>(); NEXT; }
1474  case 0xf3: { int c = set_N_R<6,E>(); NEXT; }
1475  case 0xf4: { int c = set_N_R<6,H>(); NEXT; }
1476  case 0xf5: { int c = set_N_R<6,L>(); NEXT; }
1477  case 0xf7: { int c = set_N_R<6,A>(); NEXT; }
1478  case 0xf8: { int c = set_N_R<7,B>(); NEXT; }
1479  case 0xf9: { int c = set_N_R<7,C>(); NEXT; }
1480  case 0xfa: { int c = set_N_R<7,D>(); NEXT; }
1481  case 0xfb: { int c = set_N_R<7,E>(); NEXT; }
1482  case 0xfc: { int c = set_N_R<7,H>(); NEXT; }
1483  case 0xfd: { int c = set_N_R<7,L>(); NEXT; }
1484  case 0xff: { int c = set_N_R<7,A>(); NEXT; }
1485  case 0xc6: { int c = set_N_xhl<0>(); NEXT; }
1486  case 0xce: { int c = set_N_xhl<1>(); NEXT; }
1487  case 0xd6: { int c = set_N_xhl<2>(); NEXT; }
1488  case 0xde: { int c = set_N_xhl<3>(); NEXT; }
1489  case 0xe6: { int c = set_N_xhl<4>(); NEXT; }
1490  case 0xee: { int c = set_N_xhl<5>(); NEXT; }
1491  case 0xf6: { int c = set_N_xhl<6>(); NEXT; }
1492  case 0xfe: { int c = set_N_xhl<7>(); NEXT; }
1493  default: UNREACHABLE; return;
1494  }
1495 }
1496 CASE(ED) {
1497  byte ed_opcode = RDMEM_OPCODE(T::CC_PREFIX);
1498  incR(1);
1499  switch (ed_opcode) {
1500  case 0x00: case 0x01: case 0x02: case 0x03:
1501  case 0x04: case 0x05: case 0x06: case 0x07:
1502  case 0x08: case 0x09: case 0x0a: case 0x0b:
1503  case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1504  case 0x10: case 0x11: case 0x12: case 0x13:
1505  case 0x14: case 0x15: case 0x16: case 0x17:
1506  case 0x18: case 0x19: case 0x1a: case 0x1b:
1507  case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1508  case 0x20: case 0x21: case 0x22: case 0x23:
1509  case 0x24: case 0x25: case 0x26: case 0x27:
1510  case 0x28: case 0x29: case 0x2a: case 0x2b:
1511  case 0x2c: case 0x2d: case 0x2e: case 0x2f:
1512  case 0x30: case 0x31: case 0x32: case 0x33:
1513  case 0x34: case 0x35: case 0x36: case 0x37:
1514  case 0x38: case 0x39: case 0x3a: case 0x3b:
1515  case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1516 
1517  case 0x77: case 0x7f:
1518 
1519  case 0x80: case 0x81: case 0x82: case 0x83:
1520  case 0x84: case 0x85: case 0x86: case 0x87:
1521  case 0x88: case 0x89: case 0x8a: case 0x8b:
1522  case 0x8c: case 0x8d: case 0x8e: case 0x8f:
1523  case 0x90: case 0x91: case 0x92: case 0x93:
1524  case 0x94: case 0x95: case 0x96: case 0x97:
1525  case 0x98: case 0x99: case 0x9a: case 0x9b:
1526  case 0x9c: case 0x9d: case 0x9e: case 0x9f:
1527  case 0xa4: case 0xa5: case 0xa6: case 0xa7:
1528  case 0xac: case 0xad: case 0xae: case 0xaf:
1529  case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1530  case 0xbc: case 0xbd: case 0xbe: case 0xbf:
1531 
1532  case 0xc0: case 0xc2:
1533  case 0xc4: case 0xc5: case 0xc6: case 0xc7:
1534  case 0xc8: case 0xca: case 0xcb:
1535  case 0xcc: case 0xcd: case 0xce: case 0xcf:
1536  case 0xd0: case 0xd2: case 0xd3:
1537  case 0xd4: case 0xd5: case 0xd6: case 0xd7:
1538  case 0xd8: case 0xda: case 0xdb:
1539  case 0xdc: case 0xdd: case 0xde: case 0xdf:
1540  case 0xe0: case 0xe1: case 0xe2: case 0xe3:
1541  case 0xe4: case 0xe5: case 0xe6: case 0xe7:
1542  case 0xe8: case 0xe9: case 0xea: case 0xeb:
1543  case 0xec: case 0xed: case 0xee: case 0xef:
1544  case 0xf0: case 0xf1: case 0xf2:
1545  case 0xf4: case 0xf5: case 0xf6: case 0xf7:
1546  case 0xf8: case 0xf9: case 0xfa: case 0xfb:
1547  case 0xfc: case 0xfd: case 0xfe: case 0xff:
1548  { int c = nop(); NEXT; }
1549 
1550  case 0x40: { int c = in_R_c<B>(); NEXT; }
1551  case 0x48: { int c = in_R_c<C>(); NEXT; }
1552  case 0x50: { int c = in_R_c<D>(); NEXT; }
1553  case 0x58: { int c = in_R_c<E>(); NEXT; }
1554  case 0x60: { int c = in_R_c<H>(); NEXT; }
1555  case 0x68: { int c = in_R_c<L>(); NEXT; }
1556  case 0x70: { int c = in_R_c<DUMMY>(); NEXT; }
1557  case 0x78: { int c = in_R_c<A>(); NEXT; }
1558 
1559  case 0x41: { int c = out_c_R<B>(); NEXT; }
1560  case 0x49: { int c = out_c_R<C>(); NEXT; }
1561  case 0x51: { int c = out_c_R<D>(); NEXT; }
1562  case 0x59: { int c = out_c_R<E>(); NEXT; }
1563  case 0x61: { int c = out_c_R<H>(); NEXT; }
1564  case 0x69: { int c = out_c_R<L>(); NEXT; }
1565  case 0x71: { int c = out_c_0(); NEXT; }
1566  case 0x79: { int c = out_c_R<A>(); NEXT; }
1567 
1568  case 0x42: { int c = sbc_hl_SS<BC>(); NEXT; }
1569  case 0x52: { int c = sbc_hl_SS<DE>(); NEXT; }
1570  case 0x62: { int c = sbc_hl_hl (); NEXT; }
1571  case 0x72: { int c = sbc_hl_SS<SP>(); NEXT; }
1572 
1573  case 0x4a: { int c = adc_hl_SS<BC>(); NEXT; }
1574  case 0x5a: { int c = adc_hl_SS<DE>(); NEXT; }
1575  case 0x6a: { int c = adc_hl_hl (); NEXT; }
1576  case 0x7a: { int c = adc_hl_SS<SP>(); NEXT; }
1577 
1578  case 0x43: { int c = ld_xword_SS_ED<BC>(); NEXT; }
1579  case 0x53: { int c = ld_xword_SS_ED<DE>(); NEXT; }
1580  case 0x63: { int c = ld_xword_SS_ED<HL>(); NEXT; }
1581  case 0x73: { int c = ld_xword_SS_ED<SP>(); NEXT; }
1582 
1583  case 0x4b: { int c = ld_SS_xword_ED<BC>(); NEXT; }
1584  case 0x5b: { int c = ld_SS_xword_ED<DE>(); NEXT; }
1585  case 0x6b: { int c = ld_SS_xword_ED<HL>(); NEXT; }
1586  case 0x7b: { int c = ld_SS_xword_ED<SP>(); NEXT; }
1587 
1588  case 0x47: { int c = ld_i_a(); NEXT; }
1589  case 0x4f: { int c = ld_r_a(); NEXT; }
1590  case 0x57: { int c = ld_a_IR<REG_I>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1591  case 0x5f: { int c = ld_a_IR<REG_R>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1592 
1593  case 0x67: { int c = rrd(); NEXT; }
1594  case 0x6f: { int c = rld(); NEXT; }
1595 
1596  case 0x45: case 0x4d: case 0x55: case 0x5d:
1597  case 0x65: case 0x6d: case 0x75: case 0x7d:
1598  { int c = retn(); NEXT_STOP; }
1599  case 0x46: case 0x4e: case 0x66: case 0x6e:
1600  { int c = im_N<0>(); NEXT; }
1601  case 0x56: case 0x76:
1602  { int c = im_N<1>(); NEXT; }
1603  case 0x5e: case 0x7e:
1604  { int c = im_N<2>(); NEXT; }
1605  case 0x44: case 0x4c: case 0x54: case 0x5c:
1606  case 0x64: case 0x6c: case 0x74: case 0x7c:
1607  { int c = neg(); NEXT; }
1608 
1609  case 0xa0: { int c = ldi(); NEXT; }
1610  case 0xa1: { int c = cpi(); NEXT; }
1611  case 0xa2: { int c = ini(); NEXT; }
1612  case 0xa3: { int c = outi(); NEXT; }
1613  case 0xa8: { int c = ldd(); NEXT; }
1614  case 0xa9: { int c = cpd(); NEXT; }
1615  case 0xaa: { int c = ind(); NEXT; }
1616  case 0xab: { int c = outd(); NEXT; }
1617  case 0xb0: { int c = ldir(); NEXT; }
1618  case 0xb1: { int c = cpir(); NEXT; }
1619  case 0xb2: { int c = inir(); NEXT; }
1620  case 0xb3: { int c = otir(); NEXT; }
1621  case 0xb8: { int c = lddr(); NEXT; }
1622  case 0xb9: { int c = cpdr(); NEXT; }
1623  case 0xba: { int c = indr(); NEXT; }
1624  case 0xbb: { int c = otdr(); NEXT; }
1625 
1626  case 0xc1: { int c = T::isR800() ? mulub_a_R<B>() : nop(); NEXT; }
1627  case 0xc9: { int c = T::isR800() ? mulub_a_R<C>() : nop(); NEXT; }
1628  case 0xd1: { int c = T::isR800() ? mulub_a_R<D>() : nop(); NEXT; }
1629  case 0xd9: { int c = T::isR800() ? mulub_a_R<E>() : nop(); NEXT; }
1630  case 0xc3: { int c = T::isR800() ? muluw_hl_SS<BC>() : nop(); NEXT; }
1631  case 0xf3: { int c = T::isR800() ? muluw_hl_SS<SP>() : nop(); NEXT; }
1632  default: UNREACHABLE; return;
1633  }
1634 }
1635 opDD_2:
1636 CASE(DD) {
1637  byte opcodeDD = RDMEM_OPCODE(T::CC_DD + T::CC_MAIN);
1638  incR(1);
1639  switch (opcodeDD) {
1640  case 0x00: // nop();
1641  case 0x01: // ld_bc_word();
1642  case 0x02: // ld_xbc_a();
1643  case 0x03: // inc_bc();
1644  case 0x04: // inc_b();
1645  case 0x05: // dec_b();
1646  case 0x06: // ld_b_byte();
1647  case 0x07: // rlca();
1648  case 0x08: // ex_af_af();
1649  case 0x0a: // ld_a_xbc();
1650  case 0x0b: // dec_bc();
1651  case 0x0c: // inc_c();
1652  case 0x0d: // dec_c();
1653  case 0x0e: // ld_c_byte();
1654  case 0x0f: // rrca();
1655  case 0x10: // djnz();
1656  case 0x11: // ld_de_word();
1657  case 0x12: // ld_xde_a();
1658  case 0x13: // inc_de();
1659  case 0x14: // inc_d();
1660  case 0x15: // dec_d();
1661  case 0x16: // ld_d_byte();
1662  case 0x17: // rla();
1663  case 0x18: // jr();
1664  case 0x1a: // ld_a_xde();
1665  case 0x1b: // dec_de();
1666  case 0x1c: // inc_e();
1667  case 0x1d: // dec_e();
1668  case 0x1e: // ld_e_byte();
1669  case 0x1f: // rra();
1670  case 0x20: // jr_nz();
1671  case 0x27: // daa();
1672  case 0x28: // jr_z();
1673  case 0x2f: // cpl();
1674  case 0x30: // jr_nc();
1675  case 0x31: // ld_sp_word();
1676  case 0x32: // ld_xbyte_a();
1677  case 0x33: // inc_sp();
1678  case 0x37: // scf();
1679  case 0x38: // jr_c();
1680  case 0x3a: // ld_a_xbyte();
1681  case 0x3b: // dec_sp();
1682  case 0x3c: // inc_a();
1683  case 0x3d: // dec_a();
1684  case 0x3e: // ld_a_byte();
1685  case 0x3f: // ccf();
1686 
1687  case 0x40: // ld_b_b();
1688  case 0x41: // ld_b_c();
1689  case 0x42: // ld_b_d();
1690  case 0x43: // ld_b_e();
1691  case 0x47: // ld_b_a();
1692  case 0x48: // ld_c_b();
1693  case 0x49: // ld_c_c();
1694  case 0x4a: // ld_c_d();
1695  case 0x4b: // ld_c_e();
1696  case 0x4f: // ld_c_a();
1697  case 0x50: // ld_d_b();
1698  case 0x51: // ld_d_c();
1699  case 0x52: // ld_d_d();
1700  case 0x53: // ld_d_e();
1701  case 0x57: // ld_d_a();
1702  case 0x58: // ld_e_b();
1703  case 0x59: // ld_e_c();
1704  case 0x5a: // ld_e_d();
1705  case 0x5b: // ld_e_e();
1706  case 0x5f: // ld_e_a();
1707  case 0x64: // ld_ixh_ixh(); == nop
1708  case 0x6d: // ld_ixl_ixl(); == nop
1709  case 0x76: // halt();
1710  case 0x78: // ld_a_b();
1711  case 0x79: // ld_a_c();
1712  case 0x7a: // ld_a_d();
1713  case 0x7b: // ld_a_e();
1714  case 0x7f: // ld_a_a();
1715 
1716  case 0x80: // add_a_b();
1717  case 0x81: // add_a_c();
1718  case 0x82: // add_a_d();
1719  case 0x83: // add_a_e();
1720  case 0x87: // add_a_a();
1721  case 0x88: // adc_a_b();
1722  case 0x89: // adc_a_c();
1723  case 0x8a: // adc_a_d();
1724  case 0x8b: // adc_a_e();
1725  case 0x8f: // adc_a_a();
1726  case 0x90: // sub_b();
1727  case 0x91: // sub_c();
1728  case 0x92: // sub_d();
1729  case 0x93: // sub_e();
1730  case 0x97: // sub_a();
1731  case 0x98: // sbc_a_b();
1732  case 0x99: // sbc_a_c();
1733  case 0x9a: // sbc_a_d();
1734  case 0x9b: // sbc_a_e();
1735  case 0x9f: // sbc_a_a();
1736  case 0xa0: // and_b();
1737  case 0xa1: // and_c();
1738  case 0xa2: // and_d();
1739  case 0xa3: // and_e();
1740  case 0xa7: // and_a();
1741  case 0xa8: // xor_b();
1742  case 0xa9: // xor_c();
1743  case 0xaa: // xor_d();
1744  case 0xab: // xor_e();
1745  case 0xaf: // xor_a();
1746  case 0xb0: // or_b();
1747  case 0xb1: // or_c();
1748  case 0xb2: // or_d();
1749  case 0xb3: // or_e();
1750  case 0xb7: // or_a();
1751  case 0xb8: // cp_b();
1752  case 0xb9: // cp_c();
1753  case 0xba: // cp_d();
1754  case 0xbb: // cp_e();
1755  case 0xbf: // cp_a();
1756 
1757  case 0xc0: // ret_nz();
1758  case 0xc1: // pop_bc();
1759  case 0xc2: // jp_nz();
1760  case 0xc3: // jp();
1761  case 0xc4: // call_nz();
1762  case 0xc5: // push_bc();
1763  case 0xc6: // add_a_byte();
1764  case 0xc7: // rst_00();
1765  case 0xc8: // ret_z();
1766  case 0xc9: // ret();
1767  case 0xca: // jp_z();
1768  case 0xcc: // call_z();
1769  case 0xcd: // call();
1770  case 0xce: // adc_a_byte();
1771  case 0xcf: // rst_08();
1772  case 0xd0: // ret_nc();
1773  case 0xd1: // pop_de();
1774  case 0xd2: // jp_nc();
1775  case 0xd3: // out_byte_a();
1776  case 0xd4: // call_nc();
1777  case 0xd5: // push_de();
1778  case 0xd6: // sub_byte();
1779  case 0xd7: // rst_10();
1780  case 0xd8: // ret_c();
1781  case 0xd9: // exx();
1782  case 0xda: // jp_c();
1783  case 0xdb: // in_a_byte();
1784  case 0xdc: // call_c();
1785  case 0xde: // sbc_a_byte();
1786  case 0xdf: // rst_18();
1787  case 0xe0: // ret_po();
1788  case 0xe2: // jp_po();
1789  case 0xe4: // call_po();
1790  case 0xe6: // and_byte();
1791  case 0xe7: // rst_20();
1792  case 0xe8: // ret_pe();
1793  case 0xea: // jp_pe();
1794  case 0xeb: // ex_de_hl();
1795  case 0xec: // call_pe();
1796  case 0xed: // ed();
1797  case 0xee: // xor_byte();
1798  case 0xef: // rst_28();
1799  case 0xf0: // ret_p();
1800  case 0xf1: // pop_af();
1801  case 0xf2: // jp_p();
1802  case 0xf3: // di();
1803  case 0xf4: // call_p();
1804  case 0xf5: // push_af();
1805  case 0xf6: // or_byte();
1806  case 0xf7: // rst_30();
1807  case 0xf8: // ret_m();
1808  case 0xfa: // jp_m();
1809  case 0xfb: // ei();
1810  case 0xfc: // call_m();
1811  case 0xfe: // cp_byte();
1812  case 0xff: // rst_38();
1813  if (T::isR800()) {
1814  int c = T::CC_DD + nop(); NEXT;
1815  } else {
1816  T::add(T::CC_DD);
1817  #ifdef USE_COMPUTED_GOTO
1818  goto *(opcodeTable[opcodeDD]);
1819  #else
1820  opcodeMain = opcodeDD;
1821  goto switchopcode;
1822  #endif
1823  }
1824 
1825  case 0x09: { int c = add_SS_TT<IX,BC,T::CC_DD>(); NEXT; }
1826  case 0x19: { int c = add_SS_TT<IX,DE,T::CC_DD>(); NEXT; }
1827  case 0x29: { int c = add_SS_SS<IX ,T::CC_DD>(); NEXT; }
1828  case 0x39: { int c = add_SS_TT<IX,SP,T::CC_DD>(); NEXT; }
1829  case 0x21: { int c = ld_SS_word<IX,T::CC_DD>(); NEXT; }
1830  case 0x22: { int c = ld_xword_SS<IX,T::CC_DD>(); NEXT; }
1831  case 0x2a: { int c = ld_SS_xword<IX,T::CC_DD>(); NEXT; }
1832  case 0x23: { int c = inc_SS<IX,T::CC_DD>(); NEXT; }
1833  case 0x2b: { int c = dec_SS<IX,T::CC_DD>(); NEXT; }
1834  case 0x24: { int c = inc_R<IXH,T::CC_DD>(); NEXT; }
1835  case 0x2c: { int c = inc_R<IXL,T::CC_DD>(); NEXT; }
1836  case 0x25: { int c = dec_R<IXH,T::CC_DD>(); NEXT; }
1837  case 0x2d: { int c = dec_R<IXL,T::CC_DD>(); NEXT; }
1838  case 0x26: { int c = ld_R_byte<IXH,T::CC_DD>(); NEXT; }
1839  case 0x2e: { int c = ld_R_byte<IXL,T::CC_DD>(); NEXT; }
1840  case 0x34: { int c = inc_xix<IX>(); NEXT; }
1841  case 0x35: { int c = dec_xix<IX>(); NEXT; }
1842  case 0x36: { int c = ld_xix_byte<IX>(); NEXT; }
1843 
1844  case 0x44: { int c = ld_R_R<B,IXH,T::CC_DD>(); NEXT; }
1845  case 0x45: { int c = ld_R_R<B,IXL,T::CC_DD>(); NEXT; }
1846  case 0x4c: { int c = ld_R_R<C,IXH,T::CC_DD>(); NEXT; }
1847  case 0x4d: { int c = ld_R_R<C,IXL,T::CC_DD>(); NEXT; }
1848  case 0x54: { int c = ld_R_R<D,IXH,T::CC_DD>(); NEXT; }
1849  case 0x55: { int c = ld_R_R<D,IXL,T::CC_DD>(); NEXT; }
1850  case 0x5c: { int c = ld_R_R<E,IXH,T::CC_DD>(); NEXT; }
1851  case 0x5d: { int c = ld_R_R<E,IXL,T::CC_DD>(); NEXT; }
1852  case 0x7c: { int c = ld_R_R<A,IXH,T::CC_DD>(); NEXT; }
1853  case 0x7d: { int c = ld_R_R<A,IXL,T::CC_DD>(); NEXT; }
1854  case 0x60: { int c = ld_R_R<IXH,B,T::CC_DD>(); NEXT; }
1855  case 0x61: { int c = ld_R_R<IXH,C,T::CC_DD>(); NEXT; }
1856  case 0x62: { int c = ld_R_R<IXH,D,T::CC_DD>(); NEXT; }
1857  case 0x63: { int c = ld_R_R<IXH,E,T::CC_DD>(); NEXT; }
1858  case 0x65: { int c = ld_R_R<IXH,IXL,T::CC_DD>(); NEXT; }
1859  case 0x67: { int c = ld_R_R<IXH,A,T::CC_DD>(); NEXT; }
1860  case 0x68: { int c = ld_R_R<IXL,B,T::CC_DD>(); NEXT; }
1861  case 0x69: { int c = ld_R_R<IXL,C,T::CC_DD>(); NEXT; }
1862  case 0x6a: { int c = ld_R_R<IXL,D,T::CC_DD>(); NEXT; }
1863  case 0x6b: { int c = ld_R_R<IXL,E,T::CC_DD>(); NEXT; }
1864  case 0x6c: { int c = ld_R_R<IXL,IXH,T::CC_DD>(); NEXT; }
1865  case 0x6f: { int c = ld_R_R<IXL,A,T::CC_DD>(); NEXT; }
1866  case 0x70: { int c = ld_xix_R<IX,B>(); NEXT; }
1867  case 0x71: { int c = ld_xix_R<IX,C>(); NEXT; }
1868  case 0x72: { int c = ld_xix_R<IX,D>(); NEXT; }
1869  case 0x73: { int c = ld_xix_R<IX,E>(); NEXT; }
1870  case 0x74: { int c = ld_xix_R<IX,H>(); NEXT; }
1871  case 0x75: { int c = ld_xix_R<IX,L>(); NEXT; }
1872  case 0x77: { int c = ld_xix_R<IX,A>(); NEXT; }
1873  case 0x46: { int c = ld_R_xix<B,IX>(); NEXT; }
1874  case 0x4e: { int c = ld_R_xix<C,IX>(); NEXT; }
1875  case 0x56: { int c = ld_R_xix<D,IX>(); NEXT; }
1876  case 0x5e: { int c = ld_R_xix<E,IX>(); NEXT; }
1877  case 0x66: { int c = ld_R_xix<H,IX>(); NEXT; }
1878  case 0x6e: { int c = ld_R_xix<L,IX>(); NEXT; }
1879  case 0x7e: { int c = ld_R_xix<A,IX>(); NEXT; }
1880 
1881  case 0x84: { int c = add_a_R<IXH,T::CC_DD>(); NEXT; }
1882  case 0x85: { int c = add_a_R<IXL,T::CC_DD>(); NEXT; }
1883  case 0x86: { int c = add_a_xix<IX>(); NEXT; }
1884  case 0x8c: { int c = adc_a_R<IXH,T::CC_DD>(); NEXT; }
1885  case 0x8d: { int c = adc_a_R<IXL,T::CC_DD>(); NEXT; }
1886  case 0x8e: { int c = adc_a_xix<IX>(); NEXT; }
1887  case 0x94: { int c = sub_R<IXH,T::CC_DD>(); NEXT; }
1888  case 0x95: { int c = sub_R<IXL,T::CC_DD>(); NEXT; }
1889  case 0x96: { int c = sub_xix<IX>(); NEXT; }
1890  case 0x9c: { int c = sbc_a_R<IXH,T::CC_DD>(); NEXT; }
1891  case 0x9d: { int c = sbc_a_R<IXL,T::CC_DD>(); NEXT; }
1892  case 0x9e: { int c = sbc_a_xix<IX>(); NEXT; }
1893  case 0xa4: { int c = and_R<IXH,T::CC_DD>(); NEXT; }
1894  case 0xa5: { int c = and_R<IXL,T::CC_DD>(); NEXT; }
1895  case 0xa6: { int c = and_xix<IX>(); NEXT; }
1896  case 0xac: { int c = xor_R<IXH,T::CC_DD>(); NEXT; }
1897  case 0xad: { int c = xor_R<IXL,T::CC_DD>(); NEXT; }
1898  case 0xae: { int c = xor_xix<IX>(); NEXT; }
1899  case 0xb4: { int c = or_R<IXH,T::CC_DD>(); NEXT; }
1900  case 0xb5: { int c = or_R<IXL,T::CC_DD>(); NEXT; }
1901  case 0xb6: { int c = or_xix<IX>(); NEXT; }
1902  case 0xbc: { int c = cp_R<IXH,T::CC_DD>(); NEXT; }
1903  case 0xbd: { int c = cp_R<IXL,T::CC_DD>(); NEXT; }
1904  case 0xbe: { int c = cp_xix<IX>(); NEXT; }
1905 
1906  case 0xe1: { int c = pop_SS <IX,T::CC_DD>(); NEXT; }
1907  case 0xe5: { int c = push_SS<IX,T::CC_DD>(); NEXT; }
1908  case 0xe3: { int c = ex_xsp_SS<IX,T::CC_DD>(); NEXT; }
1909  case 0xe9: { int c = jp_SS<IX,T::CC_DD>(); NEXT; }
1910  case 0xf9: { int c = ld_sp_SS<IX,T::CC_DD>(); NEXT; }
1911  case 0xcb: ixy = getIX(); goto xx_cb;
1912  case 0xdd: T::add(T::CC_DD); goto opDD_2;
1913  case 0xfd: T::add(T::CC_DD); goto opFD_2;
1914  default: UNREACHABLE; return;
1915  }
1916 }
1917 opFD_2:
1918 CASE(FD) {
1919  byte opcodeFD = RDMEM_OPCODE(T::CC_DD + T::CC_MAIN);
1920  incR(1);
1921  switch (opcodeFD) {
1922  case 0x00: // nop();
1923  case 0x01: // ld_bc_word();
1924  case 0x02: // ld_xbc_a();
1925  case 0x03: // inc_bc();
1926  case 0x04: // inc_b();
1927  case 0x05: // dec_b();
1928  case 0x06: // ld_b_byte();
1929  case 0x07: // rlca();
1930  case 0x08: // ex_af_af();
1931  case 0x0a: // ld_a_xbc();
1932  case 0x0b: // dec_bc();
1933  case 0x0c: // inc_c();
1934  case 0x0d: // dec_c();
1935  case 0x0e: // ld_c_byte();
1936  case 0x0f: // rrca();
1937  case 0x10: // djnz();
1938  case 0x11: // ld_de_word();
1939  case 0x12: // ld_xde_a();
1940  case 0x13: // inc_de();
1941  case 0x14: // inc_d();
1942  case 0x15: // dec_d();
1943  case 0x16: // ld_d_byte();
1944  case 0x17: // rla();
1945  case 0x18: // jr();
1946  case 0x1a: // ld_a_xde();
1947  case 0x1b: // dec_de();
1948  case 0x1c: // inc_e();
1949  case 0x1d: // dec_e();
1950  case 0x1e: // ld_e_byte();
1951  case 0x1f: // rra();
1952  case 0x20: // jr_nz();
1953  case 0x27: // daa();
1954  case 0x28: // jr_z();
1955  case 0x2f: // cpl();
1956  case 0x30: // jr_nc();
1957  case 0x31: // ld_sp_word();
1958  case 0x32: // ld_xbyte_a();
1959  case 0x33: // inc_sp();
1960  case 0x37: // scf();
1961  case 0x38: // jr_c();
1962  case 0x3a: // ld_a_xbyte();
1963  case 0x3b: // dec_sp();
1964  case 0x3c: // inc_a();
1965  case 0x3d: // dec_a();
1966  case 0x3e: // ld_a_byte();
1967  case 0x3f: // ccf();
1968 
1969  case 0x40: // ld_b_b();
1970  case 0x41: // ld_b_c();
1971  case 0x42: // ld_b_d();
1972  case 0x43: // ld_b_e();
1973  case 0x47: // ld_b_a();
1974  case 0x48: // ld_c_b();
1975  case 0x49: // ld_c_c();
1976  case 0x4a: // ld_c_d();
1977  case 0x4b: // ld_c_e();
1978  case 0x4f: // ld_c_a();
1979  case 0x50: // ld_d_b();
1980  case 0x51: // ld_d_c();
1981  case 0x52: // ld_d_d();
1982  case 0x53: // ld_d_e();
1983  case 0x57: // ld_d_a();
1984  case 0x58: // ld_e_b();
1985  case 0x59: // ld_e_c();
1986  case 0x5a: // ld_e_d();
1987  case 0x5b: // ld_e_e();
1988  case 0x5f: // ld_e_a();
1989  case 0x64: // ld_ixh_ixh(); == nop
1990  case 0x6d: // ld_ixl_ixl(); == nop
1991  case 0x76: // halt();
1992  case 0x78: // ld_a_b();
1993  case 0x79: // ld_a_c();
1994  case 0x7a: // ld_a_d();
1995  case 0x7b: // ld_a_e();
1996  case 0x7f: // ld_a_a();
1997 
1998  case 0x80: // add_a_b();
1999  case 0x81: // add_a_c();
2000  case 0x82: // add_a_d();
2001  case 0x83: // add_a_e();
2002  case 0x87: // add_a_a();
2003  case 0x88: // adc_a_b();
2004  case 0x89: // adc_a_c();
2005  case 0x8a: // adc_a_d();
2006  case 0x8b: // adc_a_e();
2007  case 0x8f: // adc_a_a();
2008  case 0x90: // sub_b();
2009  case 0x91: // sub_c();
2010  case 0x92: // sub_d();
2011  case 0x93: // sub_e();
2012  case 0x97: // sub_a();
2013  case 0x98: // sbc_a_b();
2014  case 0x99: // sbc_a_c();
2015  case 0x9a: // sbc_a_d();
2016  case 0x9b: // sbc_a_e();
2017  case 0x9f: // sbc_a_a();
2018  case 0xa0: // and_b();
2019  case 0xa1: // and_c();
2020  case 0xa2: // and_d();
2021  case 0xa3: // and_e();
2022  case 0xa7: // and_a();
2023  case 0xa8: // xor_b();
2024  case 0xa9: // xor_c();
2025  case 0xaa: // xor_d();
2026  case 0xab: // xor_e();
2027  case 0xaf: // xor_a();
2028  case 0xb0: // or_b();
2029  case 0xb1: // or_c();
2030  case 0xb2: // or_d();
2031  case 0xb3: // or_e();
2032  case 0xb7: // or_a();
2033  case 0xb8: // cp_b();
2034  case 0xb9: // cp_c();
2035  case 0xba: // cp_d();
2036  case 0xbb: // cp_e();
2037  case 0xbf: // cp_a();
2038 
2039  case 0xc0: // ret_nz();
2040  case 0xc1: // pop_bc();
2041  case 0xc2: // jp_nz();
2042  case 0xc3: // jp();
2043  case 0xc4: // call_nz();
2044  case 0xc5: // push_bc();
2045  case 0xc6: // add_a_byte();
2046  case 0xc7: // rst_00();
2047  case 0xc8: // ret_z();
2048  case 0xc9: // ret();
2049  case 0xca: // jp_z();
2050  case 0xcc: // call_z();
2051  case 0xcd: // call();
2052  case 0xce: // adc_a_byte();
2053  case 0xcf: // rst_08();
2054  case 0xd0: // ret_nc();
2055  case 0xd1: // pop_de();
2056  case 0xd2: // jp_nc();
2057  case 0xd3: // out_byte_a();
2058  case 0xd4: // call_nc();
2059  case 0xd5: // push_de();
2060  case 0xd6: // sub_byte();
2061  case 0xd7: // rst_10();
2062  case 0xd8: // ret_c();
2063  case 0xd9: // exx();
2064  case 0xda: // jp_c();
2065  case 0xdb: // in_a_byte();
2066  case 0xdc: // call_c();
2067  case 0xde: // sbc_a_byte();
2068  case 0xdf: // rst_18();
2069  case 0xe0: // ret_po();
2070  case 0xe2: // jp_po();
2071  case 0xe4: // call_po();
2072  case 0xe6: // and_byte();
2073  case 0xe7: // rst_20();
2074  case 0xe8: // ret_pe();
2075  case 0xea: // jp_pe();
2076  case 0xeb: // ex_de_hl();
2077  case 0xec: // call_pe();
2078  case 0xed: // ed();
2079  case 0xee: // xor_byte();
2080  case 0xef: // rst_28();
2081  case 0xf0: // ret_p();
2082  case 0xf1: // pop_af();
2083  case 0xf2: // jp_p();
2084  case 0xf3: // di();
2085  case 0xf4: // call_p();
2086  case 0xf5: // push_af();
2087  case 0xf6: // or_byte();
2088  case 0xf7: // rst_30();
2089  case 0xf8: // ret_m();
2090  case 0xfa: // jp_m();
2091  case 0xfb: // ei();
2092  case 0xfc: // call_m();
2093  case 0xfe: // cp_byte();
2094  case 0xff: // rst_38();
2095  if (T::isR800()) {
2096  int c = T::CC_DD + nop(); NEXT;
2097  } else {
2098  T::add(T::CC_DD);
2099  #ifdef USE_COMPUTED_GOTO
2100  goto *(opcodeTable[opcodeFD]);
2101  #else
2102  opcodeMain = opcodeFD;
2103  goto switchopcode;
2104  #endif
2105  }
2106 
2107  case 0x09: { int c = add_SS_TT<IY,BC,T::CC_DD>(); NEXT; }
2108  case 0x19: { int c = add_SS_TT<IY,DE,T::CC_DD>(); NEXT; }
2109  case 0x29: { int c = add_SS_SS<IY ,T::CC_DD>(); NEXT; }
2110  case 0x39: { int c = add_SS_TT<IY,SP,T::CC_DD>(); NEXT; }
2111  case 0x21: { int c = ld_SS_word<IY,T::CC_DD>(); NEXT; }
2112  case 0x22: { int c = ld_xword_SS<IY,T::CC_DD>(); NEXT; }
2113  case 0x2a: { int c = ld_SS_xword<IY,T::CC_DD>(); NEXT; }
2114  case 0x23: { int c = inc_SS<IY,T::CC_DD>(); NEXT; }
2115  case 0x2b: { int c = dec_SS<IY,T::CC_DD>(); NEXT; }
2116  case 0x24: { int c = inc_R<IYH,T::CC_DD>(); NEXT; }
2117  case 0x2c: { int c = inc_R<IYL,T::CC_DD>(); NEXT; }
2118  case 0x25: { int c = dec_R<IYH,T::CC_DD>(); NEXT; }
2119  case 0x2d: { int c = dec_R<IYL,T::CC_DD>(); NEXT; }
2120  case 0x26: { int c = ld_R_byte<IYH,T::CC_DD>(); NEXT; }
2121  case 0x2e: { int c = ld_R_byte<IYL,T::CC_DD>(); NEXT; }
2122  case 0x34: { int c = inc_xix<IY>(); NEXT; }
2123  case 0x35: { int c = dec_xix<IY>(); NEXT; }
2124  case 0x36: { int c = ld_xix_byte<IY>(); NEXT; }
2125 
2126  case 0x44: { int c = ld_R_R<B,IYH,T::CC_DD>(); NEXT; }
2127  case 0x45: { int c = ld_R_R<B,IYL,T::CC_DD>(); NEXT; }
2128  case 0x4c: { int c = ld_R_R<C,IYH,T::CC_DD>(); NEXT; }
2129  case 0x4d: { int c = ld_R_R<C,IYL,T::CC_DD>(); NEXT; }
2130  case 0x54: { int c = ld_R_R<D,IYH,T::CC_DD>(); NEXT; }
2131  case 0x55: { int c = ld_R_R<D,IYL,T::CC_DD>(); NEXT; }
2132  case 0x5c: { int c = ld_R_R<E,IYH,T::CC_DD>(); NEXT; }
2133  case 0x5d: { int c = ld_R_R<E,IYL,T::CC_DD>(); NEXT; }
2134  case 0x7c: { int c = ld_R_R<A,IYH,T::CC_DD>(); NEXT; }
2135  case 0x7d: { int c = ld_R_R<A,IYL,T::CC_DD>(); NEXT; }
2136  case 0x60: { int c = ld_R_R<IYH,B,T::CC_DD>(); NEXT; }
2137  case 0x61: { int c = ld_R_R<IYH,C,T::CC_DD>(); NEXT; }
2138  case 0x62: { int c = ld_R_R<IYH,D,T::CC_DD>(); NEXT; }
2139  case 0x63: { int c = ld_R_R<IYH,E,T::CC_DD>(); NEXT; }
2140  case 0x65: { int c = ld_R_R<IYH,IYL,T::CC_DD>(); NEXT; }
2141  case 0x67: { int c = ld_R_R<IYH,A,T::CC_DD>(); NEXT; }
2142  case 0x68: { int c = ld_R_R<IYL,B,T::CC_DD>(); NEXT; }
2143  case 0x69: { int c = ld_R_R<IYL,C,T::CC_DD>(); NEXT; }
2144  case 0x6a: { int c = ld_R_R<IYL,D,T::CC_DD>(); NEXT; }
2145  case 0x6b: { int c = ld_R_R<IYL,E,T::CC_DD>(); NEXT; }
2146  case 0x6c: { int c = ld_R_R<IYL,IYH,T::CC_DD>(); NEXT; }
2147  case 0x6f: { int c = ld_R_R<IYL,A,T::CC_DD>(); NEXT; }
2148  case 0x70: { int c = ld_xix_R<IY,B>(); NEXT; }
2149  case 0x71: { int c = ld_xix_R<IY,C>(); NEXT; }
2150  case 0x72: { int c = ld_xix_R<IY,D>(); NEXT; }
2151  case 0x73: { int c = ld_xix_R<IY,E>(); NEXT; }
2152  case 0x74: { int c = ld_xix_R<IY,H>(); NEXT; }
2153  case 0x75: { int c = ld_xix_R<IY,L>(); NEXT; }
2154  case 0x77: { int c = ld_xix_R<IY,A>(); NEXT; }
2155  case 0x46: { int c = ld_R_xix<B,IY>(); NEXT; }
2156  case 0x4e: { int c = ld_R_xix<C,IY>(); NEXT; }
2157  case 0x56: { int c = ld_R_xix<D,IY>(); NEXT; }
2158  case 0x5e: { int c = ld_R_xix<E,IY>(); NEXT; }
2159  case 0x66: { int c = ld_R_xix<H,IY>(); NEXT; }
2160  case 0x6e: { int c = ld_R_xix<L,IY>(); NEXT; }
2161  case 0x7e: { int c = ld_R_xix<A,IY>(); NEXT; }
2162 
2163  case 0x84: { int c = add_a_R<IYH,T::CC_DD>(); NEXT; }
2164  case 0x85: { int c = add_a_R<IYL,T::CC_DD>(); NEXT; }
2165  case 0x86: { int c = add_a_xix<IY>(); NEXT; }
2166  case 0x8c: { int c = adc_a_R<IYH,T::CC_DD>(); NEXT; }
2167  case 0x8d: { int c = adc_a_R<IYL,T::CC_DD>(); NEXT; }
2168  case 0x8e: { int c = adc_a_xix<IY>(); NEXT; }
2169  case 0x94: { int c = sub_R<IYH,T::CC_DD>(); NEXT; }
2170  case 0x95: { int c = sub_R<IYL,T::CC_DD>(); NEXT; }
2171  case 0x96: { int c = sub_xix<IY>(); NEXT; }
2172  case 0x9c: { int c = sbc_a_R<IYH,T::CC_DD>(); NEXT; }
2173  case 0x9d: { int c = sbc_a_R<IYL,T::CC_DD>(); NEXT; }
2174  case 0x9e: { int c = sbc_a_xix<IY>(); NEXT; }
2175  case 0xa4: { int c = and_R<IYH,T::CC_DD>(); NEXT; }
2176  case 0xa5: { int c = and_R<IYL,T::CC_DD>(); NEXT; }
2177  case 0xa6: { int c = and_xix<IY>(); NEXT; }
2178  case 0xac: { int c = xor_R<IYH,T::CC_DD>(); NEXT; }
2179  case 0xad: { int c = xor_R<IYL,T::CC_DD>(); NEXT; }
2180  case 0xae: { int c = xor_xix<IY>(); NEXT; }
2181  case 0xb4: { int c = or_R<IYH,T::CC_DD>(); NEXT; }
2182  case 0xb5: { int c = or_R<IYL,T::CC_DD>(); NEXT; }
2183  case 0xb6: { int c = or_xix<IY>(); NEXT; }
2184  case 0xbc: { int c = cp_R<IYH,T::CC_DD>(); NEXT; }
2185  case 0xbd: { int c = cp_R<IYL,T::CC_DD>(); NEXT; }
2186  case 0xbe: { int c = cp_xix<IY>(); NEXT; }
2187 
2188  case 0xe1: { int c = pop_SS <IY,T::CC_DD>(); NEXT; }
2189  case 0xe5: { int c = push_SS<IY,T::CC_DD>(); NEXT; }
2190  case 0xe3: { int c = ex_xsp_SS<IY,T::CC_DD>(); NEXT; }
2191  case 0xe9: { int c = jp_SS<IY,T::CC_DD>(); NEXT; }
2192  case 0xf9: { int c = ld_sp_SS<IY,T::CC_DD>(); NEXT; }
2193  case 0xcb: ixy = getIY(); goto xx_cb;
2194  case 0xdd: T::add(T::CC_DD); goto opDD_2;
2195  case 0xfd: T::add(T::CC_DD); goto opFD_2;
2196  default: UNREACHABLE; return;
2197  }
2198 }
2199 #ifndef USE_COMPUTED_GOTO
2200  default: UNREACHABLE; return;
2201 }
2202 #endif
2203 
2204 xx_cb: {
2205  unsigned tmp = RD_WORD_PC(T::CC_DD + T::CC_DD_CB);
2206  int8_t ofst = tmp & 0xFF;
2207  unsigned addr = (ixy + ofst) & 0xFFFF;
2208  byte xxcb_opcode = tmp >> 8;
2209  switch (xxcb_opcode) {
2210  case 0x00: { int c = rlc_xix_R<B>(addr); NEXT; }
2211  case 0x01: { int c = rlc_xix_R<C>(addr); NEXT; }
2212  case 0x02: { int c = rlc_xix_R<D>(addr); NEXT; }
2213  case 0x03: { int c = rlc_xix_R<E>(addr); NEXT; }
2214  case 0x04: { int c = rlc_xix_R<H>(addr); NEXT; }
2215  case 0x05: { int c = rlc_xix_R<L>(addr); NEXT; }
2216  case 0x06: { int c = rlc_xix_R<DUMMY>(addr); NEXT; }
2217  case 0x07: { int c = rlc_xix_R<A>(addr); NEXT; }
2218  case 0x08: { int c = rrc_xix_R<B>(addr); NEXT; }
2219  case 0x09: { int c = rrc_xix_R<C>(addr); NEXT; }
2220  case 0x0a: { int c = rrc_xix_R<D>(addr); NEXT; }
2221  case 0x0b: { int c = rrc_xix_R<E>(addr); NEXT; }
2222  case 0x0c: { int c = rrc_xix_R<H>(addr); NEXT; }
2223  case 0x0d: { int c = rrc_xix_R<L>(addr); NEXT; }
2224  case 0x0e: { int c = rrc_xix_R<DUMMY>(addr); NEXT; }
2225  case 0x0f: { int c = rrc_xix_R<A>(addr); NEXT; }
2226  case 0x10: { int c = rl_xix_R<B>(addr); NEXT; }
2227  case 0x11: { int c = rl_xix_R<C>(addr); NEXT; }
2228  case 0x12: { int c = rl_xix_R<D>(addr); NEXT; }
2229  case 0x13: { int c = rl_xix_R<E>(addr); NEXT; }
2230  case 0x14: { int c = rl_xix_R<H>(addr); NEXT; }
2231  case 0x15: { int c = rl_xix_R<L>(addr); NEXT; }
2232  case 0x16: { int c = rl_xix_R<DUMMY>(addr); NEXT; }
2233  case 0x17: { int c = rl_xix_R<A>(addr); NEXT; }
2234  case 0x18: { int c = rr_xix_R<B>(addr); NEXT; }
2235  case 0x19: { int c = rr_xix_R<C>(addr); NEXT; }
2236  case 0x1a: { int c = rr_xix_R<D>(addr); NEXT; }
2237  case 0x1b: { int c = rr_xix_R<E>(addr); NEXT; }
2238  case 0x1c: { int c = rr_xix_R<H>(addr); NEXT; }
2239  case 0x1d: { int c = rr_xix_R<L>(addr); NEXT; }
2240  case 0x1e: { int c = rr_xix_R<DUMMY>(addr); NEXT; }
2241  case 0x1f: { int c = rr_xix_R<A>(addr); NEXT; }
2242  case 0x20: { int c = sla_xix_R<B>(addr); NEXT; }
2243  case 0x21: { int c = sla_xix_R<C>(addr); NEXT; }
2244  case 0x22: { int c = sla_xix_R<D>(addr); NEXT; }
2245  case 0x23: { int c = sla_xix_R<E>(addr); NEXT; }
2246  case 0x24: { int c = sla_xix_R<H>(addr); NEXT; }
2247  case 0x25: { int c = sla_xix_R<L>(addr); NEXT; }
2248  case 0x26: { int c = sla_xix_R<DUMMY>(addr); NEXT; }
2249  case 0x27: { int c = sla_xix_R<A>(addr); NEXT; }
2250  case 0x28: { int c = sra_xix_R<B>(addr); NEXT; }
2251  case 0x29: { int c = sra_xix_R<C>(addr); NEXT; }
2252  case 0x2a: { int c = sra_xix_R<D>(addr); NEXT; }
2253  case 0x2b: { int c = sra_xix_R<E>(addr); NEXT; }
2254  case 0x2c: { int c = sra_xix_R<H>(addr); NEXT; }
2255  case 0x2d: { int c = sra_xix_R<L>(addr); NEXT; }
2256  case 0x2e: { int c = sra_xix_R<DUMMY>(addr); NEXT; }
2257  case 0x2f: { int c = sra_xix_R<A>(addr); NEXT; }
2258  case 0x30: { int c = T::isR800() ? sll2() : sll_xix_R<B>(addr); NEXT; }
2259  case 0x31: { int c = T::isR800() ? sll2() : sll_xix_R<C>(addr); NEXT; }
2260  case 0x32: { int c = T::isR800() ? sll2() : sll_xix_R<D>(addr); NEXT; }
2261  case 0x33: { int c = T::isR800() ? sll2() : sll_xix_R<E>(addr); NEXT; }
2262  case 0x34: { int c = T::isR800() ? sll2() : sll_xix_R<H>(addr); NEXT; }
2263  case 0x35: { int c = T::isR800() ? sll2() : sll_xix_R<L>(addr); NEXT; }
2264  case 0x36: { int c = T::isR800() ? sll2() : sll_xix_R<DUMMY>(addr); NEXT; }
2265  case 0x37: { int c = T::isR800() ? sll2() : sll_xix_R<A>(addr); NEXT; }
2266  case 0x38: { int c = srl_xix_R<B>(addr); NEXT; }
2267  case 0x39: { int c = srl_xix_R<C>(addr); NEXT; }
2268  case 0x3a: { int c = srl_xix_R<D>(addr); NEXT; }
2269  case 0x3b: { int c = srl_xix_R<E>(addr); NEXT; }
2270  case 0x3c: { int c = srl_xix_R<H>(addr); NEXT; }
2271  case 0x3d: { int c = srl_xix_R<L>(addr); NEXT; }
2272  case 0x3e: { int c = srl_xix_R<DUMMY>(addr); NEXT; }
2273  case 0x3f: { int c = srl_xix_R<A>(addr); NEXT; }
2274 
2275  case 0x40: case 0x41: case 0x42: case 0x43:
2276  case 0x44: case 0x45: case 0x46: case 0x47:
2277  { int c = bit_N_xix<0>(addr); NEXT; }
2278  case 0x48: case 0x49: case 0x4a: case 0x4b:
2279  case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2280  { int c = bit_N_xix<1>(addr); NEXT; }
2281  case 0x50: case 0x51: case 0x52: case 0x53:
2282  case 0x54: case 0x55: case 0x56: case 0x57:
2283  { int c = bit_N_xix<2>(addr); NEXT; }
2284  case 0x58: case 0x59: case 0x5a: case 0x5b:
2285  case 0x5c: case 0x5d: case 0x5e: case 0x5f:
2286  { int c = bit_N_xix<3>(addr); NEXT; }
2287  case 0x60: case 0x61: case 0x62: case 0x63:
2288  case 0x64: case 0x65: case 0x66: case 0x67:
2289  { int c = bit_N_xix<4>(addr); NEXT; }
2290  case 0x68: case 0x69: case 0x6a: case 0x6b:
2291  case 0x6c: case 0x6d: case 0x6e: case 0x6f:
2292  { int c = bit_N_xix<5>(addr); NEXT; }
2293  case 0x70: case 0x71: case 0x72: case 0x73:
2294  case 0x74: case 0x75: case 0x76: case 0x77:
2295  { int c = bit_N_xix<6>(addr); NEXT; }
2296  case 0x78: case 0x79: case 0x7a: case 0x7b:
2297  case 0x7c: case 0x7d: case 0x7e: case 0x7f:
2298  { int c = bit_N_xix<7>(addr); NEXT; }
2299 
2300  case 0x80: { int c = res_N_xix_R<0,B>(addr); NEXT; }
2301  case 0x81: { int c = res_N_xix_R<0,C>(addr); NEXT; }
2302  case 0x82: { int c = res_N_xix_R<0,D>(addr); NEXT; }
2303  case 0x83: { int c = res_N_xix_R<0,E>(addr); NEXT; }
2304  case 0x84: { int c = res_N_xix_R<0,H>(addr); NEXT; }
2305  case 0x85: { int c = res_N_xix_R<0,L>(addr); NEXT; }
2306  case 0x87: { int c = res_N_xix_R<0,A>(addr); NEXT; }
2307  case 0x88: { int c = res_N_xix_R<1,B>(addr); NEXT; }
2308  case 0x89: { int c = res_N_xix_R<1,C>(addr); NEXT; }
2309  case 0x8a: { int c = res_N_xix_R<1,D>(addr); NEXT; }
2310  case 0x8b: { int c = res_N_xix_R<1,E>(addr); NEXT; }
2311  case 0x8c: { int c = res_N_xix_R<1,H>(addr); NEXT; }
2312  case 0x8d: { int c = res_N_xix_R<1,L>(addr); NEXT; }
2313  case 0x8f: { int c = res_N_xix_R<1,A>(addr); NEXT; }
2314  case 0x90: { int c = res_N_xix_R<2,B>(addr); NEXT; }
2315  case 0x91: { int c = res_N_xix_R<2,C>(addr); NEXT; }
2316  case 0x92: { int c = res_N_xix_R<2,D>(addr); NEXT; }
2317  case 0x93: { int c = res_N_xix_R<2,E>(addr); NEXT; }
2318  case 0x94: { int c = res_N_xix_R<2,H>(addr); NEXT; }
2319  case 0x95: { int c = res_N_xix_R<2,L>(addr); NEXT; }
2320  case 0x97: { int c = res_N_xix_R<2,A>(addr); NEXT; }
2321  case 0x98: { int c = res_N_xix_R<3,B>(addr); NEXT; }
2322  case 0x99: { int c = res_N_xix_R<3,C>(addr); NEXT; }
2323  case 0x9a: { int c = res_N_xix_R<3,D>(addr); NEXT; }
2324  case 0x9b: { int c = res_N_xix_R<3,E>(addr); NEXT; }
2325  case 0x9c: { int c = res_N_xix_R<3,H>(addr); NEXT; }
2326  case 0x9d: { int c = res_N_xix_R<3,L>(addr); NEXT; }
2327  case 0x9f: { int c = res_N_xix_R<3,A>(addr); NEXT; }
2328  case 0xa0: { int c = res_N_xix_R<4,B>(addr); NEXT; }
2329  case 0xa1: { int c = res_N_xix_R<4,C>(addr); NEXT; }
2330  case 0xa2: { int c = res_N_xix_R<4,D>(addr); NEXT; }
2331  case 0xa3: { int c = res_N_xix_R<4,E>(addr); NEXT; }
2332  case 0xa4: { int c = res_N_xix_R<4,H>(addr); NEXT; }
2333  case 0xa5: { int c = res_N_xix_R<4,L>(addr); NEXT; }
2334  case 0xa7: { int c = res_N_xix_R<4,A>(addr); NEXT; }
2335  case 0xa8: { int c = res_N_xix_R<5,B>(addr); NEXT; }
2336  case 0xa9: { int c = res_N_xix_R<5,C>(addr); NEXT; }
2337  case 0xaa: { int c = res_N_xix_R<5,D>(addr); NEXT; }
2338  case 0xab: { int c = res_N_xix_R<5,E>(addr); NEXT; }
2339  case 0xac: { int c = res_N_xix_R<5,H>(addr); NEXT; }
2340  case 0xad: { int c = res_N_xix_R<5,L>(addr); NEXT; }
2341  case 0xaf: { int c = res_N_xix_R<5,A>(addr); NEXT; }
2342  case 0xb0: { int c = res_N_xix_R<6,B>(addr); NEXT; }
2343  case 0xb1: { int c = res_N_xix_R<6,C>(addr); NEXT; }
2344  case 0xb2: { int c = res_N_xix_R<6,D>(addr); NEXT; }
2345  case 0xb3: { int c = res_N_xix_R<6,E>(addr); NEXT; }
2346  case 0xb4: { int c = res_N_xix_R<6,H>(addr); NEXT; }
2347  case 0xb5: { int c = res_N_xix_R<6,L>(addr); NEXT; }
2348  case 0xb7: { int c = res_N_xix_R<6,A>(addr); NEXT; }
2349  case 0xb8: { int c = res_N_xix_R<7,B>(addr); NEXT; }
2350  case 0xb9: { int c = res_N_xix_R<7,C>(addr); NEXT; }
2351  case 0xba: { int c = res_N_xix_R<7,D>(addr); NEXT; }
2352  case 0xbb: { int c = res_N_xix_R<7,E>(addr); NEXT; }
2353  case 0xbc: { int c = res_N_xix_R<7,H>(addr); NEXT; }
2354  case 0xbd: { int c = res_N_xix_R<7,L>(addr); NEXT; }
2355  case 0xbf: { int c = res_N_xix_R<7,A>(addr); NEXT; }
2356  case 0x86: { int c = res_N_xix_R<0,DUMMY>(addr); NEXT; }
2357  case 0x8e: { int c = res_N_xix_R<1,DUMMY>(addr); NEXT; }
2358  case 0x96: { int c = res_N_xix_R<2,DUMMY>(addr); NEXT; }
2359  case 0x9e: { int c = res_N_xix_R<3,DUMMY>(addr); NEXT; }
2360  case 0xa6: { int c = res_N_xix_R<4,DUMMY>(addr); NEXT; }
2361  case 0xae: { int c = res_N_xix_R<5,DUMMY>(addr); NEXT; }
2362  case 0xb6: { int c = res_N_xix_R<6,DUMMY>(addr); NEXT; }
2363  case 0xbe: { int c = res_N_xix_R<7,DUMMY>(addr); NEXT; }
2364 
2365  case 0xc0: { int c = set_N_xix_R<0,B>(addr); NEXT; }
2366  case 0xc1: { int c = set_N_xix_R<0,C>(addr); NEXT; }
2367  case 0xc2: { int c = set_N_xix_R<0,D>(addr); NEXT; }
2368  case 0xc3: { int c = set_N_xix_R<0,E>(addr); NEXT; }
2369  case 0xc4: { int c = set_N_xix_R<0,H>(addr); NEXT; }
2370  case 0xc5: { int c = set_N_xix_R<0,L>(addr); NEXT; }
2371  case 0xc7: { int c = set_N_xix_R<0,A>(addr); NEXT; }
2372  case 0xc8: { int c = set_N_xix_R<1,B>(addr); NEXT; }
2373  case 0xc9: { int c = set_N_xix_R<1,C>(addr); NEXT; }
2374  case 0xca: { int c = set_N_xix_R<1,D>(addr); NEXT; }
2375  case 0xcb: { int c = set_N_xix_R<1,E>(addr); NEXT; }
2376  case 0xcc: { int c = set_N_xix_R<1,H>(addr); NEXT; }
2377  case 0xcd: { int c = set_N_xix_R<1,L>(addr); NEXT; }
2378  case 0xcf: { int c = set_N_xix_R<1,A>(addr); NEXT; }
2379  case 0xd0: { int c = set_N_xix_R<2,B>(addr); NEXT; }
2380  case 0xd1: { int c = set_N_xix_R<2,C>(addr); NEXT; }
2381  case 0xd2: { int c = set_N_xix_R<2,D>(addr); NEXT; }
2382  case 0xd3: { int c = set_N_xix_R<2,E>(addr); NEXT; }
2383  case 0xd4: { int c = set_N_xix_R<2,H>(addr); NEXT; }
2384  case 0xd5: { int c = set_N_xix_R<2,L>(addr); NEXT; }
2385  case 0xd7: { int c = set_N_xix_R<2,A>(addr); NEXT; }
2386  case 0xd8: { int c = set_N_xix_R<3,B>(addr); NEXT; }
2387  case 0xd9: { int c = set_N_xix_R<3,C>(addr); NEXT; }
2388  case 0xda: { int c = set_N_xix_R<3,D>(addr); NEXT; }
2389  case 0xdb: { int c = set_N_xix_R<3,E>(addr); NEXT; }
2390  case 0xdc: { int c = set_N_xix_R<3,H>(addr); NEXT; }
2391  case 0xdd: { int c = set_N_xix_R<3,L>(addr); NEXT; }
2392  case 0xdf: { int c = set_N_xix_R<3,A>(addr); NEXT; }
2393  case 0xe0: { int c = set_N_xix_R<4,B>(addr); NEXT; }
2394  case 0xe1: { int c = set_N_xix_R<4,C>(addr); NEXT; }
2395  case 0xe2: { int c = set_N_xix_R<4,D>(addr); NEXT; }
2396  case 0xe3: { int c = set_N_xix_R<4,E>(addr); NEXT; }
2397  case 0xe4: { int c = set_N_xix_R<4,H>(addr); NEXT; }
2398  case 0xe5: { int c = set_N_xix_R<4,L>(addr); NEXT; }
2399  case 0xe7: { int c = set_N_xix_R<4,A>(addr); NEXT; }
2400  case 0xe8: { int c = set_N_xix_R<5,B>(addr); NEXT; }
2401  case 0xe9: { int c = set_N_xix_R<5,C>(addr); NEXT; }
2402  case 0xea: { int c = set_N_xix_R<5,D>(addr); NEXT; }
2403  case 0xeb: { int c = set_N_xix_R<5,E>(addr); NEXT; }
2404  case 0xec: { int c = set_N_xix_R<5,H>(addr); NEXT; }
2405  case 0xed: { int c = set_N_xix_R<5,L>(addr); NEXT; }
2406  case 0xef: { int c = set_N_xix_R<5,A>(addr); NEXT; }
2407  case 0xf0: { int c = set_N_xix_R<6,B>(addr); NEXT; }
2408  case 0xf1: { int c = set_N_xix_R<6,C>(addr); NEXT; }
2409  case 0xf2: { int c = set_N_xix_R<6,D>(addr); NEXT; }
2410  case 0xf3: { int c = set_N_xix_R<6,E>(addr); NEXT; }
2411  case 0xf4: { int c = set_N_xix_R<6,H>(addr); NEXT; }
2412  case 0xf5: { int c = set_N_xix_R<6,L>(addr); NEXT; }
2413  case 0xf7: { int c = set_N_xix_R<6,A>(addr); NEXT; }
2414  case 0xf8: { int c = set_N_xix_R<7,B>(addr); NEXT; }
2415  case 0xf9: { int c = set_N_xix_R<7,C>(addr); NEXT; }
2416  case 0xfa: { int c = set_N_xix_R<7,D>(addr); NEXT; }
2417  case 0xfb: { int c = set_N_xix_R<7,E>(addr); NEXT; }
2418  case 0xfc: { int c = set_N_xix_R<7,H>(addr); NEXT; }
2419  case 0xfd: { int c = set_N_xix_R<7,L>(addr); NEXT; }
2420  case 0xff: { int c = set_N_xix_R<7,A>(addr); NEXT; }
2421  case 0xc6: { int c = set_N_xix_R<0,DUMMY>(addr); NEXT; }
2422  case 0xce: { int c = set_N_xix_R<1,DUMMY>(addr); NEXT; }
2423  case 0xd6: { int c = set_N_xix_R<2,DUMMY>(addr); NEXT; }
2424  case 0xde: { int c = set_N_xix_R<3,DUMMY>(addr); NEXT; }
2425  case 0xe6: { int c = set_N_xix_R<4,DUMMY>(addr); NEXT; }
2426  case 0xee: { int c = set_N_xix_R<5,DUMMY>(addr); NEXT; }
2427  case 0xf6: { int c = set_N_xix_R<6,DUMMY>(addr); NEXT; }
2428  case 0xfe: { int c = set_N_xix_R<7,DUMMY>(addr); NEXT; }
2429  default: UNREACHABLE;
2430  }
2431  }
2432 }
2433 
2434 template<class T> inline void CPUCore<T>::cpuTracePre()
2435 {
2436  start_pc = getPC();
2437 }
2438 template<class T> inline void CPUCore<T>::cpuTracePost()
2439 {
2440  if (unlikely(tracingEnabled)) {
2441  cpuTracePost_slow();
2442  }
2443 }
2444 template<class T> void CPUCore<T>::cpuTracePost_slow()
2445 {
2446  byte opbuf[4];
2447  string dasmOutput;
2448  dasm(*interface, start_pc, opbuf, dasmOutput, T::getTimeFast());
2449  std::cout << std::setfill('0') << std::hex << std::setw(4) << start_pc
2450  << " : " << dasmOutput
2451  << " AF=" << std::setw(4) << getAF()
2452  << " BC=" << std::setw(4) << getBC()
2453  << " DE=" << std::setw(4) << getDE()
2454  << " HL=" << std::setw(4) << getHL()
2455  << " IX=" << std::setw(4) << getIX()
2456  << " IY=" << std::setw(4) << getIY()
2457  << " SP=" << std::setw(4) << getSP()
2458  << std::endl << std::dec;
2459 }
2460 
2461 template<class T> void CPUCore<T>::executeSlow()
2462 {
2463  if (unlikely(false && nmiEdge)) {
2464  // Note: NMIs are disabled, see also raiseNMI()
2465  nmiEdge = false;
2466  nmi(); // NMI occured
2467  } else if (unlikely(IRQStatus && getIFF1() && !prevWasEI())) {
2468  // normal interrupt
2469  if (unlikely(prevWasLDAI())) {
2470  // HACK!!!
2471  // The 'ld a,i' or 'ld a,r' instruction copies the IFF2
2472  // bit to the V flag. Though when the Z80 accepts an
2473  // IRQ directly after this instruction, the V flag is 0
2474  // (instead of the expected value 1). This can probably
2475  // be explained if you look at the pipeline of the Z80.
2476  // But for speed reasons we implement it here as a
2477  // fix-up (a hack) in the IRQ routine. This behaviour
2478  // is actually a bug in the Z80.
2479  // Thanks to n_n for reporting this behaviour. I think
2480  // this was discovered by GuyveR800. Also thanks to
2481  // n_n for writing a test program that demonstrates
2482  // this quirk.
2483  // I also wrote a test program that demonstrates this
2484  // behaviour is the same whether 'ld a,i' is preceded
2485  // by a 'ei' instruction or not (so it's not caused by
2486  // the 'delayed IRQ acceptance of ei').
2487  assert(getF() & V_FLAG);
2488  setF(getF() & ~V_FLAG);
2489  }
2490  IRQAccept.signal();
2491  switch (getIM()) {
2492  case 0: irq0();
2493  break;
2494  case 1: irq1();
2495  break;
2496  case 2: irq2();
2497  break;
2498  default:
2499  UNREACHABLE;
2500  }
2501  } else if (unlikely(getHALT())) {
2502  // in halt mode
2503  incR(T::advanceHalt(T::haltStates(), scheduler.getNext()));
2504  setSlowInstructions();
2505  } else {
2506  cpuTracePre();
2507  assert(T::limitReached()); // we want only one instruction
2508  executeInstructions();
2509  endInstruction();
2510 
2511  if (T::isR800()) {
2512  if (unlikely(prev2WasCall()) && likely(!prevWasPopRet())) {
2513  // On R800 a CALL or RST instruction not _immediately_
2514  // followed by a (single-byte) POP or RET instruction
2515  // causes an extra cycle in that following instruction.
2516  // No idea why yet. See doc/internal/r800-call.txt
2517  // for more information.
2518  //
2519  // TODO this implementation adds the extra cycle at
2520  // the end of the instruction POP/RET. It is not known
2521  // where in the instruction the real R800 adds this cycle.
2522  T::add(1);
2523  }
2524  }
2525  cpuTracePost();
2526  }
2527 }
2528 
2529 template<class T> void CPUCore<T>::execute(bool fastForward)
2530 {
2531  // In fast-forward mode, breakpoints, watchpoints or debug condtions
2532  // won't trigger. It is possible we already are in break mode, but
2533  // break is ignored in fast-forward mode.
2534  assert(fastForward || !interface->isBreaked());
2535  if (fastForward) {
2536  interface->setFastForward(true);
2537  }
2538  execute2(fastForward);
2539  interface->setFastForward(false);
2540 }
2541 
2542 template<class T> void CPUCore<T>::execute2(bool fastForward)
2543 {
2544  // note: Don't use getTimeFast() here, because 'once in a while' we
2545  // need to CPUClock::sync() to avoid overflow.
2546  // Should be done at least once per second (approx). So only
2547  // once in this method is enough.
2548  scheduler.schedule(T::getTime());
2549  setSlowInstructions();
2550 
2551  if (!fastForward && (interface->isContinue() || interface->isStep())) {
2552  // at least one instruction
2553  interface->setContinue(false);
2554  executeSlow();
2555  scheduler.schedule(T::getTimeFast());
2556  --slowInstructions;
2557  if (interface->isStep()) {
2558  interface->setStep(false);
2559  interface->doBreak();
2560  return;
2561  }
2562  }
2563 
2564  // Note: we call scheduler _after_ executing the instruction and before
2565  // deciding between executeFast() and executeSlow() (because a
2566  // SyncPoint could set an IRQ and then we must choose executeSlow())
2567  if (fastForward ||
2568  (!interface->anyBreakPoints() && !tracingEnabled)) {
2569  // fast path, no breakpoints, no tracing
2570  while (!needExitCPULoop()) {
2571  if (slowInstructions) {
2572  --slowInstructions;
2573  executeSlow();
2574  scheduler.schedule(T::getTimeFast());
2575  } else {
2576  while (slowInstructions == 0) {
2577  T::enableLimit(); // does CPUClock::sync()
2578  if (likely(!T::limitReached())) {
2579  // multiple instructions
2580  executeInstructions();
2581  // note: pipeline only shifted one
2582  // step for multiple instructions
2583  endInstruction();
2584  }
2585  scheduler.schedule(T::getTimeFast());
2586  if (needExitCPULoop()) return;
2587  }
2588  }
2589  }
2590  } else {
2591  while (!needExitCPULoop()) {
2592  if (interface->checkBreakPoints(getPC(), motherboard)) {
2593  assert(interface->isBreaked());
2594  break;
2595  }
2596  if (slowInstructions == 0) {
2597  cpuTracePre();
2598  assert(T::limitReached()); // only one instruction
2599  executeInstructions();
2600  endInstruction();
2601  cpuTracePost();
2602  } else {
2603  --slowInstructions;
2604  executeSlow();
2605  }
2606  // Don't use getTimeFast() here, we need a call to
2607  // CPUClock::sync() 'once in a while'. (During a
2608  // reverse fast-forward this wasn't always the case).
2609  scheduler.schedule(T::getTime());
2610  }
2611  }
2612 }
2613 
2614 template<class T> template<Reg8 R8> ALWAYS_INLINE byte CPUCore<T>::get8() const {
2615  if (R8 == A) { return getA(); }
2616  else if (R8 == F) { return getF(); }
2617  else if (R8 == B) { return getB(); }
2618  else if (R8 == C) { return getC(); }
2619  else if (R8 == D) { return getD(); }
2620  else if (R8 == E) { return getE(); }
2621  else if (R8 == H) { return getH(); }
2622  else if (R8 == L) { return getL(); }
2623  else if (R8 == IXH) { return getIXh(); }
2624  else if (R8 == IXL) { return getIXl(); }
2625  else if (R8 == IYH) { return getIYh(); }
2626  else if (R8 == IYL) { return getIYl(); }
2627  else if (R8 == REG_I) { return getI(); }
2628  else if (R8 == REG_R) { return getR(); }
2629  else if (R8 == DUMMY) { return 0; }
2630  else { UNREACHABLE; return 0; }
2631 }
2632 template<class T> template<Reg16 R16> ALWAYS_INLINE unsigned CPUCore<T>::get16() const {
2633  if (R16 == AF) { return getAF(); }
2634  else if (R16 == BC) { return getBC(); }
2635  else if (R16 == DE) { return getDE(); }
2636  else if (R16 == HL) { return getHL(); }
2637  else if (R16 == IX) { return getIX(); }
2638  else if (R16 == IY) { return getIY(); }
2639  else if (R16 == SP) { return getSP(); }
2640  else { UNREACHABLE; return 0; }
2641 }
2642 template<class T> template<Reg8 R8> ALWAYS_INLINE void CPUCore<T>::set8(byte x) {
2643  if (R8 == A) { setA(x); }
2644  else if (R8 == F) { setF(x); }
2645  else if (R8 == B) { setB(x); }
2646  else if (R8 == C) { setC(x); }
2647  else if (R8 == D) { setD(x); }
2648  else if (R8 == E) { setE(x); }
2649  else if (R8 == H) { setH(x); }
2650  else if (R8 == L) { setL(x); }
2651  else if (R8 == IXH) { setIXh(x); }
2652  else if (R8 == IXL) { setIXl(x); }
2653  else if (R8 == IYH) { setIYh(x); }
2654  else if (R8 == IYL) { setIYl(x); }
2655  else if (R8 == REG_I) { setI(x); }
2656  else if (R8 == REG_R) { setR(x); }
2657  else if (R8 == DUMMY) { /* nothing */ }
2658  else { UNREACHABLE; }
2659 }
2660 template<class T> template<Reg16 R16> ALWAYS_INLINE void CPUCore<T>::set16(unsigned x) {
2661  if (R16 == AF) { setAF(x); }
2662  else if (R16 == BC) { setBC(x); }
2663  else if (R16 == DE) { setDE(x); }
2664  else if (R16 == HL) { setHL(x); }
2665  else if (R16 == IX) { setIX(x); }
2666  else if (R16 == IY) { setIY(x); }
2667  else if (R16 == SP) { setSP(x); }
2668  else { UNREACHABLE; }
2669 }
2670 
2671 // LD r,r
2672 template<class T> template<Reg8 DST, Reg8 SRC, int EE> int CPUCore<T>::ld_R_R() {
2673  set8<DST>(get8<SRC>()); return T::CC_LD_R_R + EE;
2674 }
2675 
2676 // LD SP,ss
2677 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_sp_SS() {
2678  setSP(get16<REG>()); return T::CC_LD_SP_HL + EE;
2679 }
2680 
2681 // LD (ss),a
2682 template<class T> template<Reg16 REG> int CPUCore<T>::ld_SS_a() {
2683  T::setMemPtr((getA() << 8) | ((get16<REG>() + 1) & 0xFF));
2684  WRMEM(get16<REG>(), getA(), T::CC_LD_SS_A_1);
2685  return T::CC_LD_SS_A;
2686 }
2687 
2688 // LD (HL),r
2689 template<class T> template<Reg8 SRC> int CPUCore<T>::ld_xhl_R() {
2690  WRMEM(getHL(), get8<SRC>(), T::CC_LD_HL_R_1);
2691  return T::CC_LD_HL_R;
2692 }
2693 
2694 // LD (IXY+e),r
2695 template<class T> template<Reg16 IXY, Reg8 SRC> int CPUCore<T>::ld_xix_R() {
2696  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_LD_XIX_R_1);
2697  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2698  T::setMemPtr(addr);
2699  WRMEM(addr, get8<SRC>(), T::CC_DD + T::CC_LD_XIX_R_2);
2700  return T::CC_DD + T::CC_LD_XIX_R;
2701 }
2702 
2703 // LD (HL),n
2704 template<class T> int CPUCore<T>::ld_xhl_byte() {
2705  byte val = RDMEM_OPCODE(T::CC_LD_HL_N_1);
2706  WRMEM(getHL(), val, T::CC_LD_HL_N_2);
2707  return T::CC_LD_HL_N;
2708 }
2709 
2710 // LD (IXY+e),n
2711 template<class T> template<Reg16 IXY> int CPUCore<T>::ld_xix_byte() {
2712  unsigned tmp = RD_WORD_PC(T::CC_DD + T::CC_LD_XIX_N_1);
2713  int8_t ofst = tmp & 0xFF;
2714  byte val = tmp >> 8;
2715  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2716  T::setMemPtr(addr);
2717  WRMEM(addr, val, T::CC_DD + T::CC_LD_XIX_N_2);
2718  return T::CC_DD + T::CC_LD_XIX_N;
2719 }
2720 
2721 // LD (nn),A
2722 template<class T> int CPUCore<T>::ld_xbyte_a() {
2723  unsigned x = RD_WORD_PC(T::CC_LD_NN_A_1);
2724  T::setMemPtr((getA() << 8) | ((x + 1) & 0xFF));
2725  WRMEM(x, getA(), T::CC_LD_NN_A_2);
2726  return T::CC_LD_NN_A;
2727 }
2728 
2729 // LD (nn),ss
2730 template<class T> template<int EE> inline int CPUCore<T>::WR_NN_Y(unsigned reg) {
2731  unsigned addr = RD_WORD_PC(T::CC_LD_XX_HL_1 + EE);
2732  T::setMemPtr(addr + 1);
2733  WR_WORD(addr, reg, T::CC_LD_XX_HL_2 + EE);
2734  return T::CC_LD_XX_HL + EE;
2735 }
2736 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_xword_SS() {
2737  return WR_NN_Y<EE >(get16<REG>());
2738 }
2739 template<class T> template<Reg16 REG> int CPUCore<T>::ld_xword_SS_ED() {
2740  return WR_NN_Y<T::EE_ED>(get16<REG>());
2741 }
2742 
2743 // LD A,(ss)
2744 template<class T> template<Reg16 REG> int CPUCore<T>::ld_a_SS() {
2745  T::setMemPtr(get16<REG>() + 1);
2746  setA(RDMEM(get16<REG>(), T::CC_LD_A_SS_1));
2747  return T::CC_LD_A_SS;
2748 }
2749 
2750 // LD A,(nn)
2751 template<class T> int CPUCore<T>::ld_a_xbyte() {
2752  unsigned addr = RD_WORD_PC(T::CC_LD_A_NN_1);
2753  T::setMemPtr(addr + 1);
2754  setA(RDMEM(addr, T::CC_LD_A_NN_2));
2755  return T::CC_LD_A_NN;
2756 }
2757 
2758 // LD r,n
2759 template<class T> template<Reg8 DST, int EE> int CPUCore<T>::ld_R_byte() {
2760  set8<DST>(RDMEM_OPCODE(T::CC_LD_R_N_1 + EE)); return T::CC_LD_R_N + EE;
2761 }
2762 
2763 // LD r,(hl)
2764 template<class T> template<Reg8 DST> int CPUCore<T>::ld_R_xhl() {
2765  set8<DST>(RDMEM(getHL(), T::CC_LD_R_HL_1)); return T::CC_LD_R_HL;
2766 }
2767 
2768 // LD r,(IXY+e)
2769 template<class T> template<Reg8 DST, Reg16 IXY> int CPUCore<T>::ld_R_xix() {
2770  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_LD_R_XIX_1);
2771  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2772  T::setMemPtr(addr);
2773  set8<DST>(RDMEM(addr, T::CC_DD + T::CC_LD_R_XIX_2));
2774  return T::CC_DD + T::CC_LD_R_XIX;
2775 }
2776 
2777 // LD ss,(nn)
2778 template<class T> template<int EE> inline unsigned CPUCore<T>::RD_P_XX() {
2779  unsigned addr = RD_WORD_PC(T::CC_LD_HL_XX_1 + EE);
2780  T::setMemPtr(addr + 1);
2781  unsigned result = RD_WORD(addr, T::CC_LD_HL_XX_2 + EE);
2782  return result;
2783 }
2784 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_SS_xword() {
2785  set16<REG>(RD_P_XX<EE>()); return T::CC_LD_HL_XX + EE;
2786 }
2787 template<class T> template<Reg16 REG> int CPUCore<T>::ld_SS_xword_ED() {
2788  set16<REG>(RD_P_XX<T::EE_ED>()); return T::CC_LD_HL_XX + T::EE_ED;
2789 }
2790 
2791 // LD ss,nn
2792 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_SS_word() {
2793  set16<REG>(RD_WORD_PC(T::CC_LD_SS_NN_1 + EE)); return T::CC_LD_SS_NN + EE;
2794 }
2795 
2796 
2797 // ADC A,r
2798 template<class T> inline void CPUCore<T>::ADC(byte reg) {
2799  unsigned res = getA() + reg + ((getF() & C_FLAG) ? 1 : 0);
2800  byte f = ((res & 0x100) ? C_FLAG : 0) |
2801  ((getA() ^ res ^ reg) & H_FLAG) |
2802  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2803  0; // N_FLAG
2804  if (T::isR800()) {
2805  f |= ZSTable[res & 0xFF];
2806  f |= getF() & (X_FLAG | Y_FLAG);
2807  } else {
2808  f |= ZSXYTable[res & 0xFF];
2809  }
2810  setF(f);
2811  setA(res);
2812 }
2813 template<class T> inline int CPUCore<T>::adc_a_a() {
2814  unsigned res = 2 * getA() + ((getF() & C_FLAG) ? 1 : 0);
2815  byte f = ((res & 0x100) ? C_FLAG : 0) |
2816  (res & H_FLAG) |
2817  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2818  0; // N_FLAG
2819  if (T::isR800()) {
2820  f |= ZSTable[res & 0xFF];
2821  f |= getF() & (X_FLAG | Y_FLAG);
2822  } else {
2823  f |= ZSXYTable[res & 0xFF];
2824  }
2825  setF(f);
2826  setA(res);
2827  return T::CC_CP_R;
2828 }
2829 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::adc_a_R() {
2830  ADC(get8<SRC>()); return T::CC_CP_R + EE;
2831 }
2832 template<class T> int CPUCore<T>::adc_a_byte() {
2833  ADC(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2834 }
2835 template<class T> int CPUCore<T>::adc_a_xhl() {
2836  ADC(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2837 }
2838 template<class T> template<Reg16 IXY> int CPUCore<T>::adc_a_xix() {
2839  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2840  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2841  T::setMemPtr(addr);
2842  ADC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2843  return T::CC_DD + T::CC_CP_XIX;
2844 }
2845 
2846 // ADD A,r
2847 template<class T> inline void CPUCore<T>::ADD(byte reg) {
2848  unsigned res = getA() + reg;
2849  byte f = ((res & 0x100) ? C_FLAG : 0) |
2850  ((getA() ^ res ^ reg) & H_FLAG) |
2851  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2852  0; // N_FLAG
2853  if (T::isR800()) {
2854  f |= ZSTable[res & 0xFF];
2855  f |= getF() & (X_FLAG | Y_FLAG);
2856  } else {
2857  f |= ZSXYTable[res & 0xFF];
2858  }
2859  setF(f);
2860  setA(res);
2861 }
2862 template<class T> inline int CPUCore<T>::add_a_a() {
2863  unsigned res = 2 * getA();
2864  byte f = ((res & 0x100) ? C_FLAG : 0) |
2865  (res & H_FLAG) |
2866  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2867  0; // N_FLAG
2868  if (T::isR800()) {
2869  f |= ZSTable[res & 0xFF];
2870  f |= getF() & (X_FLAG | Y_FLAG);
2871  } else {
2872  f |= ZSXYTable[res & 0xFF];
2873  }
2874  setF(f);
2875  setA(res);
2876  return T::CC_CP_R;
2877 }
2878 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::add_a_R() {
2879  ADD(get8<SRC>()); return T::CC_CP_R + EE;
2880 }
2881 template<class T> int CPUCore<T>::add_a_byte() {
2882  ADD(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2883 }
2884 template<class T> int CPUCore<T>::add_a_xhl() {
2885  ADD(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2886 }
2887 template<class T> template<Reg16 IXY> int CPUCore<T>::add_a_xix() {
2888  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2889  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2890  T::setMemPtr(addr);
2891  ADD(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2892  return T::CC_DD + T::CC_CP_XIX;
2893 }
2894 
2895 // AND r
2896 template<class T> inline void CPUCore<T>::AND(byte reg) {
2897  setA(getA() & reg);
2898  byte f = 0;
2899  if (T::isR800()) {
2900  f |= ZSPHTable[getA()];
2901  f |= getF() & (X_FLAG | Y_FLAG);
2902  } else {
2903  f |= ZSPXYTable[getA()] | H_FLAG;
2904  }
2905  setF(f);
2906 }
2907 template<class T> int CPUCore<T>::and_a() {
2908  byte f = 0;
2909  if (T::isR800()) {
2910  f |= ZSPHTable[getA()];
2911  f |= getF() & (X_FLAG | Y_FLAG);
2912  } else {
2913  f |= ZSPXYTable[getA()] | H_FLAG;
2914  }
2915  setF(f);
2916  return T::CC_CP_R;
2917 }
2918 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::and_R() {
2919  AND(get8<SRC>()); return T::CC_CP_R + EE;
2920 }
2921 template<class T> int CPUCore<T>::and_byte() {
2922  AND(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2923 }
2924 template<class T> int CPUCore<T>::and_xhl() {
2925  AND(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2926 }
2927 template<class T> template<Reg16 IXY> int CPUCore<T>::and_xix() {
2928  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2929  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2930  T::setMemPtr(addr);
2931  AND(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2932  return T::CC_DD + T::CC_CP_XIX;
2933 }
2934 
2935 // CP r
2936 template<class T> inline void CPUCore<T>::CP(byte reg) {
2937  unsigned q = getA() - reg;
2938  byte f = ZSTable[q & 0xFF] |
2939  ((q & 0x100) ? C_FLAG : 0) |
2940  N_FLAG |
2941  ((getA() ^ q ^ reg) & H_FLAG) |
2942  (((reg ^ getA()) & (getA() ^ q) & 0x80) >> 5); // V_FLAG
2943  if (T::isR800()) {
2944  f |= getF() & (X_FLAG | Y_FLAG);
2945  } else {
2946  f |= reg & (X_FLAG | Y_FLAG); // XY from operand, not from result
2947  }
2948  setF(f);
2949 }
2950 template<class T> int CPUCore<T>::cp_a() {
2951  byte f = ZS0 | N_FLAG;
2952  if (T::isR800()) {
2953  f |= getF() & (X_FLAG | Y_FLAG);
2954  } else {
2955  f |= getA() & (X_FLAG | Y_FLAG); // XY from operand, not from result
2956  }
2957  setF(f);
2958  return T::CC_CP_R;
2959 }
2960 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::cp_R() {
2961  CP(get8<SRC>()); return T::CC_CP_R + EE;
2962 }
2963 template<class T> int CPUCore<T>::cp_byte() {
2964  CP(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2965 }
2966 template<class T> int CPUCore<T>::cp_xhl() {
2967  CP(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2968 }
2969 template<class T> template<Reg16 IXY> int CPUCore<T>::cp_xix() {
2970  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2971  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2972  T::setMemPtr(addr);
2973  CP(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2974  return T::CC_DD + T::CC_CP_XIX;
2975 }
2976 
2977 // OR r
2978 template<class T> inline void CPUCore<T>::OR(byte reg) {
2979  setA(getA() | reg);
2980  byte f = 0;
2981  if (T::isR800()) {
2982  f |= ZSPTable[getA()];
2983  f |= getF() & (X_FLAG | Y_FLAG);
2984  } else {
2985  f |= ZSPXYTable[getA()];
2986  }
2987  setF(f);
2988 }
2989 template<class T> int CPUCore<T>::or_a() {
2990  byte f = 0;
2991  if (T::isR800()) {
2992  f |= ZSPTable[getA()];
2993  f |= getF() & (X_FLAG | Y_FLAG);
2994  } else {
2995  f |= ZSPXYTable[getA()];
2996  }
2997  setF(f);
2998  return T::CC_CP_R;
2999 }
3000 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::or_R() {
3001  OR(get8<SRC>()); return T::CC_CP_R + EE;
3002 }
3003 template<class T> int CPUCore<T>::or_byte() {
3004  OR(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3005 }
3006 template<class T> int CPUCore<T>::or_xhl() {
3007  OR(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3008 }
3009 template<class T> template<Reg16 IXY> int CPUCore<T>::or_xix() {
3010  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3011  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3012  T::setMemPtr(addr);
3013  OR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3014  return T::CC_DD + T::CC_CP_XIX;
3015 }
3016 
3017 // SBC A,r
3018 template<class T> inline void CPUCore<T>::SBC(byte reg) {
3019  unsigned res = getA() - reg - ((getF() & C_FLAG) ? 1 : 0);
3020  byte f = ((res & 0x100) ? C_FLAG : 0) |
3021  N_FLAG |
3022  ((getA() ^ res ^ reg) & H_FLAG) |
3023  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3024  if (T::isR800()) {
3025  f |= ZSTable[res & 0xFF];
3026  f |= getF() & (X_FLAG | Y_FLAG);
3027  } else {
3028  f |= ZSXYTable[res & 0xFF];
3029  }
3030  setF(f);
3031  setA(res);
3032 }
3033 template<class T> int CPUCore<T>::sbc_a_a() {
3034  if (T::isR800()) {
3035  word t = (getF() & C_FLAG)
3036  ? (255 * 256 | ZS255 | C_FLAG | H_FLAG | N_FLAG)
3037  : ( 0 * 256 | ZS0 | N_FLAG);
3038  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3039  } else {
3040  setAF((getF() & C_FLAG) ?
3041  (255 * 256 | ZSXY255 | C_FLAG | H_FLAG | N_FLAG) :
3042  ( 0 * 256 | ZSXY0 | N_FLAG));
3043  }
3044  return T::CC_CP_R;
3045 }
3046 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::sbc_a_R() {
3047  SBC(get8<SRC>()); return T::CC_CP_R + EE;
3048 }
3049 template<class T> int CPUCore<T>::sbc_a_byte() {
3050  SBC(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3051 }
3052 template<class T> int CPUCore<T>::sbc_a_xhl() {
3053  SBC(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3054 }
3055 template<class T> template<Reg16 IXY> int CPUCore<T>::sbc_a_xix() {
3056  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3057  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3058  T::setMemPtr(addr);
3059  SBC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3060  return T::CC_DD + T::CC_CP_XIX;
3061 }
3062 
3063 // SUB r
3064 template<class T> inline void CPUCore<T>::SUB(byte reg) {
3065  unsigned res = getA() - reg;
3066  byte f = ((res & 0x100) ? C_FLAG : 0) |
3067  N_FLAG |
3068  ((getA() ^ res ^ reg) & H_FLAG) |
3069  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3070  if (T::isR800()) {
3071  f |= ZSTable[res & 0xFF];
3072  f |= getF() & (X_FLAG | Y_FLAG);
3073  } else {
3074  f |= ZSXYTable[res & 0xFF];
3075  }
3076  setF(f);
3077  setA(res);
3078 }
3079 template<class T> int CPUCore<T>::sub_a() {
3080  if (T::isR800()) {
3081  word t = 0 * 256 | ZS0 | N_FLAG;
3082  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3083  } else {
3084  setAF(0 * 256 | ZSXY0 | N_FLAG);
3085  }
3086  return T::CC_CP_R;
3087 }
3088 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::sub_R() {
3089  SUB(get8<SRC>()); return T::CC_CP_R + EE;
3090 }
3091 template<class T> int CPUCore<T>::sub_byte() {
3092  SUB(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3093 }
3094 template<class T> int CPUCore<T>::sub_xhl() {
3095  SUB(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3096 }
3097 template<class T> template<Reg16 IXY> int CPUCore<T>::sub_xix() {
3098  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3099  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3100  T::setMemPtr(addr);
3101  SUB(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3102  return T::CC_DD + T::CC_CP_XIX;
3103 }
3104 
3105 // XOR r
3106 template<class T> inline void CPUCore<T>::XOR(byte reg) {
3107  setA(getA() ^ reg);
3108  byte f = 0;
3109  if (T::isR800()) {
3110  f |= ZSPTable[getA()];
3111  f |= getF() & (X_FLAG | Y_FLAG);
3112  } else {
3113  f |= ZSPXYTable[getA()];
3114  }
3115  setF(f);
3116 }
3117 template<class T> int CPUCore<T>::xor_a() {
3118  if (T::isR800()) {
3119  word t = 0 * 256 + ZSP0;
3120  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3121  } else {
3122  setAF(0 * 256 + ZSPXY0);
3123  }
3124  return T::CC_CP_R;
3125 }
3126 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::xor_R() {
3127  XOR(get8<SRC>()); return T::CC_CP_R + EE;
3128 }
3129 template<class T> int CPUCore<T>::xor_byte() {
3130  XOR(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3131 }
3132 template<class T> int CPUCore<T>::xor_xhl() {
3133  XOR(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3134 }
3135 template<class T> template<Reg16 IXY> int CPUCore<T>::xor_xix() {
3136  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3137  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3138  T::setMemPtr(addr);
3139  XOR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3140  return T::CC_DD + T::CC_CP_XIX;
3141 }
3142 
3143 
3144 // DEC r
3145 template<class T> inline byte CPUCore<T>::DEC(byte reg) {
3146  byte res = reg - 1;
3147  byte f = ((reg & ~res & 0x80) >> 5) | // V_FLAG
3148  (((res & 0x0F) + 1) & H_FLAG) |
3149  N_FLAG;
3150  if (T::isR800()) {
3151  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3152  f |= ZSTable[res];
3153  } else {
3154  f |= getF() & C_FLAG;
3155  f |= ZSXYTable[res];
3156  }
3157  setF(f);
3158  return res;
3159 }
3160 template<class T> template<Reg8 REG, int EE> int CPUCore<T>::dec_R() {
3161  set8<REG>(DEC(get8<REG>())); return T::CC_INC_R + EE;
3162 }
3163 template<class T> template<int EE> inline int CPUCore<T>::DEC_X(unsigned x) {
3164  byte val = DEC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3165  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3166  return T::CC_INC_XHL + EE;
3167 }
3168 template<class T> int CPUCore<T>::dec_xhl() {
3169  return DEC_X<0>(getHL());
3170 }
3171 template<class T> template<Reg16 IXY> int CPUCore<T>::dec_xix() {
3172  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_INC_XIX_1);
3173  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3174  T::setMemPtr(addr);
3175  return DEC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3176 }
3177 
3178 // INC r
3179 template<class T> inline byte CPUCore<T>::INC(byte reg) {
3180  reg++;
3181  byte f = ((reg & -reg & 0x80) >> 5) | // V_FLAG
3182  (((reg & 0x0F) - 1) & H_FLAG) |
3183  0; // N_FLAG
3184  if (T::isR800()) {
3185  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3186  f |= ZSTable[reg];
3187  } else {
3188  f |= getF() & C_FLAG;
3189  f |= ZSXYTable[reg];
3190  }
3191  setF(f);
3192  return reg;
3193 }
3194 template<class T> template<Reg8 REG, int EE> int CPUCore<T>::inc_R() {
3195  set8<REG>(INC(get8<REG>())); return T::CC_INC_R + EE;
3196 }
3197 template<class T> template<int EE> inline int CPUCore<T>::INC_X(unsigned x) {
3198  byte val = INC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3199  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3200  return T::CC_INC_XHL + EE;
3201 }
3202 template<class T> int CPUCore<T>::inc_xhl() {
3203  return INC_X<0>(getHL());
3204 }
3205 template<class T> template<Reg16 IXY> int CPUCore<T>::inc_xix() {
3206  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_INC_XIX_1);
3207  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3208  T::setMemPtr(addr);
3209  return INC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3210 }
3211 
3212 
3213 // ADC HL,ss
3214 template<class T> template<Reg16 REG> inline int CPUCore<T>::adc_hl_SS() {
3215  unsigned reg = get16<REG>();
3216  T::setMemPtr(getHL() + 1);
3217  unsigned res = getHL() + reg + ((getF() & C_FLAG) ? 1 : 0);
3218  byte f = (res >> 16) | // C_FLAG
3219  0; // N_FLAG
3220  if (T::isR800()) {
3221  f |= getF() & (X_FLAG | Y_FLAG);
3222  }
3223  if (res & 0xFFFF) {
3224  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3225  f |= 0; // Z_FLAG
3226  f |= ((getHL() ^ res) & (reg ^ res) & 0x8000) >> 13; // V_FLAG
3227  if (T::isR800()) {
3228  f |= (res >> 8) & S_FLAG;
3229  } else {
3230  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3231  }
3232  } else {
3233  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3234  f |= Z_FLAG;
3235  f |= (getHL() & reg & 0x8000) >> 13; // V_FLAG
3236  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3237  }
3238  setF(f);
3239  setHL(res);
3240  return T::CC_ADC_HL_SS;
3241 }
3242 template<class T> int CPUCore<T>::adc_hl_hl() {
3243  T::setMemPtr(getHL() + 1);
3244  unsigned res = 2 * getHL() + ((getF() & C_FLAG) ? 1 : 0);
3245  byte f = (res >> 16) | // C_FLAG
3246  0; // N_FLAG
3247  if (T::isR800()) {
3248  f |= getF() & (X_FLAG | Y_FLAG);
3249  }
3250  if (res & 0xFFFF) {
3251  f |= 0; // Z_FLAG
3252  f |= ((getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3253  if (T::isR800()) {
3254  f |= (res >> 8) & (H_FLAG | S_FLAG);
3255  } else {
3256  f |= (res >> 8) & (H_FLAG | S_FLAG | X_FLAG | Y_FLAG);
3257  }
3258  } else {
3259  f |= Z_FLAG;
3260  f |= (getHL() & 0x8000) >> 13; // V_FLAG
3261  f |= 0; // H_FLAG S_FLAG (X_FLAG Y_FLAG)
3262  }
3263  setF(f);
3264  setHL(res);
3265  return T::CC_ADC_HL_SS;
3266 }
3267 
3268 // ADD HL/IX/IY,ss
3269 template<class T> template<Reg16 REG1, Reg16 REG2, int EE> int CPUCore<T>::add_SS_TT() {
3270  unsigned reg1 = get16<REG1>();
3271  unsigned reg2 = get16<REG2>();
3272  T::setMemPtr(reg1 + 1);
3273  unsigned res = reg1 + reg2;
3274  byte f = (((reg1 ^ res ^ reg2) >> 8) & H_FLAG) |
3275  (res >> 16) | // C_FLAG
3276  0; // N_FLAG
3277  if (T::isR800()) {
3278  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3279  } else {
3280  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3281  f |= (res >> 8) & (X_FLAG | Y_FLAG);
3282  }
3283  setF(f);
3284  set16<REG1>(res & 0xFFFF);
3285  return T::CC_ADD_HL_SS + EE;
3286 }
3287 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::add_SS_SS() {
3288  unsigned reg = get16<REG>();
3289  T::setMemPtr(reg + 1);
3290  unsigned res = 2 * reg;
3291  byte f = (res >> 16) | // C_FLAG
3292  0; // N_FLAG
3293  if (T::isR800()) {
3294  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3295  f |= (res >> 8) & H_FLAG;
3296  } else {
3297  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3298  f |= (res >> 8) & (H_FLAG | X_FLAG | Y_FLAG);
3299  }
3300  setF(f);
3301  set16<REG>(res & 0xFFFF);
3302  return T::CC_ADD_HL_SS + EE;
3303 }
3304 
3305 // SBC HL,ss
3306 template<class T> template<Reg16 REG> inline int CPUCore<T>::sbc_hl_SS() {
3307  unsigned reg = get16<REG>();
3308  T::setMemPtr(getHL() + 1);
3309  unsigned res = getHL() - reg - ((getF() & C_FLAG) ? 1 : 0);
3310  byte f = ((res & 0x10000) ? C_FLAG : 0) |
3311  N_FLAG;
3312  if (T::isR800()) {
3313  f |= getF() & (X_FLAG | Y_FLAG);
3314  }
3315  if (res & 0xFFFF) {
3316  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3317  f |= 0; // Z_FLAG
3318  f |= ((reg ^ getHL()) & (getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3319  if (T::isR800()) {
3320  f |= (res >> 8) & S_FLAG;
3321  } else {
3322  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3323  }
3324  } else {
3325  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3326  f |= Z_FLAG;
3327  f |= ((reg ^ getHL()) & getHL() & 0x8000) >> 13; // V_FLAG
3328  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3329  }
3330  setF(f);
3331  setHL(res);
3332  return T::CC_ADC_HL_SS;
3333 }
3334 template<class T> int CPUCore<T>::sbc_hl_hl() {
3335  T::setMemPtr(getHL() + 1);
3336  byte f = T::isR800() ? (getF() & (X_FLAG | Y_FLAG)) : 0;
3337  if (getF() & C_FLAG) {
3338  f |= C_FLAG | H_FLAG | S_FLAG | N_FLAG;
3339  if (!T::isR800()) {
3340  f |= X_FLAG | Y_FLAG;
3341  }
3342  setHL(0xFFFF);
3343  } else {
3344  f |= Z_FLAG | N_FLAG;
3345  setHL(0);
3346  }
3347  setF(f);
3348  return T::CC_ADC_HL_SS;
3349 }
3350 
3351 // DEC ss
3352 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::dec_SS() {
3353  set16<REG>(get16<REG>() - 1); return T::CC_INC_SS + EE;
3354 }
3355 
3356 // INC ss
3357 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::inc_SS() {
3358  set16<REG>(get16<REG>() + 1); return T::CC_INC_SS + EE;
3359 }
3360 
3361 
3362 // BIT n,r
3363 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::bit_N_R() {
3364  byte reg = get8<REG>();
3365  byte f = 0; // N_FLAG
3366  if (T::isR800()) {
3367  // this is very different from Z80 (not only XY flags)
3368  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3369  f |= H_FLAG;
3370  f |= (reg & (1 << N)) ? 0 : Z_FLAG;
3371  } else {
3372  f |= ZSPHTable[reg & (1 << N)];
3373  f |= getF() & C_FLAG;
3374  f |= reg & (X_FLAG | Y_FLAG);
3375  }
3376  setF(f);
3377  return T::CC_BIT_R;
3378 }
3379 template<class T> template<unsigned N> inline int CPUCore<T>::bit_N_xhl() {
3380  byte m = RDMEM(getHL(), T::CC_BIT_XHL_1) & (1 << N);
3381  byte f = 0; // N_FLAG
3382  if (T::isR800()) {
3383  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3384  f |= H_FLAG;
3385  f |= m ? 0 : Z_FLAG;
3386  } else {
3387  f |= ZSPHTable[m];
3388  f |= getF() & C_FLAG;
3389  f |= (T::getMemPtr() >> 8) & (X_FLAG | Y_FLAG);
3390  }
3391  setF(f);
3392  return T::CC_BIT_XHL;
3393 }
3394 template<class T> template<unsigned N> inline int CPUCore<T>::bit_N_xix(unsigned addr) {
3395  T::setMemPtr(addr);
3396  byte m = RDMEM(addr, T::CC_DD + T::CC_BIT_XIX_1) & (1 << N);
3397  byte f = 0; // N_FLAG
3398  if (T::isR800()) {
3399  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3400  f |= H_FLAG;
3401  f |= m ? 0 : Z_FLAG;
3402  } else {
3403  f |= ZSPHTable[m];
3404  f |= getF() & C_FLAG;
3405  f |= (addr >> 8) & (X_FLAG | Y_FLAG);
3406  }
3407  setF(f);
3408  return T::CC_DD + T::CC_BIT_XIX;
3409 }
3410 
3411 // RES n,r
3412 static inline byte RES(unsigned b, byte reg) {
3413  return reg & ~(1 << b);
3414 }
3415 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::res_N_R() {
3416  set8<REG>(RES(N, get8<REG>())); return T::CC_SET_R;
3417 }
3418 template<class T> template<int EE> inline byte CPUCore<T>::RES_X(unsigned bit, unsigned addr) {
3419  byte res = RES(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3420  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3421  return res;
3422 }
3423 template<class T> template<unsigned N> int CPUCore<T>::res_N_xhl() {
3424  RES_X<0>(N, getHL()); return T::CC_SET_XHL;
3425 }
3426 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::res_N_xix_R(unsigned a) {
3427  T::setMemPtr(a);
3428  set8<REG>(RES_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3429  return T::CC_DD + T::CC_SET_XIX;
3430 }
3431 
3432 // SET n,r
3433 static inline byte SET(unsigned b, byte reg) {
3434  return reg | (1 << b);
3435 }
3436 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::set_N_R() {
3437  set8<REG>(SET(N, get8<REG>())); return T::CC_SET_R;
3438 }
3439 template<class T> template<int EE> inline byte CPUCore<T>::SET_X(unsigned bit, unsigned addr) {
3440  byte res = SET(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3441  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3442  return res;
3443 }
3444 template<class T> template<unsigned N> int CPUCore<T>::set_N_xhl() {
3445  SET_X<0>(N, getHL()); return T::CC_SET_XHL;
3446 }
3447 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::set_N_xix_R(unsigned a) {
3448  T::setMemPtr(a);
3449  set8<REG>(SET_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3450  return T::CC_DD + T::CC_SET_XIX;
3451 }
3452 
3453 // RL r
3454 template<class T> inline byte CPUCore<T>::RL(byte reg) {
3455  byte c = reg >> 7;
3456  reg = (reg << 1) | ((getF() & C_FLAG) ? 0x01 : 0);
3457  byte f = c ? C_FLAG : 0;
3458  if (T::isR800()) {
3459  f |= ZSPTable[reg];
3460  f |= getF() & (X_FLAG | Y_FLAG);
3461  } else {
3462  f |= ZSPXYTable[reg];
3463  }
3464  setF(f);
3465  return reg;
3466 }
3467 template<class T> template<int EE> inline byte CPUCore<T>::RL_X(unsigned x) {
3468  byte res = RL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3469  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3470  return res;
3471 }
3472 template<class T> template<Reg8 REG> int CPUCore<T>::rl_R() {
3473  set8<REG>(RL(get8<REG>())); return T::CC_SET_R;
3474 }
3475 template<class T> int CPUCore<T>::rl_xhl() {
3476  RL_X<0>(getHL()); return T::CC_SET_XHL;
3477 }
3478 template<class T> template<Reg8 REG> int CPUCore<T>::rl_xix_R(unsigned a) {
3479  T::setMemPtr(a);
3480  set8<REG>(RL_X<T::CC_DD + T::EE_SET_XIX>(a));
3481  return T::CC_DD + T::CC_SET_XIX;
3482 }
3483 
3484 // RLC r
3485 template<class T> inline byte CPUCore<T>::RLC(byte reg) {
3486  byte c = reg >> 7;
3487  reg = (reg << 1) | c;
3488  byte f = c ? C_FLAG : 0;
3489  if (T::isR800()) {
3490  f |= ZSPTable[reg];
3491  f |= getF() & (X_FLAG | Y_FLAG);
3492  } else {
3493  f |= ZSPXYTable[reg];
3494  }
3495  setF(f);
3496  return reg;
3497 }
3498 template<class T> template<int EE> inline byte CPUCore<T>::RLC_X(unsigned x) {
3499  byte res = RLC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3500  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3501  return res;
3502 }
3503 template<class T> template<Reg8 REG> int CPUCore<T>::rlc_R() {
3504  set8<REG>(RLC(get8<REG>())); return T::CC_SET_R;
3505 }
3506 template<class T> int CPUCore<T>::rlc_xhl() {
3507  RLC_X<0>(getHL()); return T::CC_SET_XHL;
3508 }
3509 template<class T> template<Reg8 REG> int CPUCore<T>::rlc_xix_R(unsigned a) {
3510  T::setMemPtr(a);
3511  set8<REG>(RLC_X<T::CC_DD + T::EE_SET_XIX>(a));
3512  return T::CC_DD + T::CC_SET_XIX;
3513 }
3514 
3515 // RR r
3516 template<class T> inline byte CPUCore<T>::RR(byte reg) {
3517  byte c = reg & 1;
3518  reg = (reg >> 1) | ((getF() & C_FLAG) << 7);
3519  byte f = c ? C_FLAG : 0;
3520  if (T::isR800()) {
3521  f |= ZSPTable[reg];
3522  f |= getF() & (X_FLAG | Y_FLAG);
3523  } else {
3524  f |= ZSPXYTable[reg];
3525  }
3526  setF(f);
3527  return reg;
3528 }
3529 template<class T> template<int EE> inline byte CPUCore<T>::RR_X(unsigned x) {
3530  byte res = RR(RDMEM(x, T::CC_SET_XHL_1 + EE));
3531  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3532  return res;
3533 }
3534 template<class T> template<Reg8 REG> int CPUCore<T>::rr_R() {
3535  set8<REG>(RR(get8<REG>())); return T::CC_SET_R;
3536 }
3537 template<class T> int CPUCore<T>::rr_xhl() {
3538  RR_X<0>(getHL()); return T::CC_SET_XHL;
3539 }
3540 template<class T> template<Reg8 REG> int CPUCore<T>::rr_xix_R(unsigned a) {
3541  T::setMemPtr(a);
3542  set8<REG>(RR_X<T::CC_DD + T::EE_SET_XIX>(a));
3543  return T::CC_DD + T::CC_SET_XIX;
3544 }
3545 
3546 // RRC r
3547 template<class T> inline byte CPUCore<T>::RRC(byte reg) {
3548  byte c = reg & 1;
3549  reg = (reg >> 1) | (c << 7);
3550  byte f = c ? C_FLAG : 0;
3551  if (T::isR800()) {
3552  f |= ZSPTable[reg];
3553  f |= getF() & (X_FLAG | Y_FLAG);
3554  } else {
3555  f |= ZSPXYTable[reg];
3556  }
3557  setF(f);
3558  return reg;
3559 }
3560 template<class T> template<int EE> inline byte CPUCore<T>::RRC_X(unsigned x) {
3561  byte res = RRC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3562  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3563  return res;
3564 }
3565 template<class T> template<Reg8 REG> int CPUCore<T>::rrc_R() {
3566  set8<REG>(RRC(get8<REG>())); return T::CC_SET_R;
3567 }
3568 template<class T> int CPUCore<T>::rrc_xhl() {
3569  RRC_X<0>(getHL()); return T::CC_SET_XHL;
3570 }
3571 template<class T> template<Reg8 REG> int CPUCore<T>::rrc_xix_R(unsigned a) {
3572  T::setMemPtr(a);
3573  set8<REG>(RRC_X<T::CC_DD + T::EE_SET_XIX>(a));
3574  return T::CC_DD + T::CC_SET_XIX;
3575 }
3576 
3577 // SLA r
3578 template<class T> inline byte CPUCore<T>::SLA(byte reg) {
3579  byte c = reg >> 7;
3580  reg <<= 1;
3581  byte f = c ? C_FLAG : 0;
3582  if (T::isR800()) {
3583  f |= ZSPTable[reg];
3584  f |= getF() & (X_FLAG | Y_FLAG);
3585  } else {
3586  f |= ZSPXYTable[reg];
3587  }
3588  setF(f);
3589  return reg;
3590 }
3591 template<class T> template<int EE> inline byte CPUCore<T>::SLA_X(unsigned x) {
3592  byte res = SLA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3593  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3594  return res;
3595 }
3596 template<class T> template<Reg8 REG> int CPUCore<T>::sla_R() {
3597  set8<REG>(SLA(get8<REG>())); return T::CC_SET_R;
3598 }
3599 template<class T> int CPUCore<T>::sla_xhl() {
3600  SLA_X<0>(getHL()); return T::CC_SET_XHL;
3601 }
3602 template<class T> template<Reg8 REG> int CPUCore<T>::sla_xix_R(unsigned a) {
3603  T::setMemPtr(a);
3604  set8<REG>(SLA_X<T::CC_DD + T::EE_SET_XIX>(a));
3605  return T::CC_DD + T::CC_SET_XIX;
3606 }
3607 
3608 // SLL r
3609 template<class T> inline byte CPUCore<T>::SLL(byte reg) {
3610  assert(!T::isR800()); // this instruction is Z80-only
3611  byte c = reg >> 7;
3612  reg = (reg << 1) | 1;
3613  byte f = c ? C_FLAG : 0;
3614  f |= ZSPXYTable[reg];
3615  setF(f);
3616  return reg;
3617 }
3618 template<class T> template<int EE> inline byte CPUCore<T>::SLL_X(unsigned x) {
3619  byte res = SLL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3620  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3621  return res;
3622 }
3623 template<class T> template<Reg8 REG> int CPUCore<T>::sll_R() {
3624  set8<REG>(SLL(get8<REG>())); return T::CC_SET_R;
3625 }
3626 template<class T> int CPUCore<T>::sll_xhl() {
3627  SLL_X<0>(getHL()); return T::CC_SET_XHL;
3628 }
3629 template<class T> template<Reg8 REG> int CPUCore<T>::sll_xix_R(unsigned a) {
3630  T::setMemPtr(a);
3631  set8<REG>(SLL_X<T::CC_DD + T::EE_SET_XIX>(a));
3632  return T::CC_DD + T::CC_SET_XIX;
3633 }
3634 template<class T> int CPUCore<T>::sll2() {
3635  assert(T::isR800()); // this instruction is R800-only
3636  byte f = (getF() & (X_FLAG | Y_FLAG)) |
3637  (getA() >> 7) | // C_FLAG
3638  0; // all other flags zero
3639  setF(f);
3640  return T::CC_DD + T::CC_SET_XIX; // TODO
3641 }
3642 
3643 // SRA r
3644 template<class T> inline byte CPUCore<T>::SRA(byte reg) {
3645  byte c = reg & 1;
3646  reg = (reg >> 1) | (reg & 0x80);
3647  byte f = c ? C_FLAG : 0;
3648  if (T::isR800()) {
3649  f |= ZSPTable[reg];
3650  f |= getF() & (X_FLAG | Y_FLAG);
3651  } else {
3652  f |= ZSPXYTable[reg];
3653  }
3654  setF(f);
3655  return reg;
3656 }
3657 template<class T> template<int EE> inline byte CPUCore<T>::SRA_X(unsigned x) {
3658  byte res = SRA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3659  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3660  return res;
3661 }
3662 template<class T> template<Reg8 REG> int CPUCore<T>::sra_R() {
3663  set8<REG>(SRA(get8<REG>())); return T::CC_SET_R;
3664 }
3665 template<class T> int CPUCore<T>::sra_xhl() {
3666  SRA_X<0>(getHL()); return T::CC_SET_XHL;
3667 }
3668 template<class T> template<Reg8 REG> int CPUCore<T>::sra_xix_R(unsigned a) {
3669  T::setMemPtr(a);
3670  set8<REG>(SRA_X<T::CC_DD + T::EE_SET_XIX>(a));
3671  return T::CC_DD + T::CC_SET_XIX;
3672 }
3673 
3674 // SRL R
3675 template<class T> inline byte CPUCore<T>::SRL(byte reg) {
3676  byte c = reg & 1;
3677  reg >>= 1;
3678  byte f = c ? C_FLAG : 0;
3679  if (T::isR800()) {
3680  f |= ZSPTable[reg];
3681  f |= getF() & (X_FLAG | Y_FLAG);
3682  } else {
3683  f |= ZSPXYTable[reg];
3684  }
3685  setF(f);
3686  return reg;
3687 }
3688 template<class T> template<int EE> inline byte CPUCore<T>::SRL_X(unsigned x) {
3689  byte res = SRL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3690  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3691  return res;
3692 }
3693 template<class T> template<Reg8 REG> int CPUCore<T>::srl_R() {
3694  set8<REG>(SRL(get8<REG>())); return T::CC_SET_R;
3695 }
3696 template<class T> int CPUCore<T>::srl_xhl() {
3697  SRL_X<0>(getHL()); return T::CC_SET_XHL;
3698 }
3699 template<class T> template<Reg8 REG> int CPUCore<T>::srl_xix_R(unsigned a) {
3700  T::setMemPtr(a);
3701  set8<REG>(SRL_X<T::CC_DD + T::EE_SET_XIX>(a));
3702  return T::CC_DD + T::CC_SET_XIX;
3703 }
3704 
3705 // RLA RLCA RRA RRCA
3706 template<class T> int CPUCore<T>::rla() {
3707  byte c = getF() & C_FLAG;
3708  byte f = (getA() & 0x80) ? C_FLAG : 0;
3709  if (T::isR800()) {
3710  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3711  } else {
3712  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3713  }
3714  setA((getA() << 1) | (c ? 1 : 0));
3715  if (!T::isR800()) {
3716  f |= getA() & (X_FLAG | Y_FLAG);
3717  }
3718  setF(f);
3719  return T::CC_RLA;
3720 }
3721 template<class T> int CPUCore<T>::rlca() {
3722  setA((getA() << 1) | (getA() >> 7));
3723  byte f = 0;
3724  if (T::isR800()) {
3725  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3726  f |= getA() & C_FLAG;
3727  } else {
3728  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3729  f |= getA() & (Y_FLAG | X_FLAG | C_FLAG);
3730  }
3731  setF(f);
3732  return T::CC_RLA;
3733 }
3734 template<class T> int CPUCore<T>::rra() {
3735  byte c = (getF() & C_FLAG) << 7;
3736  byte f = (getA() & 0x01) ? C_FLAG : 0;
3737  if (T::isR800()) {
3738  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3739  } else {
3740  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3741  }
3742  setA((getA() >> 1) | c);
3743  if (!T::isR800()) {
3744  f |= getA() & (X_FLAG | Y_FLAG);
3745  }
3746  setF(f);
3747  return T::CC_RLA;
3748 }
3749 template<class T> int CPUCore<T>::rrca() {
3750  byte f = getA() & C_FLAG;
3751  if (T::isR800()) {
3752  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3753  } else {
3754  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3755  }
3756  setA((getA() >> 1) | (getA() << 7));
3757  if (!T::isR800()) {
3758  f |= getA() & (X_FLAG | Y_FLAG);
3759  }
3760  setF(f);
3761  return T::CC_RLA;
3762 }
3763 
3764 
3765 // RLD
3766 template<class T> int CPUCore<T>::rld() {
3767  byte val = RDMEM(getHL(), T::CC_RLD_1);
3768  T::setMemPtr(getHL() + 1);
3769  WRMEM(getHL(), (val << 4) | (getA() & 0x0F), T::CC_RLD_2);
3770  setA((getA() & 0xF0) | (val >> 4));
3771  byte f = 0;
3772  if (T::isR800()) {
3773  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3774  f |= ZSPTable[getA()];
3775  } else {
3776  f |= getF() & C_FLAG;
3777  f |= ZSPXYTable[getA()];
3778  }
3779  setF(f);
3780  return T::CC_RLD;
3781 }
3782 
3783 // RRD
3784 template<class T> int CPUCore<T>::rrd() {
3785  byte val = RDMEM(getHL(), T::CC_RLD_1);
3786  T::setMemPtr(getHL() + 1);
3787  WRMEM(getHL(), (val >> 4) | (getA() << 4), T::CC_RLD_2);
3788  setA((getA() & 0xF0) | (val & 0x0F));
3789  byte f = 0;
3790  if (T::isR800()) {
3791  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3792  f |= ZSPTable[getA()];
3793  } else {
3794  f |= getF() & C_FLAG;
3795  f |= ZSPXYTable[getA()];
3796  }
3797  setF(f);
3798  return T::CC_RLD;
3799 }
3800 
3801 
3802 // PUSH ss
3803 template<class T> template<int EE> inline void CPUCore<T>::PUSH(unsigned reg) {
3804  setSP(getSP() - 2);
3805  WR_WORD_rev<true, true>(getSP(), reg, T::CC_PUSH_1 + EE);
3806 }
3807 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::push_SS() {
3808  PUSH<EE>(get16<REG>()); return T::CC_PUSH + EE;
3809 }
3810 
3811 // POP ss
3812 template<class T> template<int EE> inline unsigned CPUCore<T>::POP() {
3813  unsigned addr = getSP();
3814  setSP(addr + 2);
3815  if (T::isR800()) {
3816  // handles both POP and RET instructions (RET with condition = true)
3817  if (EE == 0) { // not reti/retn, not pop ix/iy
3818  setCurrentPopRet();
3819  // No need for setSlowInstructions()
3820  // -> this only matters directly after a CALL
3821  // instruction and in that case we're still
3822  // executing slow instructions.
3823  }
3824  }
3825  return RD_WORD(addr, T::CC_POP_1 + EE);
3826 }
3827 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::pop_SS() {
3828  set16<REG>(POP<EE>()); return T::CC_POP + EE;
3829 }
3830 
3831 
3832 // CALL nn / CALL cc,nn
3833 template<class T> template<typename COND> int CPUCore<T>::call(COND cond) {
3834  unsigned addr = RD_WORD_PC(T::CC_CALL_1);
3835  T::setMemPtr(addr);
3836  if (cond(getF())) {
3837  PUSH<T::EE_CALL>(getPC());
3838  setPC(addr);
3839  if (T::isR800()) {
3840  setCurrentCall();
3841  setSlowInstructions();
3842  }
3843  return T::CC_CALL_A;
3844  } else {
3845  return T::CC_CALL_B;
3846  }
3847 }
3848 
3849 
3850 // RST n
3851 template<class T> template<unsigned ADDR> int CPUCore<T>::rst() {
3852  PUSH<0>(getPC());
3853  T::setMemPtr(ADDR);
3854  setPC(ADDR);
3855  if (T::isR800()) {
3856  setCurrentCall();
3857  setSlowInstructions();
3858  }
3859  return T::CC_RST;
3860 }
3861 
3862 
3863 // RET
3864 template<class T> template<int EE, typename COND> inline int CPUCore<T>::RET(COND cond) {
3865  if (cond(getF())) {
3866  unsigned addr = POP<EE>();
3867  T::setMemPtr(addr);
3868  setPC(addr);
3869  return T::CC_RET_A + EE;
3870  } else {
3871  return T::CC_RET_B + EE;
3872  }
3873 }
3874 template<class T> template<typename COND> int CPUCore<T>::ret(COND cond) {
3875  return RET<T::EE_RET_C>(cond);
3876 }
3877 template<class T> int CPUCore<T>::ret() {
3878  return RET<0>(CondTrue());
3879 }
3880 template<class T> int CPUCore<T>::retn() { // also reti
3881  setIFF1(getIFF2());
3882  setSlowInstructions();
3883  return RET<T::EE_RETN>(CondTrue());
3884 }
3885 
3886 
3887 // JP ss
3888 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::jp_SS() {
3889  setPC(get16<REG>()); T::R800ForcePageBreak(); return T::CC_JP_HL + EE;
3890 }
3891 
3892 // JP nn / JP cc,nn
3893 template<class T> template<typename COND> int CPUCore<T>::jp(COND cond) {
3894  unsigned addr = RD_WORD_PC(T::CC_JP_1);
3895  T::setMemPtr(addr);
3896  if (cond(getF())) {
3897  setPC(addr);
3898  T::R800ForcePageBreak();
3899  return T::CC_JP_A;
3900  } else {
3901  return T::CC_JP_B;
3902  }
3903 }
3904 
3905 // JR e
3906 template<class T> template<typename COND> int CPUCore<T>::jr(COND cond) {
3907  int8_t ofst = RDMEM_OPCODE(T::CC_JR_1);
3908  if (cond(getF())) {
3909  if ((getPC() & 0xFF) == 0) {
3910  // On R800, when this instruction is located in the
3911  // last two byte of a page (a page is a 256-byte
3912  // (aligned) memory block) and even if we jump back,
3913  // thus fetching the next opcode byte does not cause a
3914  // page-break, there still is one cycle overhead. It's
3915  // as-if there is a page-break.
3916  //
3917  // This could be explained by some (very limited)
3918  // pipeline behaviour in R800: it seems that the
3919  // decision to cause a page-break on the next
3920  // instruction is already made before the jump
3921  // destination address for the current instruction is
3922  // calculated (though a destination address in another
3923  // page is also a reason for a page-break).
3924  //
3925  // It's likely all instructions behave like this, but I
3926  // think we can get away with only explicitly emulating
3927  // this behaviour in the djnz and the jr (conditional
3928  // or not) instructions: all other instructions that
3929  // cause the PC to change in a non-incremental way do
3930  // already force a pagebreak for another reason, so
3931  // this effect is masked. Examples of such instructions
3932  // are: JP, RET, CALL, RST, all repeated block
3933  // instructions, accepting an IRQ, (are there more
3934  // instructions are events that change PC?)
3935  //
3936  // See doc/r800-djnz.txt for more details.
3937  T::R800ForcePageBreak();
3938  }
3939  setPC((getPC() + ofst) & 0xFFFF);
3940  T::setMemPtr(getPC());
3941  return T::CC_JR_A;
3942  } else {
3943  return T::CC_JR_B;
3944  }
3945 }
3946 
3947 // DJNZ e
3948 template<class T> int CPUCore<T>::djnz() {
3949  byte b = getB() - 1;
3950  setB(b);
3951  int8_t ofst = RDMEM_OPCODE(T::CC_JR_1 + T::EE_DJNZ);
3952  if (b) {
3953  if ((getPC() & 0xFF) == 0) {
3954  // See comment in jr()
3955  T::R800ForcePageBreak();
3956  }
3957  setPC((getPC() + ofst) & 0xFFFF);
3958  T::setMemPtr(getPC());
3959  return T::CC_JR_A + T::EE_DJNZ;
3960  } else {
3961  return T::CC_JR_B + T::EE_DJNZ;
3962  }
3963 }
3964 
3965 // EX (SP),ss
3966 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ex_xsp_SS() {
3967  unsigned res = RD_WORD_impl<true, false>(getSP(), T::CC_EX_SP_HL_1 + EE);
3968  T::setMemPtr(res);
3969  WR_WORD_rev<false, true>(getSP(), get16<REG>(), T::CC_EX_SP_HL_2 + EE);
3970  set16<REG>(res);
3971  return T::CC_EX_SP_HL + EE;
3972 }
3973 
3974 // IN r,(c)
3975 template<class T> template<Reg8 REG> int CPUCore<T>::in_R_c() {
3976  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_R_C_1);
3977  T::setMemPtr(getBC() + 1);
3978  byte res = READ_PORT(getBC(), T::CC_IN_R_C_1);
3979  byte f = 0;
3980  if (T::isR800()) {
3981  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3982  f |= ZSPTable[res];
3983  } else {
3984  f |= getF() & C_FLAG;
3985  f |= ZSPXYTable[res];
3986  }
3987  setF(f);
3988  set8<REG>(res);
3989  return T::CC_IN_R_C;
3990 }
3991 
3992 // IN a,(n)
3993 template<class T> int CPUCore<T>::in_a_byte() {
3994  unsigned y = RDMEM_OPCODE(T::CC_IN_A_N_1) + 256 * getA();
3995  T::setMemPtr(y + 1);
3996  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_A_N_2);
3997  setA(READ_PORT(y, T::CC_IN_A_N_2));
3998  return T::CC_IN_A_N;
3999 }
4000 
4001 // OUT (c),r
4002 template<class T> template<Reg8 REG> int CPUCore<T>::out_c_R() {
4003  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4004  T::setMemPtr(getBC() + 1);
4005  WRITE_PORT(getBC(), get8<REG>(), T::CC_OUT_C_R_1);
4006  return T::CC_OUT_C_R;
4007 }
4008 template<class T> int CPUCore<T>::out_c_0() {
4009  // TODO not on R800
4010  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4011  T::setMemPtr(getBC() + 1);
4012  byte out_c_x = isTurboR ? 255 : 0;
4013  WRITE_PORT(getBC(), out_c_x, T::CC_OUT_C_R_1);
4014  return T::CC_OUT_C_R;
4015 }
4016 
4017 // OUT (n),a
4018 template<class T> int CPUCore<T>::out_byte_a() {
4019  byte port = RDMEM_OPCODE(T::CC_OUT_N_A_1);
4020  unsigned y = (getA() << 8) | port;
4021  T::setMemPtr((getA() << 8) | ((port + 1) & 255));
4022  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_N_A_2);
4023  WRITE_PORT(y, getA(), T::CC_OUT_N_A_2);
4024  return T::CC_OUT_N_A;
4025 }
4026 
4027 
4028 // block CP
4029 template<class T> inline int CPUCore<T>::BLOCK_CP(int increase, bool repeat) {
4030  T::setMemPtr(T::getMemPtr() + increase);
4031  byte val = RDMEM(getHL(), T::CC_CPI_1);
4032  byte res = getA() - val;
4033  setHL(getHL() + increase);
4034  setBC(getBC() - 1);
4035  byte f = ((getA() ^ val ^ res) & H_FLAG) |
4036  ZSTable[res] |
4037  N_FLAG |
4038  (getBC() ? V_FLAG : 0);
4039  if (T::isR800()) {
4040  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4041  } else {
4042  f |= getF() & C_FLAG;
4043  unsigned k = res - ((f & H_FLAG) >> 4);
4044  f |= (k << 4) & Y_FLAG; // bit 1 -> flag 5
4045  f |= k & X_FLAG; // bit 3 -> flag 3
4046  }
4047  setF(f);
4048  if (repeat && getBC() && res) {
4049  setPC(getPC() - 2);
4050  T::setMemPtr(getPC() + 1);
4051  return T::CC_CPIR;
4052  } else {
4053  return T::CC_CPI;
4054  }
4055 }
4056 template<class T> int CPUCore<T>::cpd() { return BLOCK_CP(-1, false); }
4057 template<class T> int CPUCore<T>::cpi() { return BLOCK_CP( 1, false); }
4058 template<class T> int CPUCore<T>::cpdr() { return BLOCK_CP(-1, true ); }
4059 template<class T> int CPUCore<T>::cpir() { return BLOCK_CP( 1, true ); }
4060 
4061 
4062 // block LD
4063 template<class T> inline int CPUCore<T>::BLOCK_LD(int increase, bool repeat) {
4064  byte val = RDMEM(getHL(), T::CC_LDI_1);
4065  WRMEM(getDE(), val, T::CC_LDI_2);
4066  setHL(getHL() + increase);
4067  setDE(getDE() + increase);
4068  setBC(getBC() - 1);
4069  byte f = getBC() ? V_FLAG : 0;
4070  if (T::isR800()) {
4071  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG | X_FLAG | Y_FLAG);
4072  } else {
4073  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG);
4074  f |= ((getA() + val) << 4) & Y_FLAG; // bit 1 -> flag 5
4075  f |= (getA() + val) & X_FLAG; // bit 3 -> flag 3
4076  }
4077  setF(f);
4078  if (repeat && getBC()) {
4079  setPC(getPC() - 2);
4080  T::setMemPtr(getPC() + 1);
4081  return T::CC_LDIR;
4082  } else {
4083  return T::CC_LDI;
4084  }
4085 }
4086 template<class T> int CPUCore<T>::ldd() { return BLOCK_LD(-1, false); }
4087 template<class T> int CPUCore<T>::ldi() { return BLOCK_LD( 1, false); }
4088 template<class T> int CPUCore<T>::lddr() { return BLOCK_LD(-1, true ); }
4089 template<class T> int CPUCore<T>::ldir() { return BLOCK_LD( 1, true ); }
4090 
4091 
4092 // block IN
4093 template<class T> inline int CPUCore<T>::BLOCK_IN(int increase, bool repeat) {
4094  // TODO R800 flags
4095  if (T::isR800()) T::waitForEvenCycle(T::CC_INI_1);
4096  T::setMemPtr(getBC() + increase);
4097  setBC(getBC() - 0x100); // decr before use
4098  byte val = READ_PORT(getBC(), T::CC_INI_1);
4099  WRMEM(getHL(), val, T::CC_INI_2);
4100  setHL(getHL() + increase);
4101  unsigned k = val + ((getC() + increase) & 0xFF);
4102  byte b = getB();
4103  setF(((val & S_FLAG) >> 6) | // N_FLAG
4104  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4105  ZSXYTable[b] |
4106  (ZSPXYTable[(k & 0x07) ^ b] & P_FLAG));
4107  if (repeat && b) {
4108  setPC(getPC() - 2);
4109  return T::CC_INIR;
4110  } else {
4111  return T::CC_INI;
4112  }
4113 }
4114 template<class T> int CPUCore<T>::ind() { return BLOCK_IN(-1, false); }
4115 template<class T> int CPUCore<T>::ini() { return BLOCK_IN( 1, false); }
4116 template<class T> int CPUCore<T>::indr() { return BLOCK_IN(-1, true ); }
4117 template<class T> int CPUCore<T>::inir() { return BLOCK_IN( 1, true ); }
4118 
4119 
4120 // block OUT
4121 template<class T> inline int CPUCore<T>::BLOCK_OUT(int increase, bool repeat) {
4122  // TODO R800 flags
4123  byte val = RDMEM(getHL(), T::CC_OUTI_1);
4124  setHL(getHL() + increase);
4125  if (T::isR800()) T::waitForEvenCycle(T::CC_OUTI_2);
4126  WRITE_PORT(getBC(), val, T::CC_OUTI_2);
4127  setBC(getBC() - 0x100); // decr after use
4128  T::setMemPtr(getBC() + increase);
4129  unsigned k = val + getL();
4130  byte b = getB();
4131  setF(((val & S_FLAG) >> 6) | // N_FLAG
4132  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4133  ZSXYTable[b] |
4134  (ZSPXYTable[(k & 0x07) ^ b] & P_FLAG));
4135  if (repeat && b) {
4136  setPC(getPC() - 2);
4137  return T::CC_OTIR;
4138  } else {
4139  return T::CC_OUTI;
4140  }
4141 }
4142 template<class T> int CPUCore<T>::outd() { return BLOCK_OUT(-1, false); }
4143 template<class T> int CPUCore<T>::outi() { return BLOCK_OUT( 1, false); }
4144 template<class T> int CPUCore<T>::otdr() { return BLOCK_OUT(-1, true ); }
4145 template<class T> int CPUCore<T>::otir() { return BLOCK_OUT( 1, true ); }
4146 
4147 
4148 // various
4149 template<class T> int CPUCore<T>::nop() { return T::CC_NOP; }
4150 template<class T> int CPUCore<T>::ccf() {
4151  byte f = 0;
4152  if (T::isR800()) {
4153  // H flag is different from Z80 (and as always XY flags as well)
4154  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | X_FLAG | Y_FLAG | H_FLAG);
4155  } else {
4156  f |= (getF() & C_FLAG) << 4; // H_FLAG
4157  // only set X(Y) flag (don't reset if already set)
4158  if (isTurboR) {
4159  // Y flag is not changed on a turboR-Z80
4160  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | Y_FLAG);
4161  f |= (getF() | getA()) & X_FLAG;
4162  } else {
4163  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4164  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4165  }
4166  }
4167  f ^= C_FLAG;
4168  setF(f);
4169  return T::CC_CCF;
4170 }
4171 template<class T> int CPUCore<T>::cpl() {
4172  setA(getA() ^ 0xFF);
4173  byte f = H_FLAG | N_FLAG;
4174  if (T::isR800()) {
4175  f |= getF();
4176  } else {
4177  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4178  f |= getA() & (X_FLAG | Y_FLAG);
4179  }
4180  setF(f);
4181  return T::CC_CPL;
4182 }
4183 template<class T> int CPUCore<T>::daa() {
4184  byte a = getA();
4185  byte f = getF();
4186  byte adjust = 0;
4187  if ((f & H_FLAG) || ((getA() & 0xf) > 9)) adjust += 6;
4188  if ((f & C_FLAG) || (getA() > 0x99)) adjust += 0x60;
4189  if (f & N_FLAG) a -= adjust; else a += adjust;
4190  if (T::isR800()) {
4191  f &= C_FLAG | N_FLAG | X_FLAG | Y_FLAG;
4192  f |= ZSPTable[a];
4193  } else {
4194  f &= C_FLAG | N_FLAG;
4195  f |= ZSPXYTable[a];
4196  }
4197  f |= (getA() > 0x99) | ((getA() ^ a) & H_FLAG);
4198  setA(a);
4199  setF(f);
4200  return T::CC_DAA;
4201 }
4202 template<class T> int CPUCore<T>::neg() {
4203  // alternative: LUT word negTable[256]
4204  unsigned a = getA();
4205  unsigned res = -signed(a);
4206  byte f = ((res & 0x100) ? C_FLAG : 0) |
4207  N_FLAG |
4208  ((res ^ a) & H_FLAG) |
4209  ((a & res & 0x80) >> 5); // V_FLAG
4210  if (T::isR800()) {
4211  f |= ZSTable[res & 0xFF];
4212  f |= getF() & (X_FLAG | Y_FLAG);
4213  } else {
4214  f |= ZSXYTable[res & 0xFF];
4215  }
4216  setF(f);
4217  setA(res);
4218  return T::CC_NEG;
4219 }
4220 template<class T> int CPUCore<T>::scf() {
4221  byte f = C_FLAG;
4222  if (T::isR800()) {
4223  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
4224  } else {
4225  // only set X(Y) flag (don't reset if already set)
4226  if (isTurboR) {
4227  // Y flag is not changed on a turboR-Z80
4228  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | Y_FLAG);
4229  f |= (getF() | getA()) & X_FLAG;
4230  } else {
4231  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
4232  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4233  }
4234  }
4235  setF(f);
4236  return T::CC_SCF;
4237 }
4238 
4239 template<class T> int CPUCore<T>::ex_af_af() {
4240  unsigned t = getAF2(); setAF2(getAF()); setAF(t);
4241  return T::CC_EX;
4242 }
4243 template<class T> int CPUCore<T>::ex_de_hl() {
4244  unsigned t = getDE(); setDE(getHL()); setHL(t);
4245  return T::CC_EX;
4246 }
4247 template<class T> int CPUCore<T>::exx() {
4248  unsigned t1 = getBC2(); setBC2(getBC()); setBC(t1);
4249  unsigned t2 = getDE2(); setDE2(getDE()); setDE(t2);
4250  unsigned t3 = getHL2(); setHL2(getHL()); setHL(t3);
4251  return T::CC_EX;
4252 }
4253 
4254 template<class T> int CPUCore<T>::di() {
4255  setIFF1(false);
4256  setIFF2(false);
4257  return T::CC_DI;
4258 }
4259 template<class T> int CPUCore<T>::ei() {
4260  setIFF1(true);
4261  setIFF2(true);
4262  setCurrentEI(); // no ints directly after this instr
4263  setSlowInstructions();
4264  return T::CC_EI;
4265 }
4266 template<class T> int CPUCore<T>::halt() {
4267  setHALT(true);
4268  setSlowInstructions();
4269 
4270  if (!(getIFF1() || getIFF2())) {
4271  diHaltCallback.execute();
4272  }
4273  return T::CC_HALT;
4274 }
4275 template<class T> template<unsigned N> int CPUCore<T>::im_N() {
4276  setIM(N); return T::CC_IM;
4277 }
4278 
4279 // LD A,I/R
4280 template<class T> template<Reg8 REG> int CPUCore<T>::ld_a_IR() {
4281  setA(get8<REG>());
4282  byte f = getIFF2() ? V_FLAG : 0;
4283  if (T::isR800()) {
4284  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4285  f |= ZSTable[getA()];
4286  } else {
4287  f |= getF() & C_FLAG;
4288  f |= ZSXYTable[getA()];
4289  // see comment in the IRQ acceptance part of executeSlow().
4290  setCurrentLDAI(); // only Z80 (not R800) has this quirk
4291  setSlowInstructions();
4292  }
4293  setF(f);
4294  return T::CC_LD_A_I;
4295 }
4296 
4297 // LD I/R,A
4298 template<class T> int CPUCore<T>::ld_r_a() {
4299  // This code sequence:
4300  // XOR A / LD R,A / LD A,R
4301  // gives A=2 for Z80, but A=1 for R800. The difference can possibly be
4302  // explained by a difference in the relative time between writing the
4303  // new value to the R register and increasing the R register per M1
4304  // cycle. Here we implemented the R800 behaviour by storing 'A-1' into
4305  // R, that's good enough for now.
4306  byte val = getA();
4307  if (T::isR800()) val -= 1;
4308  setR(val);
4309  return T::CC_LD_A_I;
4310 }
4311 template<class T> int CPUCore<T>::ld_i_a() {
4312  setI(getA());
4313  return T::CC_LD_A_I;
4314 }
4315 
4316 // MULUB A,r
4317 template<class T> template<Reg8 REG> int CPUCore<T>::mulub_a_R() {
4318  assert(T::isR800()); // this instruction is R800-only
4319  // Verified on real R800:
4320  // YHXN flags are unchanged
4321  // SV flags are reset
4322  // Z flag is set when result is zero
4323  // C flag is set when result doesn't fit in 8-bit
4324  setHL(unsigned(getA()) * get8<REG>());
4325  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4326  0 | // S_FLAG V_FLAG
4327  (getHL() ? 0 : Z_FLAG) |
4328  ((getHL() & 0xFF00) ? C_FLAG : 0));
4329  return T::CC_MULUB;
4330 }
4331 
4332 // MULUW HL,ss
4333 template<class T> template<Reg16 REG> int CPUCore<T>::muluw_hl_SS() {
4334  assert(T::isR800()); // this instruction is R800-only
4335  // Verified on real R800:
4336  // YHXN flags are unchanged
4337  // SV flags are reset
4338  // Z flag is set when result is zero
4339  // C flag is set when result doesn't fit in 16-bit
4340  unsigned res = unsigned(getHL()) * get16<REG>();
4341  setDE(res >> 16);
4342  setHL(res & 0xffff);
4343  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4344  0 | // S_FLAG V_FLAG
4345  (res ? 0 : Z_FLAG) |
4346  ((res & 0xFFFF0000) ? C_FLAG : 0));
4347  return T::CC_MULUW;
4348 }
4349 
4350 
4351 // versions:
4352 // 1 -> initial version
4353 // 2 -> moved memptr from here to Z80TYPE (and not to R800TYPE)
4354 // 3 -> timing of the emulation changed (no changes in serialization)
4355 // 4 -> timing of the emulation changed again (see doc/internal/r800-call.txt)
4356 template<class T> template<typename Archive>
4357 void CPUCore<T>::serialize(Archive& ar, unsigned version)
4358 {
4359  T::serialize(ar, version);
4360  ar.serialize("regs", static_cast<CPURegs&>(*this));
4361  if (ar.versionBelow(version, 2)) {
4362  unsigned mptr = 0; // dummy value (avoid warning)
4363  ar.serialize("memptr", mptr);
4364  T::setMemPtr(mptr);
4365  }
4366 
4367  if (ar.isLoader()) {
4368  invalidateMemCache(0x0000, 0x10000);
4369  }
4370 
4371  // don't serialize
4372  // IRQStatus
4373  // NMIStatus, nmiEdge
4374  // slowInstructions
4375  // exitLoop
4376 
4377  if (T::isR800() && ar.versionBelow(version, 4)) {
4378  motherboard.getMSXCliComm().printWarning(
4379  "Loading an old savestate: the timing of the R800 "
4380  "emulation has changed. This may cause synchronization "
4381  "problems in replay.");
4382  }
4383 }
4384 
4385 // Force template instantiation
4386 template class CPUCore<Z80TYPE>;
4387 template class CPUCore<R800TYPE>;
4388 
4391 
4392 } // namespace openmsx
#define CASE(X)
void doReset(EmuTime::param time)
Reset the CPU.
Definition: CPUCore.cc:358
bool operator()(byte f) const
Definition: CPUCore.cc:258
bool operator()(byte f) const
Definition: CPUCore.cc:256
EmuTime::param getCurrentTime() const
Definition: CPUCore.cc:343
void setI(byte x)
Definition: CPURegs.hh:107
static bool checkBreakPoints(unsigned pc, MSXMotherBoard &motherBoard)
byte getC() const
Definition: CPURegs.hh:26
bool isM1Cycle(unsigned address) const
Definition: CPUCore.cc:491
const byte * getReadCacheLine(word start) const
Test that the memory in the interval [start, start + CacheLine::SIZE) is cacheable for reading...
void setBC2(unsigned x)
Definition: CPURegs.hh:98
unsigned getPC() const
Definition: CPURegs.hh:58
unsigned getSP() const
Definition: CPURegs.hh:59
void setC(byte x)
Definition: CPURegs.hh:71
size_type size() const
Definition: array_ref.hh:61
static const int CLOCK_FREQ
Definition: R800.hh:33
#define NEVER_INLINE
Definition: inline.hh:17
bool prev2WasCall() const
Definition: CPURegs.hh:165
#define ALWAYS_INLINE
Definition: inline.hh:16
#define unlikely(x)
Definition: likely.hh:15
void exitCPULoopAsync()
Similar to exitCPULoopSync(), but this method may be called from any thread.
Definition: CPUCore.cc:422
void setR(byte x)
Definition: CPURegs.hh:108
void setFreq(unsigned freq)
Change the clock freq.
Definition: CPUCore.cc:557
byte getR() const
Definition: CPURegs.hh:63
void setExtHALT(bool x)
Definition: CPURegs.hh:112
void disasmCommand(Interpreter &interp, array_ref< TclObject > tokens, TclObject &result) const
Definition: CPUCore.cc:530
void printWarning(string_ref message)
Definition: CliComm.cc:28
bool prevWasEI() const
Definition: CPURegs.hh:157
void setB(byte x)
Definition: CPURegs.hh:70
uint8_t byte
8 bit unsigned integer
Definition: openmsx.hh:26
void lowerNMI()
Lowers the non-maskable interrupt count.
Definition: CPUCore.cc:485
TclObject execute()
Definition: TclCallback.cc:42
bool operator()(byte f) const
Definition: CPUCore.cc:262
void setFastForward(bool fastForward_)
unsigned dasm(const MSXCPUInterface &interf, word pc, byte buf[4], std::string &dest, EmuTime::param time)
Disassemble.
Definition: Dasm.cc:18
void writeMem(word address, byte value, EmuTime::param time)
This writes a byte to the currently selected device.
void setIM(byte x)
Definition: CPURegs.hh:106
bool operator()(byte f) const
Definition: CPUCore.cc:259
CPUCore(MSXMotherBoard &motherboard, const std::string &name, const BooleanSetting &traceSetting, TclCallback &diHaltCallback, EmuTime::param time)
Definition: CPUCore.cc:295
bool operator()(byte f) const
Definition: CPUCore.cc:257
void setE(byte x)
Definition: CPURegs.hh:73
bool getIFF1() const
Definition: CPURegs.hh:64
bool operator()(byte) const
Definition: CPUCore.cc:264
unsigned getBC() const
Definition: CPURegs.hh:49
void setIFF1(bool x)
Definition: CPURegs.hh:109
void setIY(unsigned x)
Definition: CPURegs.hh:102
void setIYh(byte x)
Definition: CPURegs.hh:86
void exitCPULoopSync()
Request to exit the main CPU emulation loop.
Definition: CPUCore.cc:427
void setNextSyncPoint(EmuTime::param time)
Definition: CPUCore.cc:514
EmuTime::param getNext() const
TODO.
Definition: Scheduler.hh:55
void endInstruction()
Definition: CPURegs.hh:175
#define NEXT
byte getIYl() const
Definition: CPURegs.hh:42
#define NEXT_STOP
void setPC(unsigned x)
Definition: CPURegs.hh:103
byte getIM() const
Definition: CPURegs.hh:61
unsigned getHL() const
Definition: CPURegs.hh:51
void setIX(unsigned x)
Definition: CPURegs.hh:101
void setIYl(byte x)
Definition: CPURegs.hh:87
void setDE(unsigned x)
Definition: CPURegs.hh:95
byte * getWriteCacheLine(word start) const
Test that the memory in the interval [start, start + CacheLine::SIZE) is cacheable for writing...
bool prevWasPopRet() const
Definition: CPURegs.hh:169
void incR(byte x)
Definition: CPURegs.hh:114
This class implements a subset of the proposal for std::array_ref (proposed for the next c++ standard...
Definition: array_ref.hh:19
unsigned getAF2() const
Definition: CPURegs.hh:52
void writeIO(word port, byte value, EmuTime::param time)
This writes a byte to the given IO-port.
void checkNoCurrentFlags() const
Definition: CPURegs.hh:186
bool prevWasLDAI() const
Definition: CPURegs.hh:161
void setCurrentLDAI()
Definition: CPURegs.hh:144
unsigned getHL2() const
Definition: CPURegs.hh:55
void setDE2(unsigned x)
Definition: CPURegs.hh:99
byte getHALT() const
Definition: CPURegs.hh:66
void clearPrevious()
Definition: CPURegs.hh:180
static void setStep(bool x)
void setA(byte x)
Definition: CPURegs.hh:68
void setL(byte x)
Definition: CPURegs.hh:75
Thanks to enen for testing this on a real cartridge:
Definition: Autofire.cc:5
bool operator()(byte f) const
Definition: CPUCore.cc:260
void setH(byte x)
Definition: CPURegs.hh:74
unsigned getIX() const
Definition: CPURegs.hh:56
byte getIYh() const
Definition: CPURegs.hh:41
byte getH() const
Definition: CPURegs.hh:29
EmuTime waitCycles(EmuTime::param time, unsigned cycles)
Definition: CPUCore.cc:504
void raiseIRQ()
Raises the maskable interrupt count.
Definition: CPUCore.cc:457
void setAF(unsigned x)
Definition: CPURegs.hh:93
void setHALT(bool x)
Definition: CPURegs.hh:111
byte getD() const
Definition: CPURegs.hh:27
unsigned getAF() const
Definition: CPURegs.hh:48
static const int CLOCK_FREQ
Definition: Z80.hh:17
void setHL2(unsigned x)
Definition: CPURegs.hh:100
bool operator()(byte f) const
Definition: CPUCore.cc:263
void execute(bool fastForward)
Definition: CPUCore.cc:2529
uint16_t word
16 bit unsigned integer
Definition: openmsx.hh:29
void addListElement(string_ref element)
Definition: TclObject.cc:69
byte getL() const
Definition: CPURegs.hh:30
void lowerIRQ()
Lowers the maskable interrupt count.
Definition: CPUCore.cc:466
void setCurrentEI()
Definition: CPURegs.hh:140
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
Definition: serialize.hh:840
void wait(EmuTime::param time)
Definition: CPUCore.cc:497
void setIXl(byte x)
Definition: CPURegs.hh:85
byte readIO(word port, EmuTime::param time)
This read a byte from the given IO-port.
#define NEXT_EI
size_t size() const
void warp(EmuTime::param time)
Definition: CPUCore.cc:337
byte getIXh() const
Definition: CPURegs.hh:39
unsigned getIY() const
Definition: CPURegs.hh:57
#define likely(x)
Definition: likely.hh:14
void setF(byte x)
Definition: CPURegs.hh:69
void setD(byte x)
Definition: CPURegs.hh:72
byte getF() const
Definition: CPURegs.hh:24
byte getB() const
Definition: CPURegs.hh:25
byte getA() const
Definition: CPURegs.hh:23
void schedule(EmuTime::param limit)
Schedule till a certain moment in time.
Definition: Scheduler.hh:63
void serialize(Archive &ar, unsigned version)
Definition: CPUCore.cc:4357
byte readMem(word address, EmuTime::param time)
This reads a byte from the currently selected device.
bool operator()(byte f) const
Definition: CPUCore.cc:261
void setBC(unsigned x)
Definition: CPURegs.hh:94
void setIFF2(bool x)
Definition: CPURegs.hh:110
unsigned getDE2() const
Definition: CPURegs.hh:54
void setAF2(unsigned x)
Definition: CPURegs.hh:97
byte getE() const
Definition: CPURegs.hh:28
void setHL(unsigned x)
Definition: CPURegs.hh:96
static void setContinue(bool x)
void setIXh(byte x)
Definition: CPURegs.hh:84
byte getIXl() const
Definition: CPURegs.hh:40
void setCurrentPopRet()
Definition: CPURegs.hh:152
void serialize(Archive &ar, T &t, unsigned version)
void raiseNMI()
Raises the non-maskable interrupt count.
Definition: CPUCore.cc:472
byte getI() const
Definition: CPURegs.hh:62
void setCurrentCall()
Definition: CPURegs.hh:148
static bool isMainThread()
Returns true when called from the main thread.
Definition: Thread.cc:19
unsigned getDE() const
Definition: CPURegs.hh:50
void invalidateMemCache(unsigned start, unsigned size)
Definition: CPUCore.cc:348
void setSP(unsigned x)
Definition: CPURegs.hh:104
byte readIRQVector()
CPU uses this method to read &#39;extra&#39; data from the databus used in interrupt routines.
bool getIFF2() const
Definition: CPURegs.hh:65
unsigned getBC2() const
Definition: CPURegs.hh:53
#define UNREACHABLE
Definition: unreachable.hh:35