10 , panasonicMemory(getMotherBoard().getPanasonicMemory())
39 const byte* rData = data;
47template<
typename Archive>
50 ar.template serializeBase<MSXMemoryMapperBase>(*
this);
#define REGISTER_MSXDEVICE(CLASS, NAME)
byte * getWriteCacheLine(size_t addr)
Ram & getUncheckedRam()
Give access to the unchecked Ram.
void write(size_t addr, byte value)
byte * getRWCacheLines(size_t addr, size_t size)
void fillDeviceRWCache(unsigned start, unsigned size, byte *rwData)
Calls MSXCPUInterface::fillXXCache() for the specific (part of) the slot that this device is located ...
static std::array< byte, 0x10000 > unmappedWrite
void invalidateDeviceRWCache()
Calls MSXCPUInterface::invalidateXXCache() for the specific (part of) the slot that this device is lo...
unsigned calcAddress(word address) const
Converts a Z80 address to a RAM address.
void writeIOImpl(word port, byte value, EmuTime::param time)
unsigned segmentOffset(byte page) const
void registerRam(Ram &ram)
Pass reference of the actual Ram block for use in DRAM mode and RAM access via the ROM mapper.
bool isWritable(unsigned address) const
void serialize(Archive &ar, unsigned version)
void writeMem(word address, byte value, EmuTime::param time) override
Write a given byte to a given location at a certain time to this device.
void writeIO(word port, byte value, EmuTime::param time) override
Write a byte to a given IO port at a certain time to this device.
byte * getWriteCacheLine(word start) override
Test that the memory in the interval [start, start + CacheLine::SIZE) is cacheable for writing.
PanasonicRam(const DeviceConfig &config)
This file implemented 3 utility functions:
uint16_t word
16 bit unsigned integer
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)