openMSX
CPUCore.cc
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1 // MEMORY EMULATION
2 // ----------------
3 //
4 // Memory access emulation is a very important part of the CPU emulation.
5 // Because they happen so frequently they really need to be executed as fast as
6 // possible otherwise they will completely bring down the speed of the CPU
7 // emulation.
8 //
9 // A very fast way to emulate memory accesses is by simply reading/writing to a
10 // 64kb array (for a 16-bit address space). Unfortunately this doesn't allow
11 // for memory mapped IO (MMIO). These are memory regions where read/writes
12 // trigger side effects, so where we need to execute device-specific code on
13 // read or writes. An alternative that does work with MMIO is for every access
14 // execute a virtual method call, (this is the approach taken by most current
15 // MSX emulators). Unfortunately this is also a lot slower.
16 //
17 // It is possible to combine the speed of array accesses with the flexibility
18 // of virtual methods. In openMSX it's implemented as follows: the 64kb address
19 // space is divided in 256 regions of 256 bytes (called cacheLines in the code
20 // below). For each such region we store a pointer, if this pointer is nullptr
21 // then we have to use the slow way (=virtual method call). If it is not nullptr,
22 // the pointer points to a block of memory that can be directly accessed. In
23 // some contexts accesses via the pointer are known as backdoor accesses while
24 // the accesses directly to the device are known as frontdoor accesses.
25 //
26 // We keep different pointers for read and write accesses. This allows to also
27 // implement ROMs efficiently: read is handled as regular RAM, but writes end
28 // up in some dummy memory region. This region is called 'unmappedWrite' in the
29 // code. There is also a special region 'unmappedRead', this region is filled
30 // with 0xFF and can be used to model (parts of) a device that don't react to
31 // reads (so reads return 0xFF).
32 //
33 // Because of bankswitching (the MSX slot select mechanism, but also e.g.
34 // MegaROM backswitching) the memory map as seen by the Z80 is not static. This
35 // means that the cacheLine pointers also need to change during runtime. To
36 // solve this we made the bankswitch code also responsible for invalidating the
37 // cacheLines of the switched region. These pointers are filled-in again in a
38 // lazy way: the first read or write to a cache line will first get this
39 // pointer (see getReadCacheLine() and getWriteCacheLine() in the code below),
40 // from then on this pointer is used for all further accesses to this region,
41 // until the cache is invalidated again.
42 //
43 //
44 // INSTRUCTION EMULATION
45 // ---------------------
46 //
47 // UPDATE: the 'threaded interpreter model' is not enabled by default
48 // main reason is the huge memory requirement while compiling
49 // and that it doesn't work on non-gcc compilers
50 //
51 // The current implementation is based on a 'threaded interpreter model'. In
52 // the text below I'll call the older implementation the 'traditional
53 // interpreter model'. From a very high level these two models look like this:
54 //
55 // Traditional model:
56 // while (!needExit()) {
57 // byte opcode = fetch(PC++);
58 // switch (opcode) {
59 // case 0x00: nop(); break;
60 // case 0x01: ld_bc_nn(); break;
61 // ...
62 // }
63 // }
64 //
65 // Threaded model:
66 // byte opcode = fetch(PC++); //
67 // goto *(table[opcode]); // fetch-and-dispatch
68 // // note: the goto * syntax is a gcc extension called computed-gotos
69 //
70 // op00: nop(); if (!needExit()) [fetch-and-dispatch];
71 // op01: ld_bc_nn(); if (!needExit()) [fetch-and-dispatch];
72 // ...
73 //
74 // In the first model there is a central place in the code that fetches (the
75 // first byte of) the instruction and based on this byte jumps to the
76 // appropriate routine. In the second model, this fetch-and-dispatch logic is
77 // duplicated at the end of each instruction.
78 //
79 // Typically the 'dispatch' part in above paragraph is implemented (either by
80 // the compiler or manually using computed goto's) via a jump table. Thus on
81 // assembler level via an indirect jump. For the host CPU it's hard to predict
82 // the destination address of such an indirect jump, certainly if there's only
83 // one such jump for all dispatching (the traditional model). If each
84 // instruction has its own indirect jump instruction (the threaded model), it
85 // becomes a bit easier, because often one particular z80 instructions is
86 // followed by a specific other z80 instruction (or one from a small subset).
87 // For example a z80 'cp' instruction is most likely followed by a 'conditional
88 // jump' z80 instruction. Modern CPUs are quite sensitive to
89 // branch-(mis)predictions, so the above optimization helps quite a lot. I
90 // measured a speedup of more than 10%!
91 //
92 // There is another advantage to the threaded model. Because also the
93 // needExit() test is duplicated for each instruction, it becomes possible to
94 // tweak it for individual instructions. But first let me explain this
95 // exit-test in more detail.
96 //
97 // These are the main reasons why the emulator should stop emulating CPU
98 // instructions:
99 // 1) When other devices than the CPU must be emulated (e.g. video frame
100 // rendering). In openMSX this is handled by the Scheduler class and
101 // actually we don't exit the CPU loop (anymore) for this. Instead we
102 // simply execute the device code as a subroutine. Each time right before
103 // we access an IO port or do a frontdoor memory access, there is a check
104 // whether we should emulate device code (search for schedule() in the code
105 // below).
106 // 2) To keep the inner CPU loop as fast as possible we don't check for IRQ,
107 // NMI or HALT status in this loop. Instead this condition is checked only
108 // once at the beginning outside of the loop (if there wasn't a pending IRQ
109 // on the first instruction there also won't be one on the second
110 // instruction, if all we did was emulating cpu instructions). Now when one
111 // of these conditions changes, we must exit the inner loop and re-evaluate
112 // them. For example after an EI instruction we must check the IRQ status
113 // again.
114 // 3) Various reasons like:
115 // * Z80/R800 switch
116 // * executing a Tcl command (could be a cpu-register debug read)
117 // * exit the emulator
118 // 4) 'once-in-a-while': To avoid threading problems and race conditions,
119 // several threads in openMSX only 'schedule' work that will later be
120 // executed by the main emulation thread. The main thread checks for such
121 // task outside of the cpu emulation loop. So once-in-a-while we need to
122 // exit the loop. The exact timing doesn't matter here because anyway the
123 // relative timing between threads is undefined.
124 // So for 1) we don't need to do anything (we don't actually exit). For 2) and
125 // 3) we need to exit the loop as soon as possible (right after the current
126 // instruction is finished). For 4) it's OK to exit 'eventually' (a few hundred
127 // z80 instructions late is still OK).
128 //
129 // Condition 2) is implemented with the 'slowInstructions' mechanism. Condition
130 // 3) via exitCPULoopSync() (may only get called by the main emulation thread)
131 // and condition 4) is implemented via exitCPULoopAsync() (can be called from
132 // any thread).
133 //
134 // Now back to the exit-test optimization: in the threaded model each
135 // instruction ends with:
136 //
137 // if (needExit()) return
138 // byte opcode = fetch(PC++);
139 // goto *(table[opcode]);
140 //
141 // And if we look in more detail at fetch():
142 //
143 // if (canDoBackdoor(addr)) {
144 // doBackdoorAccess(addr);
145 // } else {
146 // doFrontdoorAccess(addr);
147 // }
148 //
149 // So there are in fact two checks per instruction. This can be reduced to only
150 // one check with the following trick:
151 //
152 // !!!WRONG!!!
153 // In the past we optimized this to only check canDoBackdoor() (and make sure
154 // canDoBackdoor() returned false when needExit() would return true). This
155 // worked rather well, except for one case: when we exit the CPU loop we also
156 // check for pending Syncronization points. It is possible such a SyncPoint
157 // raises the IRQ line. So it is important to check for exit after every
158 // instruction, otherwise we would enter the IRQ routine a couple of
159 // instructions too late.
160 
161 #include "CPUCore.hh"
162 #include "MSXCPUInterface.hh"
163 #include "Scheduler.hh"
164 #include "MSXMotherBoard.hh"
165 #include "CliComm.hh"
166 #include "TclCallback.hh"
167 #include "Dasm.hh"
168 #include "Z80.hh"
169 #include "R800.hh"
170 #include "Thread.hh"
171 #include "endian.hh"
172 #include "likely.hh"
173 #include "inline.hh"
174 #include "unreachable.hh"
175 #include "xrange.hh"
176 #include <iostream>
177 #include <type_traits>
178 #include <cassert>
179 #include <cstring>
180 
181 
182 //
183 // #define USE_COMPUTED_GOTO
184 //
185 // Computed goto's are not enabled by default:
186 // - Computed goto's are a gcc extension, it's not part of the official c++
187 // standard. So this will only work if you use gcc as your compiler (it
188 // won't work with visual c++ for example)
189 // - This is only beneficial on CPUs with branch prediction for indirect jumps
190 // and a reasonable amount of cache. For example it is very benefical for a
191 // intel core2 cpu (10% faster), but not for a ARM920 (a few percent slower)
192 // - Compiling src/cpu/CPUCore.cc with computed goto's enabled is very demanding
193 // on the compiler. On older gcc versions it requires up to 1.5GB of memory.
194 // But even on more recent gcc versions it still requires around 700MB.
195 //
196 // Probably the easiest way to enable this, is to pass the -DUSE_COMPUTED_GOTO
197 // flag to the compiler. This is for example done in the super-opt flavour.
198 // See build/flavour-super-opt.mk
199 
200 
201 using std::string;
202 
203 namespace openmsx {
204 
205 enum Reg8 : int { A, F, B, C, D, E, H, L, IXH, IXL, IYH, IYL, REG_I, REG_R, DUMMY };
206 enum Reg16 : int { AF, BC, DE, HL, IX, IY, SP };
207 
208 // flag positions
209 constexpr byte S_FLAG = 0x80;
210 constexpr byte Z_FLAG = 0x40;
211 constexpr byte Y_FLAG = 0x20;
212 constexpr byte H_FLAG = 0x10;
213 constexpr byte X_FLAG = 0x08;
214 constexpr byte V_FLAG = 0x04;
215 constexpr byte P_FLAG = V_FLAG;
216 constexpr byte N_FLAG = 0x02;
217 constexpr byte C_FLAG = 0x01;
218 
219 // flag-register lookup tables
220 struct Table {
221  byte ZS [256];
222  byte ZSXY [256];
223  byte ZSP [256];
224  byte ZSPXY[256];
225  byte ZSPH [256];
226 };
227 
228 constexpr byte ZS0 = Z_FLAG;
229 constexpr byte ZSXY0 = Z_FLAG;
230 constexpr byte ZSP0 = Z_FLAG | V_FLAG;
231 constexpr byte ZSPXY0 = Z_FLAG | V_FLAG;
232 constexpr byte ZS255 = S_FLAG;
233 constexpr byte ZSXY255 = S_FLAG | X_FLAG | Y_FLAG;
234 
235 static constexpr Table initTables()
236 {
237  Table table = {};
238 
239  for (auto i : xrange(256)) {
240  byte zFlag = (i == 0) ? Z_FLAG : 0;
241  byte sFlag = i & S_FLAG;
242  byte xFlag = i & X_FLAG;
243  byte yFlag = i & Y_FLAG;
244  byte vFlag = V_FLAG;
245  for (int v = 128; v != 0; v >>= 1) {
246  if (i & v) vFlag ^= V_FLAG;
247  }
248  table.ZS [i] = zFlag | sFlag;
249  table.ZSXY [i] = zFlag | sFlag | xFlag | yFlag;
250  table.ZSP [i] = zFlag | sFlag | vFlag;
251  table.ZSPXY[i] = zFlag | sFlag | xFlag | yFlag | vFlag;
252  table.ZSPH [i] = zFlag | sFlag | vFlag | H_FLAG;
253  }
254  assert(table.ZS [ 0] == ZS0);
255  assert(table.ZSXY [ 0] == ZSXY0);
256  assert(table.ZSP [ 0] == ZSP0);
257  assert(table.ZSPXY[ 0] == ZSPXY0);
258  assert(table.ZS [255] == ZS255);
259  assert(table.ZSXY [255] == ZSXY255);
260 
261  return table;
262 }
263 
264 constexpr Table table = initTables();
265 
266 // Global variable, because it should be shared between Z80 and R800.
267 // It must not be shared between the CPUs of different MSX machines, but
268 // the (logical) lifetime of this variable cannot overlap between execution
269 // of two MSX machines.
270 static word start_pc;
271 
272 // conditions
273 struct CondC { bool operator()(byte f) const { return (f & C_FLAG) != 0; } };
274 struct CondNC { bool operator()(byte f) const { return !(f & C_FLAG); } };
275 struct CondZ { bool operator()(byte f) const { return (f & Z_FLAG) != 0; } };
276 struct CondNZ { bool operator()(byte f) const { return !(f & Z_FLAG); } };
277 struct CondM { bool operator()(byte f) const { return (f & S_FLAG) != 0; } };
278 struct CondP { bool operator()(byte f) const { return !(f & S_FLAG); } };
279 struct CondPE { bool operator()(byte f) const { return (f & V_FLAG) != 0; } };
280 struct CondPO { bool operator()(byte f) const { return !(f & V_FLAG); } };
281 struct CondTrue { bool operator()(byte /*f*/) const { return true; } };
282 
283 template<typename T> CPUCore<T>::CPUCore(
284  MSXMotherBoard& motherboard_, const string& name,
285  const BooleanSetting& traceSetting_,
286  TclCallback& diHaltCallback_, EmuTime::param time)
287  : CPURegs(T::IS_R800)
288  , T(time, motherboard_.getScheduler())
289  , motherboard(motherboard_)
290  , scheduler(motherboard.getScheduler())
291  , interface(nullptr)
292  , traceSetting(traceSetting_)
293  , diHaltCallback(diHaltCallback_)
294  , IRQStatus(motherboard.getDebugger(), name + ".pendingIRQ",
295  "Non-zero if there are pending IRQs (thus CPU would enter "
296  "interrupt routine in EI mode).",
297  0)
298  , IRQAccept(motherboard.getDebugger(), name + ".acceptIRQ",
299  "This probe is only useful to set a breakpoint on (the value "
300  "return by read is meaningless). The breakpoint gets triggered "
301  "right after the CPU accepted an IRQ.")
302  , freqLocked(
303  motherboard.getCommandController(), tmpStrCat(name, "_freq_locked"),
304  "real (locked) or custom (unlocked) CPU frequency",
305  true)
306  , freqValue(
307  motherboard.getCommandController(), tmpStrCat(name, "_freq"),
308  "custom CPU frequency (only valid when unlocked)",
309  T::CLOCK_FREQ, 1000000, 1000000000)
310  , freq(T::CLOCK_FREQ)
311  , NMIStatus(0)
312  , nmiEdge(false)
313  , exitLoop(false)
314  , tracingEnabled(traceSetting.getBoolean())
315  , isTurboR(motherboard.isTurboR())
316 {
317  static_assert(!std::is_polymorphic_v<CPUCore<T>>,
318  "keep CPUCore non-virtual to keep PC at offset 0");
319  doSetFreq();
320  doReset(time);
321 }
322 
323 template<typename T> void CPUCore<T>::warp(EmuTime::param time)
324 {
325  assert(T::getTimeFast() <= time);
326  T::setTime(time);
327 }
328 
329 template<typename T> EmuTime::param CPUCore<T>::getCurrentTime() const
330 {
331  return T::getTime();
332 }
333 
334 template<typename T> void CPUCore<T>::doReset(EmuTime::param time)
335 {
336  // AF and SP are 0xFFFF
337  // PC, R, IFF1, IFF2, HALT and IM are 0x0
338  // all others are random
339  setAF(0xFFFF);
340  setBC(0xFFFF);
341  setDE(0xFFFF);
342  setHL(0xFFFF);
343  setIX(0xFFFF);
344  setIY(0xFFFF);
345  setPC(0x0000);
346  setSP(0xFFFF);
347  setAF2(0xFFFF);
348  setBC2(0xFFFF);
349  setDE2(0xFFFF);
350  setHL2(0xFFFF);
351  setIFF1(false);
352  setIFF2(false);
353  setHALT(false);
354  setExtHALT(false);
355  setIM(0);
356  setI(0x00);
357  setR(0x00);
358  T::setMemPtr(0xFFFF);
359  clearPrevious();
360 
361  // We expect this assert to be valid
362  // assert(T::getTimeFast() <= time); // time shouldn't go backwards
363  // But it's disabled for the following reason:
364  // 'motion' (IRC nickname) managed to create a replay file that
365  // contains a reset command that falls in the middle of a Z80
366  // instruction. Replayed commands go via the Scheduler, and are
367  // (typically) executed right after a complete CPU instruction. So
368  // the CPU is (slightly) ahead in time of the about to be executed
369  // reset command.
370  // Normally this situation should never occur: console commands,
371  // hotkeys, commands over clicomm, ... are all handled via the global
372  // event mechanism. Such global events are scheduled between CPU
373  // instructions, so also in a replay they should fall between CPU
374  // instructions.
375  // However if for some reason the timing of the emulation changed
376  // (improved emulation accuracy or a bug so that emulation isn't
377  // deterministic or the replay file was edited, ...), then the above
378  // reasoning no longer holds and the assert can trigger.
379  // We need to be robust against loading older replays (when emulation
380  // timing has changed). So in that respect disabling the assert is
381  // good. Though in the example above (motion's replay) it's not clear
382  // whether the assert is really triggered by mixing an old replay
383  // with a newer openMSX version. In any case so far we haven't been
384  // able to reproduce this assert by recording and replaying using a
385  // single openMSX version.
386  T::setTime(time);
387 
388  assert(NMIStatus == 0); // other devices must reset their NMI source
389  assert(IRQStatus == 0); // other devices must reset their IRQ source
390 }
391 
392 // I believe the following two methods are thread safe even without any
393 // locking. The worst that can happen is that we occasionally needlessly
394 // exit the CPU loop, but that's harmless
395 // TODO thread issues are always tricky, can someone confirm this really
396 // is thread safe
397 template<typename T> void CPUCore<T>::exitCPULoopAsync()
398 {
399  // can get called from non-main threads
400  exitLoop = true;
401 }
402 template<typename T> void CPUCore<T>::exitCPULoopSync()
403 {
404  assert(Thread::isMainThread());
405  exitLoop = true;
406  T::disableLimit();
407 }
408 template<typename T> inline bool CPUCore<T>::needExitCPULoop()
409 {
410  // always executed in main thread
411  if (unlikely(exitLoop)) {
412  // Note: The test-and-set is _not_ atomic! But that's fine.
413  // An atomic implementation is trivial (see below), but
414  // this version (at least on x86) avoids the more expensive
415  // instructions on the likely path.
416  exitLoop = false;
417  return true;
418  }
419  return false;
420 
421  // Alternative implementation:
422  // atomically set to false and return the old value
423  //return exitLoop.exchange(false);
424 }
425 
426 template<typename T> void CPUCore<T>::setSlowInstructions()
427 {
428  slowInstructions = 2;
429  T::disableLimit();
430 }
431 
432 template<typename T> void CPUCore<T>::raiseIRQ()
433 {
434  assert(IRQStatus >= 0);
435  if (IRQStatus == 0) {
436  setSlowInstructions();
437  }
438  IRQStatus = IRQStatus + 1;
439 }
440 
441 template<typename T> void CPUCore<T>::lowerIRQ()
442 {
443  IRQStatus = IRQStatus - 1;
444  assert(IRQStatus >= 0);
445 }
446 
447 template<typename T> void CPUCore<T>::raiseNMI()
448 {
449  assert(NMIStatus >= 0);
450  if (NMIStatus == 0) {
451  nmiEdge = true;
452  setSlowInstructions();
453  }
454  NMIStatus++;
455 }
456 
457 template<typename T> void CPUCore<T>::lowerNMI()
458 {
459  NMIStatus--;
460  assert(NMIStatus >= 0);
461 }
462 
463 template<typename T> bool CPUCore<T>::isM1Cycle(unsigned address) const
464 {
465  // This method should only be called from within a MSXDevice::readMem()
466  // method. It can be used to check whether the current read action has
467  // the M1 pin active. The 'address' parameter that is give to readMem()
468  // should be passed (unchanged) to this method.
469  //
470  // This simple implementation works because the rest of the CPUCore
471  // code is careful to only update the PC register on M1 cycles. In
472  // practice that means that the PC is (only) updated at the very end of
473  // every instruction, even if is a multi-byte instruction. Or for
474  // prefix-instructions the PC is also updated after the prefix is
475  // fetched (because such instructions activate M1 twice).
476  return address == getPC();
477 }
478 
479 template<typename T> void CPUCore<T>::wait(EmuTime::param time)
480 {
481  assert(time >= getCurrentTime());
482  scheduler.schedule(time);
483  T::advanceTime(time);
484 }
485 
486 template<typename T> EmuTime CPUCore<T>::waitCycles(EmuTime::param time, unsigned cycles)
487 {
488  T::add(cycles);
489  EmuTime time2 = T::calcTime(time, cycles);
490  // note: time2 is not necessarily equal to T::getTime() because of the
491  // way how WRITE_PORT() is implemented.
492  scheduler.schedule(time2);
493  return time2;
494 }
495 
496 template<typename T> void CPUCore<T>::setNextSyncPoint(EmuTime::param time)
497 {
498  T::setLimit(time);
499 }
500 
501 
502 static constexpr char toHex(byte x)
503 {
504  return (x < 10) ? (x + '0') : (x - 10 + 'A');
505 }
506 static constexpr void toHex(byte x, char* buf)
507 {
508  buf[0] = toHex(x / 16);
509  buf[1] = toHex(x & 15);
510 }
511 
512 template<typename T> void CPUCore<T>::disasmCommand(
513  Interpreter& interp, span<const TclObject> tokens, TclObject& result) const
514 {
515  word address = (tokens.size() < 3) ? getPC() : tokens[2].getInt(interp);
516  byte outBuf[4];
517  std::string dasmOutput;
518  unsigned len = dasm(*interface, address, outBuf, dasmOutput,
519  T::getTimeFast());
520  result.addListElement(dasmOutput);
521  char tmp[3]; tmp[2] = 0;
522  for (auto i : xrange(len)) {
523  toHex(outBuf[i], tmp);
524  result.addListElement(tmp);
525  }
526 }
527 
528 template<typename T> void CPUCore<T>::update(const Setting& setting) noexcept
529 {
530  if (&setting == &freqLocked) {
531  doSetFreq();
532  } else if (&setting == &freqValue) {
533  doSetFreq();
534  } else if (&setting == &traceSetting) {
535  tracingEnabled = traceSetting.getBoolean();
536  }
537 }
538 
539 template<typename T> void CPUCore<T>::setFreq(unsigned freq_)
540 {
541  freq = freq_;
542  doSetFreq();
543 }
544 
545 template<typename T> void CPUCore<T>::doSetFreq()
546 {
547  if (freqLocked.getBoolean()) {
548  // locked, use value set via setFreq()
549  T::setFreq(freq);
550  } else {
551  // unlocked, use value set by user
552  T::setFreq(freqValue.getInt());
553  }
554 }
555 
556 
557 template<typename T> inline byte CPUCore<T>::READ_PORT(unsigned port, unsigned cc)
558 {
559  EmuTime time = T::getTimeFast(cc);
560  scheduler.schedule(time);
561  byte result = interface->readIO(port, time);
562  // note: no forced page-break after IO
563  return result;
564 }
565 
566 template<typename T> inline void CPUCore<T>::WRITE_PORT(unsigned port, byte value, unsigned cc)
567 {
568  EmuTime time = T::getTimeFast(cc);
569  scheduler.schedule(time);
570  interface->writeIO(port, value, time);
571  // note: no forced page-break after IO
572 }
573 
574 template<typename T> template<bool PRE_PB, bool POST_PB>
575 NEVER_INLINE byte CPUCore<T>::RDMEMslow(unsigned address, unsigned cc)
576 {
577  interface->tick(CacheLineCounters::NonCachedRead);
578  // not cached
579  unsigned high = address >> CacheLine::BITS;
580  if (readCacheLine[high] == nullptr) {
581  // try to cache now (not a valid entry, and not yet tried)
582  unsigned addrBase = address & CacheLine::HIGH;
583  if (const byte* line = interface->getReadCacheLine(addrBase)) {
584  // cached ok
585  T::template PRE_MEM<PRE_PB, POST_PB>(address);
586  T::template POST_MEM< POST_PB>(address);
587  readCacheLine[high] = line - addrBase;
588  return readCacheLine[high][address];
589  }
590  }
591  // uncacheable
592  readCacheLine[high] = reinterpret_cast<const byte*>(1);
593  T::template PRE_MEM<PRE_PB, POST_PB>(address);
594  EmuTime time = T::getTimeFast(cc);
595  scheduler.schedule(time);
596  byte result = interface->readMem(address, time);
597  T::template POST_MEM<POST_PB>(address);
598  return result;
599 }
600 template<typename T> template<bool PRE_PB, bool POST_PB>
601 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl2(unsigned address, unsigned cc)
602 {
603  const byte* line = readCacheLine[address >> CacheLine::BITS];
604  if (likely(uintptr_t(line) > 1)) {
605  // cached, fast path
606  T::template PRE_MEM<PRE_PB, POST_PB>(address);
607  T::template POST_MEM< POST_PB>(address);
608  return line[address];
609  } else {
610  return RDMEMslow<PRE_PB, POST_PB>(address, cc); // not inlined
611  }
612 }
613 template<typename T> template<bool PRE_PB, bool POST_PB>
614 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl(unsigned address, unsigned cc)
615 {
616  constexpr bool PRE = T::template Normalize<PRE_PB >::value;
617  constexpr bool POST = T::template Normalize<POST_PB>::value;
618  return RDMEM_impl2<PRE, POST>(address, cc);
619 }
620 template<typename T> template<unsigned PC_OFFSET> ALWAYS_INLINE byte CPUCore<T>::RDMEM_OPCODE(unsigned cc)
621 {
622  // Real Z80 would update the PC register now. In this implementation
623  // we've chosen to instead update PC only once at the end of the
624  // instruction. (Of course we made sure this difference is not
625  // noticeable by the program).
626  //
627  // See the comments in isM1Cycle() for the motivation for this
628  // deviation. Apart from that functional aspect it also turns out to be
629  // faster to only update PC once per instruction instead of after each
630  // fetch.
631  unsigned address = (getPC() + PC_OFFSET) & 0xFFFF;
632  return RDMEM_impl<false, false>(address, cc);
633 }
634 template<typename T> ALWAYS_INLINE byte CPUCore<T>::RDMEM(unsigned address, unsigned cc)
635 {
636  return RDMEM_impl<true, true>(address, cc);
637 }
638 
639 template<typename T> template<bool PRE_PB, bool POST_PB>
640 NEVER_INLINE unsigned CPUCore<T>::RD_WORD_slow(unsigned address, unsigned cc)
641 {
642  unsigned res = RDMEM_impl<PRE_PB, false>(address, cc);
643  res += RDMEM_impl<false, POST_PB>((address + 1) & 0xFFFF, cc + T::CC_RDMEM) << 8;
644  return res;
645 }
646 template<typename T> template<bool PRE_PB, bool POST_PB>
647 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl2(unsigned address, unsigned cc)
648 {
649  const byte* line = readCacheLine[address >> CacheLine::BITS];
650  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && (uintptr_t(line) > 1))) {
651  // fast path: cached and two bytes in same cache line
652  T::template PRE_WORD<PRE_PB, POST_PB>(address);
653  T::template POST_WORD< POST_PB>(address);
654  return Endian::read_UA_L16(&line[address]);
655  } else {
656  // slow path, not inline
657  return RD_WORD_slow<PRE_PB, POST_PB>(address, cc);
658  }
659 }
660 template<typename T> template<bool PRE_PB, bool POST_PB>
661 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl(unsigned address, unsigned cc)
662 {
663  constexpr bool PRE = T::template Normalize<PRE_PB >::value;
664  constexpr bool POST = T::template Normalize<POST_PB>::value;
665  return RD_WORD_impl2<PRE, POST>(address, cc);
666 }
667 template<typename T> template<unsigned PC_OFFSET> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_PC(unsigned cc)
668 {
669  unsigned addr = (getPC() + PC_OFFSET) & 0xFFFF;
670  return RD_WORD_impl<false, false>(addr, cc);
671 }
672 template<typename T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD(
673  unsigned address, unsigned cc)
674 {
675  return RD_WORD_impl<true, true>(address, cc);
676 }
677 
678 template<typename T> template<bool PRE_PB, bool POST_PB>
679 NEVER_INLINE void CPUCore<T>::WRMEMslow(unsigned address, byte value, unsigned cc)
680 {
681  interface->tick(CacheLineCounters::NonCachedWrite);
682  // not cached
683  unsigned high = address >> CacheLine::BITS;
684  if (writeCacheLine[high] == nullptr) {
685  // try to cache now
686  unsigned addrBase = address & CacheLine::HIGH;
687  if (byte* line = interface->getWriteCacheLine(addrBase)) {
688  // cached ok
689  T::template PRE_MEM<PRE_PB, POST_PB>(address);
690  T::template POST_MEM< POST_PB>(address);
691  writeCacheLine[high] = line - addrBase;
692  writeCacheLine[high][address] = value;
693  return;
694  }
695  }
696  // uncacheable
697  writeCacheLine[high] = reinterpret_cast<byte*>(1);
698  T::template PRE_MEM<PRE_PB, POST_PB>(address);
699  EmuTime time = T::getTimeFast(cc);
700  scheduler.schedule(time);
701  interface->writeMem(address, value, time);
702  T::template POST_MEM<POST_PB>(address);
703 }
704 template<typename T> template<bool PRE_PB, bool POST_PB>
706  unsigned address, byte value, unsigned cc)
707 {
708  byte* line = writeCacheLine[address >> CacheLine::BITS];
709  if (likely(uintptr_t(line) > 1)) {
710  // cached, fast path
711  T::template PRE_MEM<PRE_PB, POST_PB>(address);
712  T::template POST_MEM< POST_PB>(address);
713  line[address] = value;
714  } else {
715  WRMEMslow<PRE_PB, POST_PB>(address, value, cc); // not inlined
716  }
717 }
718 template<typename T> template<bool PRE_PB, bool POST_PB>
720  unsigned address, byte value, unsigned cc)
721 {
722  constexpr bool PRE = T::template Normalize<PRE_PB >::value;
723  constexpr bool POST = T::template Normalize<POST_PB>::value;
724  WRMEM_impl2<PRE, POST>(address, value, cc);
725 }
726 template<typename T> ALWAYS_INLINE void CPUCore<T>::WRMEM(
727  unsigned address, byte value, unsigned cc)
728 {
729  WRMEM_impl<true, true>(address, value, cc);
730 }
731 
732 template<typename T> NEVER_INLINE void CPUCore<T>::WR_WORD_slow(
733  unsigned address, unsigned value, unsigned cc)
734 {
735  WRMEM_impl<true, false>( address, value & 255, cc);
736  WRMEM_impl<false, true>((address + 1) & 0xFFFF, value >> 8, cc + T::CC_WRMEM);
737 }
738 template<typename T> ALWAYS_INLINE void CPUCore<T>::WR_WORD(
739  unsigned address, unsigned value, unsigned cc)
740 {
741  byte* line = writeCacheLine[address >> CacheLine::BITS];
742  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && (uintptr_t(line) > 1))) {
743  // fast path: cached and two bytes in same cache line
744  T::template PRE_WORD<true, true>(address);
745  T::template POST_WORD< true>(address);
746  Endian::write_UA_L16(&line[address], value);
747  } else {
748  // slow path, not inline
749  WR_WORD_slow(address, value, cc);
750  }
751 }
752 
753 // same as WR_WORD, but writes high byte first
754 template<typename T> template<bool PRE_PB, bool POST_PB>
756  unsigned address, unsigned value, unsigned cc)
757 {
758  WRMEM_impl<PRE_PB, false>((address + 1) & 0xFFFF, value >> 8, cc);
759  WRMEM_impl<false, POST_PB>( address, value & 255, cc + T::CC_WRMEM);
760 }
761 template<typename T> template<bool PRE_PB, bool POST_PB>
763  unsigned address, unsigned value, unsigned cc)
764 {
765  byte* line = writeCacheLine[address >> CacheLine::BITS];
766  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && (uintptr_t(line) > 1))) {
767  // fast path: cached and two bytes in same cache line
768  T::template PRE_WORD<PRE_PB, POST_PB>(address);
769  T::template POST_WORD< POST_PB>(address);
770  Endian::write_UA_L16(&line[address], value);
771  } else {
772  // slow path, not inline
773  WR_WORD_rev_slow<PRE_PB, POST_PB>(address, value, cc);
774  }
775 }
776 template<typename T> template<bool PRE_PB, bool POST_PB>
778  unsigned address, unsigned value, unsigned cc)
779 {
780  constexpr bool PRE = T::template Normalize<PRE_PB >::value;
781  constexpr bool POST = T::template Normalize<POST_PB>::value;
782  WR_WORD_rev2<PRE, POST>(address, value, cc);
783 }
784 
785 
786 // NMI interrupt
787 template<typename T> inline void CPUCore<T>::nmi()
788 {
789  incR(1);
790  setHALT(false);
791  setIFF1(false);
792  PUSH<T::EE_NMI_1>(getPC());
793  setPC(0x0066);
794  T::add(T::CC_NMI);
795 }
796 
797 // IM0 interrupt
798 template<typename T> inline void CPUCore<T>::irq0()
799 {
800  // TODO current implementation only works for 1-byte instructions
801  // ok for MSX
802  assert(interface->readIRQVector() == 0xFF);
803  incR(1);
804  setHALT(false);
805  setIFF1(false);
806  setIFF2(false);
807  PUSH<T::EE_IRQ0_1>(getPC());
808  setPC(0x0038);
809  T::setMemPtr(getPC());
810  T::add(T::CC_IRQ0);
811 }
812 
813 // IM1 interrupt
814 template<typename T> inline void CPUCore<T>::irq1()
815 {
816  incR(1);
817  setHALT(false);
818  setIFF1(false);
819  setIFF2(false);
820  PUSH<T::EE_IRQ1_1>(getPC());
821  setPC(0x0038);
822  T::setMemPtr(getPC());
823  T::add(T::CC_IRQ1);
824 }
825 
826 // IM2 interrupt
827 template<typename T> inline void CPUCore<T>::irq2()
828 {
829  incR(1);
830  setHALT(false);
831  setIFF1(false);
832  setIFF2(false);
833  PUSH<T::EE_IRQ2_1>(getPC());
834  unsigned x = interface->readIRQVector() | (getI() << 8);
835  setPC(RD_WORD(x, T::CC_IRQ2_2));
836  T::setMemPtr(getPC());
837  T::add(T::CC_IRQ2);
838 }
839 
840 template<typename T>
841 void CPUCore<T>::executeInstructions()
842 {
843  checkNoCurrentFlags();
844 #ifdef USE_COMPUTED_GOTO
845  // Addresses of all main-opcode routines,
846  // Note that 40/49/53/5B/64/6D/7F is replaced by 00 (ld r,r == nop)
847  static void* opcodeTable[256] = {
848  &&op00, &&op01, &&op02, &&op03, &&op04, &&op05, &&op06, &&op07,
849  &&op08, &&op09, &&op0A, &&op0B, &&op0C, &&op0D, &&op0E, &&op0F,
850  &&op10, &&op11, &&op12, &&op13, &&op14, &&op15, &&op16, &&op17,
851  &&op18, &&op19, &&op1A, &&op1B, &&op1C, &&op1D, &&op1E, &&op1F,
852  &&op20, &&op21, &&op22, &&op23, &&op24, &&op25, &&op26, &&op27,
853  &&op28, &&op29, &&op2A, &&op2B, &&op2C, &&op2D, &&op2E, &&op2F,
854  &&op30, &&op31, &&op32, &&op33, &&op34, &&op35, &&op36, &&op37,
855  &&op38, &&op39, &&op3A, &&op3B, &&op3C, &&op3D, &&op3E, &&op3F,
856  &&op00, &&op41, &&op42, &&op43, &&op44, &&op45, &&op46, &&op47,
857  &&op48, &&op00, &&op4A, &&op4B, &&op4C, &&op4D, &&op4E, &&op4F,
858  &&op50, &&op51, &&op00, &&op53, &&op54, &&op55, &&op56, &&op57,
859  &&op58, &&op59, &&op5A, &&op00, &&op5C, &&op5D, &&op5E, &&op5F,
860  &&op60, &&op61, &&op62, &&op63, &&op00, &&op65, &&op66, &&op67,
861  &&op68, &&op69, &&op6A, &&op6B, &&op6C, &&op00, &&op6E, &&op6F,
862  &&op70, &&op71, &&op72, &&op73, &&op74, &&op75, &&op76, &&op77,
863  &&op78, &&op79, &&op7A, &&op7B, &&op7C, &&op7D, &&op7E, &&op00,
864  &&op80, &&op81, &&op82, &&op83, &&op84, &&op85, &&op86, &&op87,
865  &&op88, &&op89, &&op8A, &&op8B, &&op8C, &&op8D, &&op8E, &&op8F,
866  &&op90, &&op91, &&op92, &&op93, &&op94, &&op95, &&op96, &&op97,
867  &&op98, &&op99, &&op9A, &&op9B, &&op9C, &&op9D, &&op9E, &&op9F,
868  &&opA0, &&opA1, &&opA2, &&opA3, &&opA4, &&opA5, &&opA6, &&opA7,
869  &&opA8, &&opA9, &&opAA, &&opAB, &&opAC, &&opAD, &&opAE, &&opAF,
870  &&opB0, &&opB1, &&opB2, &&opB3, &&opB4, &&opB5, &&opB6, &&opB7,
871  &&opB8, &&opB9, &&opBA, &&opBB, &&opBC, &&opBD, &&opBE, &&opBF,
872  &&opC0, &&opC1, &&opC2, &&opC3, &&opC4, &&opC5, &&opC6, &&opC7,
873  &&opC8, &&opC9, &&opCA, &&opCB, &&opCC, &&opCD, &&opCE, &&opCF,
874  &&opD0, &&opD1, &&opD2, &&opD3, &&opD4, &&opD5, &&opD6, &&opD7,
875  &&opD8, &&opD9, &&opDA, &&opDB, &&opDC, &&opDD, &&opDE, &&opDF,
876  &&opE0, &&opE1, &&opE2, &&opE3, &&opE4, &&opE5, &&opE6, &&opE7,
877  &&opE8, &&opE9, &&opEA, &&opEB, &&opEC, &&opED, &&opEE, &&opEF,
878  &&opF0, &&opF1, &&opF2, &&opF3, &&opF4, &&opF5, &&opF6, &&opF7,
879  &&opF8, &&opF9, &&opFA, &&opFB, &&opFC, &&opFD, &&opFE, &&opFF,
880  };
881 
882 // Check T::limitReached(). If it's OK to continue,
883 // fetch and execute next instruction.
884 #define NEXT \
885  setPC(getPC() + ii.length); \
886  T::add(ii.cycles); \
887  T::R800Refresh(*this); \
888  if (likely(!T::limitReached())) { \
889  incR(1); \
890  unsigned address = getPC(); \
891  const byte* line = readCacheLine[address >> CacheLine::BITS]; \
892  if (likely(uintptr_t(line) > 1)) { \
893  T::template PRE_MEM<false, false>(address); \
894  T::template POST_MEM< false>(address); \
895  byte op = line[address]; \
896  goto *(opcodeTable[op]); \
897  } else { \
898  goto fetchSlow; \
899  } \
900  } \
901  return;
902 
903 // After some instructions we must always exit the CPU loop (ei, halt, retn)
904 #define NEXT_STOP \
905  setPC(getPC() + ii.length); \
906  T::add(ii.cycles); \
907  T::R800Refresh(*this); \
908  assert(T::limitReached()); \
909  return;
910 
911 #define NEXT_EI \
912  setPC(getPC() + ii.length); \
913  T::add(ii.cycles); \
914  /* !! NO T::R800Refresh(*this); !! */ \
915  assert(T::limitReached()); \
916  return;
917 
918 // Define a label (instead of case in a switch statement)
919 #define CASE(X) op##X:
920 
921 #else // USE_COMPUTED_GOTO
922 
923 #define NEXT \
924  setPC(getPC() + ii.length); \
925  T::add(ii.cycles); \
926  T::R800Refresh(*this); \
927  if (likely(!T::limitReached())) { \
928  goto start; \
929  } \
930  return;
931 
932 #define NEXT_STOP \
933  setPC(getPC() + ii.length); \
934  T::add(ii.cycles); \
935  T::R800Refresh(*this); \
936  assert(T::limitReached()); \
937  return;
938 
939 #define NEXT_EI \
940  setPC(getPC() + ii.length); \
941  T::add(ii.cycles); \
942  /* !! NO T::R800Refresh(*this); !! */ \
943  assert(T::limitReached()); \
944  return;
945 
946 #define CASE(X) case 0x##X:
947 
948 #endif // USE_COMPUTED_GOTO
949 
950 #ifndef USE_COMPUTED_GOTO
951 start:
952 #endif
953  unsigned ixy; // for dd_cb/fd_cb
954  byte opcodeMain = RDMEM_OPCODE<0>(T::CC_MAIN);
955  incR(1);
956 #ifdef USE_COMPUTED_GOTO
957  goto *(opcodeTable[opcodeMain]);
958 
959 fetchSlow: {
960  unsigned address = getPC();
961  byte opcodeSlow = RDMEMslow<false, false>(address, T::CC_MAIN);
962  goto *(opcodeTable[opcodeSlow]);
963 }
964 #endif
965 
966 #ifndef USE_COMPUTED_GOTO
967 switchopcode:
968  switch (opcodeMain) {
969 CASE(40) // ld b,b
970 CASE(49) // ld c,c
971 CASE(52) // ld d,d
972 CASE(5B) // ld e,e
973 CASE(64) // ld h,h
974 CASE(6D) // ld l,l
975 CASE(7F) // ld a,a
976 #endif
977 CASE(00) { II ii = nop(); NEXT; }
978 CASE(07) { II ii = rlca(); NEXT; }
979 CASE(0F) { II ii = rrca(); NEXT; }
980 CASE(17) { II ii = rla(); NEXT; }
981 CASE(1F) { II ii = rra(); NEXT; }
982 CASE(08) { II ii = ex_af_af(); NEXT; }
983 CASE(27) { II ii = daa(); NEXT; }
984 CASE(2F) { II ii = cpl(); NEXT; }
985 CASE(37) { II ii = scf(); NEXT; }
986 CASE(3F) { II ii = ccf(); NEXT; }
987 CASE(20) { II ii = jr(CondNZ()); NEXT; }
988 CASE(28) { II ii = jr(CondZ ()); NEXT; }
989 CASE(30) { II ii = jr(CondNC()); NEXT; }
990 CASE(38) { II ii = jr(CondC ()); NEXT; }
991 CASE(18) { II ii = jr(CondTrue()); NEXT; }
992 CASE(10) { II ii = djnz(); NEXT; }
993 CASE(32) { II ii = ld_xbyte_a(); NEXT; }
994 CASE(3A) { II ii = ld_a_xbyte(); NEXT; }
995 CASE(22) { II ii = ld_xword_SS<HL,0>(); NEXT; }
996 CASE(2A) { II ii = ld_SS_xword<HL,0>(); NEXT; }
997 CASE(02) { II ii = ld_SS_a<BC>(); NEXT; }
998 CASE(12) { II ii = ld_SS_a<DE>(); NEXT; }
999 CASE(1A) { II ii = ld_a_SS<DE>(); NEXT; }
1000 CASE(0A) { II ii = ld_a_SS<BC>(); NEXT; }
1001 CASE(03) { II ii = inc_SS<BC,0>(); NEXT; }
1002 CASE(13) { II ii = inc_SS<DE,0>(); NEXT; }
1003 CASE(23) { II ii = inc_SS<HL,0>(); NEXT; }
1004 CASE(33) { II ii = inc_SS<SP,0>(); NEXT; }
1005 CASE(0B) { II ii = dec_SS<BC,0>(); NEXT; }
1006 CASE(1B) { II ii = dec_SS<DE,0>(); NEXT; }
1007 CASE(2B) { II ii = dec_SS<HL,0>(); NEXT; }
1008 CASE(3B) { II ii = dec_SS<SP,0>(); NEXT; }
1009 CASE(09) { II ii = add_SS_TT<HL,BC,0>(); NEXT; }
1010 CASE(19) { II ii = add_SS_TT<HL,DE,0>(); NEXT; }
1011 CASE(29) { II ii = add_SS_SS<HL ,0>(); NEXT; }
1012 CASE(39) { II ii = add_SS_TT<HL,SP,0>(); NEXT; }
1013 CASE(01) { II ii = ld_SS_word<BC,0>(); NEXT; }
1014 CASE(11) { II ii = ld_SS_word<DE,0>(); NEXT; }
1015 CASE(21) { II ii = ld_SS_word<HL,0>(); NEXT; }
1016 CASE(31) { II ii = ld_SS_word<SP,0>(); NEXT; }
1017 CASE(04) { II ii = inc_R<B,0>(); NEXT; }
1018 CASE(0C) { II ii = inc_R<C,0>(); NEXT; }
1019 CASE(14) { II ii = inc_R<D,0>(); NEXT; }
1020 CASE(1C) { II ii = inc_R<E,0>(); NEXT; }
1021 CASE(24) { II ii = inc_R<H,0>(); NEXT; }
1022 CASE(2C) { II ii = inc_R<L,0>(); NEXT; }
1023 CASE(3C) { II ii = inc_R<A,0>(); NEXT; }
1024 CASE(34) { II ii = inc_xhl(); NEXT; }
1025 CASE(05) { II ii = dec_R<B,0>(); NEXT; }
1026 CASE(0D) { II ii = dec_R<C,0>(); NEXT; }
1027 CASE(15) { II ii = dec_R<D,0>(); NEXT; }
1028 CASE(1D) { II ii = dec_R<E,0>(); NEXT; }
1029 CASE(25) { II ii = dec_R<H,0>(); NEXT; }
1030 CASE(2D) { II ii = dec_R<L,0>(); NEXT; }
1031 CASE(3D) { II ii = dec_R<A,0>(); NEXT; }
1032 CASE(35) { II ii = dec_xhl(); NEXT; }
1033 CASE(06) { II ii = ld_R_byte<B,0>(); NEXT; }
1034 CASE(0E) { II ii = ld_R_byte<C,0>(); NEXT; }
1035 CASE(16) { II ii = ld_R_byte<D,0>(); NEXT; }
1036 CASE(1E) { II ii = ld_R_byte<E,0>(); NEXT; }
1037 CASE(26) { II ii = ld_R_byte<H,0>(); NEXT; }
1038 CASE(2E) { II ii = ld_R_byte<L,0>(); NEXT; }
1039 CASE(3E) { II ii = ld_R_byte<A,0>(); NEXT; }
1040 CASE(36) { II ii = ld_xhl_byte(); NEXT; }
1041 
1042 CASE(41) { II ii = ld_R_R<B,C,0>(); NEXT; }
1043 CASE(42) { II ii = ld_R_R<B,D,0>(); NEXT; }
1044 CASE(43) { II ii = ld_R_R<B,E,0>(); NEXT; }
1045 CASE(44) { II ii = ld_R_R<B,H,0>(); NEXT; }
1046 CASE(45) { II ii = ld_R_R<B,L,0>(); NEXT; }
1047 CASE(47) { II ii = ld_R_R<B,A,0>(); NEXT; }
1048 CASE(48) { II ii = ld_R_R<C,B,0>(); NEXT; }
1049 CASE(4A) { II ii = ld_R_R<C,D,0>(); NEXT; }
1050 CASE(4B) { II ii = ld_R_R<C,E,0>(); NEXT; }
1051 CASE(4C) { II ii = ld_R_R<C,H,0>(); NEXT; }
1052 CASE(4D) { II ii = ld_R_R<C,L,0>(); NEXT; }
1053 CASE(4F) { II ii = ld_R_R<C,A,0>(); NEXT; }
1054 CASE(50) { II ii = ld_R_R<D,B,0>(); NEXT; }
1055 CASE(51) { II ii = ld_R_R<D,C,0>(); NEXT; }
1056 CASE(53) { II ii = ld_R_R<D,E,0>(); NEXT; }
1057 CASE(54) { II ii = ld_R_R<D,H,0>(); NEXT; }
1058 CASE(55) { II ii = ld_R_R<D,L,0>(); NEXT; }
1059 CASE(57) { II ii = ld_R_R<D,A,0>(); NEXT; }
1060 CASE(58) { II ii = ld_R_R<E,B,0>(); NEXT; }
1061 CASE(59) { II ii = ld_R_R<E,C,0>(); NEXT; }
1062 CASE(5A) { II ii = ld_R_R<E,D,0>(); NEXT; }
1063 CASE(5C) { II ii = ld_R_R<E,H,0>(); NEXT; }
1064 CASE(5D) { II ii = ld_R_R<E,L,0>(); NEXT; }
1065 CASE(5F) { II ii = ld_R_R<E,A,0>(); NEXT; }
1066 CASE(60) { II ii = ld_R_R<H,B,0>(); NEXT; }
1067 CASE(61) { II ii = ld_R_R<H,C,0>(); NEXT; }
1068 CASE(62) { II ii = ld_R_R<H,D,0>(); NEXT; }
1069 CASE(63) { II ii = ld_R_R<H,E,0>(); NEXT; }
1070 CASE(65) { II ii = ld_R_R<H,L,0>(); NEXT; }
1071 CASE(67) { II ii = ld_R_R<H,A,0>(); NEXT; }
1072 CASE(68) { II ii = ld_R_R<L,B,0>(); NEXT; }
1073 CASE(69) { II ii = ld_R_R<L,C,0>(); NEXT; }
1074 CASE(6A) { II ii = ld_R_R<L,D,0>(); NEXT; }
1075 CASE(6B) { II ii = ld_R_R<L,E,0>(); NEXT; }
1076 CASE(6C) { II ii = ld_R_R<L,H,0>(); NEXT; }
1077 CASE(6F) { II ii = ld_R_R<L,A,0>(); NEXT; }
1078 CASE(78) { II ii = ld_R_R<A,B,0>(); NEXT; }
1079 CASE(79) { II ii = ld_R_R<A,C,0>(); NEXT; }
1080 CASE(7A) { II ii = ld_R_R<A,D,0>(); NEXT; }
1081 CASE(7B) { II ii = ld_R_R<A,E,0>(); NEXT; }
1082 CASE(7C) { II ii = ld_R_R<A,H,0>(); NEXT; }
1083 CASE(7D) { II ii = ld_R_R<A,L,0>(); NEXT; }
1084 CASE(70) { II ii = ld_xhl_R<B>(); NEXT; }
1085 CASE(71) { II ii = ld_xhl_R<C>(); NEXT; }
1086 CASE(72) { II ii = ld_xhl_R<D>(); NEXT; }
1087 CASE(73) { II ii = ld_xhl_R<E>(); NEXT; }
1088 CASE(74) { II ii = ld_xhl_R<H>(); NEXT; }
1089 CASE(75) { II ii = ld_xhl_R<L>(); NEXT; }
1090 CASE(77) { II ii = ld_xhl_R<A>(); NEXT; }
1091 CASE(46) { II ii = ld_R_xhl<B>(); NEXT; }
1092 CASE(4E) { II ii = ld_R_xhl<C>(); NEXT; }
1093 CASE(56) { II ii = ld_R_xhl<D>(); NEXT; }
1094 CASE(5E) { II ii = ld_R_xhl<E>(); NEXT; }
1095 CASE(66) { II ii = ld_R_xhl<H>(); NEXT; }
1096 CASE(6E) { II ii = ld_R_xhl<L>(); NEXT; }
1097 CASE(7E) { II ii = ld_R_xhl<A>(); NEXT; }
1098 CASE(76) { II ii = halt(); NEXT_STOP; }
1099 
1100 CASE(80) { II ii = add_a_R<B,0>(); NEXT; }
1101 CASE(81) { II ii = add_a_R<C,0>(); NEXT; }
1102 CASE(82) { II ii = add_a_R<D,0>(); NEXT; }
1103 CASE(83) { II ii = add_a_R<E,0>(); NEXT; }
1104 CASE(84) { II ii = add_a_R<H,0>(); NEXT; }
1105 CASE(85) { II ii = add_a_R<L,0>(); NEXT; }
1106 CASE(86) { II ii = add_a_xhl(); NEXT; }
1107 CASE(87) { II ii = add_a_a(); NEXT; }
1108 CASE(88) { II ii = adc_a_R<B,0>(); NEXT; }
1109 CASE(89) { II ii = adc_a_R<C,0>(); NEXT; }
1110 CASE(8A) { II ii = adc_a_R<D,0>(); NEXT; }
1111 CASE(8B) { II ii = adc_a_R<E,0>(); NEXT; }
1112 CASE(8C) { II ii = adc_a_R<H,0>(); NEXT; }
1113 CASE(8D) { II ii = adc_a_R<L,0>(); NEXT; }
1114 CASE(8E) { II ii = adc_a_xhl(); NEXT; }
1115 CASE(8F) { II ii = adc_a_a(); NEXT; }
1116 CASE(90) { II ii = sub_R<B,0>(); NEXT; }
1117 CASE(91) { II ii = sub_R<C,0>(); NEXT; }
1118 CASE(92) { II ii = sub_R<D,0>(); NEXT; }
1119 CASE(93) { II ii = sub_R<E,0>(); NEXT; }
1120 CASE(94) { II ii = sub_R<H,0>(); NEXT; }
1121 CASE(95) { II ii = sub_R<L,0>(); NEXT; }
1122 CASE(96) { II ii = sub_xhl(); NEXT; }
1123 CASE(97) { II ii = sub_a(); NEXT; }
1124 CASE(98) { II ii = sbc_a_R<B,0>(); NEXT; }
1125 CASE(99) { II ii = sbc_a_R<C,0>(); NEXT; }
1126 CASE(9A) { II ii = sbc_a_R<D,0>(); NEXT; }
1127 CASE(9B) { II ii = sbc_a_R<E,0>(); NEXT; }
1128 CASE(9C) { II ii = sbc_a_R<H,0>(); NEXT; }
1129 CASE(9D) { II ii = sbc_a_R<L,0>(); NEXT; }
1130 CASE(9E) { II ii = sbc_a_xhl(); NEXT; }
1131 CASE(9F) { II ii = sbc_a_a(); NEXT; }
1132 CASE(A0) { II ii = and_R<B,0>(); NEXT; }
1133 CASE(A1) { II ii = and_R<C,0>(); NEXT; }
1134 CASE(A2) { II ii = and_R<D,0>(); NEXT; }
1135 CASE(A3) { II ii = and_R<E,0>(); NEXT; }
1136 CASE(A4) { II ii = and_R<H,0>(); NEXT; }
1137 CASE(A5) { II ii = and_R<L,0>(); NEXT; }
1138 CASE(A6) { II ii = and_xhl(); NEXT; }
1139 CASE(A7) { II ii = and_a(); NEXT; }
1140 CASE(A8) { II ii = xor_R<B,0>(); NEXT; }
1141 CASE(A9) { II ii = xor_R<C,0>(); NEXT; }
1142 CASE(AA) { II ii = xor_R<D,0>(); NEXT; }
1143 CASE(AB) { II ii = xor_R<E,0>(); NEXT; }
1144 CASE(AC) { II ii = xor_R<H,0>(); NEXT; }
1145 CASE(AD) { II ii = xor_R<L,0>(); NEXT; }
1146 CASE(AE) { II ii = xor_xhl(); NEXT; }
1147 CASE(AF) { II ii = xor_a(); NEXT; }
1148 CASE(B0) { II ii = or_R<B,0>(); NEXT; }
1149 CASE(B1) { II ii = or_R<C,0>(); NEXT; }
1150 CASE(B2) { II ii = or_R<D,0>(); NEXT; }
1151 CASE(B3) { II ii = or_R<E,0>(); NEXT; }
1152 CASE(B4) { II ii = or_R<H,0>(); NEXT; }
1153 CASE(B5) { II ii = or_R<L,0>(); NEXT; }
1154 CASE(B6) { II ii = or_xhl(); NEXT; }
1155 CASE(B7) { II ii = or_a(); NEXT; }
1156 CASE(B8) { II ii = cp_R<B,0>(); NEXT; }
1157 CASE(B9) { II ii = cp_R<C,0>(); NEXT; }
1158 CASE(BA) { II ii = cp_R<D,0>(); NEXT; }
1159 CASE(BB) { II ii = cp_R<E,0>(); NEXT; }
1160 CASE(BC) { II ii = cp_R<H,0>(); NEXT; }
1161 CASE(BD) { II ii = cp_R<L,0>(); NEXT; }
1162 CASE(BE) { II ii = cp_xhl(); NEXT; }
1163 CASE(BF) { II ii = cp_a(); NEXT; }
1164 
1165 CASE(D3) { II ii = out_byte_a(); NEXT; }
1166 CASE(DB) { II ii = in_a_byte(); NEXT; }
1167 CASE(D9) { II ii = exx(); NEXT; }
1168 CASE(E3) { II ii = ex_xsp_SS<HL,0>(); NEXT; }
1169 CASE(EB) { II ii = ex_de_hl(); NEXT; }
1170 CASE(E9) { II ii = jp_SS<HL,0>(); NEXT; }
1171 CASE(F9) { II ii = ld_sp_SS<HL,0>(); NEXT; }
1172 CASE(F3) { II ii = di(); NEXT; }
1173 CASE(FB) { II ii = ei(); NEXT_EI; }
1174 CASE(C6) { II ii = add_a_byte(); NEXT; }
1175 CASE(CE) { II ii = adc_a_byte(); NEXT; }
1176 CASE(D6) { II ii = sub_byte(); NEXT; }
1177 CASE(DE) { II ii = sbc_a_byte(); NEXT; }
1178 CASE(E6) { II ii = and_byte(); NEXT; }
1179 CASE(EE) { II ii = xor_byte(); NEXT; }
1180 CASE(F6) { II ii = or_byte(); NEXT; }
1181 CASE(FE) { II ii = cp_byte(); NEXT; }
1182 CASE(C0) { II ii = ret(CondNZ()); NEXT; }
1183 CASE(C8) { II ii = ret(CondZ ()); NEXT; }
1184 CASE(D0) { II ii = ret(CondNC()); NEXT; }
1185 CASE(D8) { II ii = ret(CondC ()); NEXT; }
1186 CASE(E0) { II ii = ret(CondPO()); NEXT; }
1187 CASE(E8) { II ii = ret(CondPE()); NEXT; }
1188 CASE(F0) { II ii = ret(CondP ()); NEXT; }
1189 CASE(F8) { II ii = ret(CondM ()); NEXT; }
1190 CASE(C9) { II ii = ret(); NEXT; }
1191 CASE(C2) { II ii = jp(CondNZ()); NEXT; }
1192 CASE(CA) { II ii = jp(CondZ ()); NEXT; }
1193 CASE(D2) { II ii = jp(CondNC()); NEXT; }
1194 CASE(DA) { II ii = jp(CondC ()); NEXT; }
1195 CASE(E2) { II ii = jp(CondPO()); NEXT; }
1196 CASE(EA) { II ii = jp(CondPE()); NEXT; }
1197 CASE(F2) { II ii = jp(CondP ()); NEXT; }
1198 CASE(FA) { II ii = jp(CondM ()); NEXT; }
1199 CASE(C3) { II ii = jp(CondTrue()); NEXT; }
1200 CASE(C4) { II ii = call(CondNZ()); NEXT; }
1201 CASE(CC) { II ii = call(CondZ ()); NEXT; }
1202 CASE(D4) { II ii = call(CondNC()); NEXT; }
1203 CASE(DC) { II ii = call(CondC ()); NEXT; }
1204 CASE(E4) { II ii = call(CondPO()); NEXT; }
1205 CASE(EC) { II ii = call(CondPE()); NEXT; }
1206 CASE(F4) { II ii = call(CondP ()); NEXT; }
1207 CASE(FC) { II ii = call(CondM ()); NEXT; }
1208 CASE(CD) { II ii = call(CondTrue()); NEXT; }
1209 CASE(C1) { II ii = pop_SS <BC,0>(); NEXT; }
1210 CASE(D1) { II ii = pop_SS <DE,0>(); NEXT; }
1211 CASE(E1) { II ii = pop_SS <HL,0>(); NEXT; }
1212 CASE(F1) { II ii = pop_SS <AF,0>(); NEXT; }
1213 CASE(C5) { II ii = push_SS<BC,0>(); NEXT; }
1214 CASE(D5) { II ii = push_SS<DE,0>(); NEXT; }
1215 CASE(E5) { II ii = push_SS<HL,0>(); NEXT; }
1216 CASE(F5) { II ii = push_SS<AF,0>(); NEXT; }
1217 CASE(C7) { II ii = rst<0x00>(); NEXT; }
1218 CASE(CF) { II ii = rst<0x08>(); NEXT; }
1219 CASE(D7) { II ii = rst<0x10>(); NEXT; }
1220 CASE(DF) { II ii = rst<0x18>(); NEXT; }
1221 CASE(E7) { II ii = rst<0x20>(); NEXT; }
1222 CASE(EF) { II ii = rst<0x28>(); NEXT; }
1223 CASE(F7) { II ii = rst<0x30>(); NEXT; }
1224 CASE(FF) { II ii = rst<0x38>(); NEXT; }
1225 CASE(CB) {
1226  setPC(getPC() + 1); // M1 cycle at this point
1227  byte cb_opcode = RDMEM_OPCODE<0>(T::CC_PREFIX);
1228  incR(1);
1229  switch (cb_opcode) {
1230  case 0x00: { II ii = rlc_R<B>(); NEXT; }
1231  case 0x01: { II ii = rlc_R<C>(); NEXT; }
1232  case 0x02: { II ii = rlc_R<D>(); NEXT; }
1233  case 0x03: { II ii = rlc_R<E>(); NEXT; }
1234  case 0x04: { II ii = rlc_R<H>(); NEXT; }
1235  case 0x05: { II ii = rlc_R<L>(); NEXT; }
1236  case 0x07: { II ii = rlc_R<A>(); NEXT; }
1237  case 0x06: { II ii = rlc_xhl(); NEXT; }
1238  case 0x08: { II ii = rrc_R<B>(); NEXT; }
1239  case 0x09: { II ii = rrc_R<C>(); NEXT; }
1240  case 0x0a: { II ii = rrc_R<D>(); NEXT; }
1241  case 0x0b: { II ii = rrc_R<E>(); NEXT; }
1242  case 0x0c: { II ii = rrc_R<H>(); NEXT; }
1243  case 0x0d: { II ii = rrc_R<L>(); NEXT; }
1244  case 0x0f: { II ii = rrc_R<A>(); NEXT; }
1245  case 0x0e: { II ii = rrc_xhl(); NEXT; }
1246  case 0x10: { II ii = rl_R<B>(); NEXT; }
1247  case 0x11: { II ii = rl_R<C>(); NEXT; }
1248  case 0x12: { II ii = rl_R<D>(); NEXT; }
1249  case 0x13: { II ii = rl_R<E>(); NEXT; }
1250  case 0x14: { II ii = rl_R<H>(); NEXT; }
1251  case 0x15: { II ii = rl_R<L>(); NEXT; }
1252  case 0x17: { II ii = rl_R<A>(); NEXT; }
1253  case 0x16: { II ii = rl_xhl(); NEXT; }
1254  case 0x18: { II ii = rr_R<B>(); NEXT; }
1255  case 0x19: { II ii = rr_R<C>(); NEXT; }
1256  case 0x1a: { II ii = rr_R<D>(); NEXT; }
1257  case 0x1b: { II ii = rr_R<E>(); NEXT; }
1258  case 0x1c: { II ii = rr_R<H>(); NEXT; }
1259  case 0x1d: { II ii = rr_R<L>(); NEXT; }
1260  case 0x1f: { II ii = rr_R<A>(); NEXT; }
1261  case 0x1e: { II ii = rr_xhl(); NEXT; }
1262  case 0x20: { II ii = sla_R<B>(); NEXT; }
1263  case 0x21: { II ii = sla_R<C>(); NEXT; }
1264  case 0x22: { II ii = sla_R<D>(); NEXT; }
1265  case 0x23: { II ii = sla_R<E>(); NEXT; }
1266  case 0x24: { II ii = sla_R<H>(); NEXT; }
1267  case 0x25: { II ii = sla_R<L>(); NEXT; }
1268  case 0x27: { II ii = sla_R<A>(); NEXT; }
1269  case 0x26: { II ii = sla_xhl(); NEXT; }
1270  case 0x28: { II ii = sra_R<B>(); NEXT; }
1271  case 0x29: { II ii = sra_R<C>(); NEXT; }
1272  case 0x2a: { II ii = sra_R<D>(); NEXT; }
1273  case 0x2b: { II ii = sra_R<E>(); NEXT; }
1274  case 0x2c: { II ii = sra_R<H>(); NEXT; }
1275  case 0x2d: { II ii = sra_R<L>(); NEXT; }
1276  case 0x2f: { II ii = sra_R<A>(); NEXT; }
1277  case 0x2e: { II ii = sra_xhl(); NEXT; }
1278  case 0x30: { II ii = T::IS_R800 ? sla_R<B>() : sll_R<B>(); NEXT; }
1279  case 0x31: { II ii = T::IS_R800 ? sla_R<C>() : sll_R<C>(); NEXT; }
1280  case 0x32: { II ii = T::IS_R800 ? sla_R<D>() : sll_R<D>(); NEXT; }
1281  case 0x33: { II ii = T::IS_R800 ? sla_R<E>() : sll_R<E>(); NEXT; }
1282  case 0x34: { II ii = T::IS_R800 ? sla_R<H>() : sll_R<H>(); NEXT; }
1283  case 0x35: { II ii = T::IS_R800 ? sla_R<L>() : sll_R<L>(); NEXT; }
1284  case 0x37: { II ii = T::IS_R800 ? sla_R<A>() : sll_R<A>(); NEXT; }
1285  case 0x36: { II ii = T::IS_R800 ? sla_xhl() : sll_xhl(); NEXT; }
1286  case 0x38: { II ii = srl_R<B>(); NEXT; }
1287  case 0x39: { II ii = srl_R<C>(); NEXT; }
1288  case 0x3a: { II ii = srl_R<D>(); NEXT; }
1289  case 0x3b: { II ii = srl_R<E>(); NEXT; }
1290  case 0x3c: { II ii = srl_R<H>(); NEXT; }
1291  case 0x3d: { II ii = srl_R<L>(); NEXT; }
1292  case 0x3f: { II ii = srl_R<A>(); NEXT; }
1293  case 0x3e: { II ii = srl_xhl(); NEXT; }
1294 
1295  case 0x40: { II ii = bit_N_R<0,B>(); NEXT; }
1296  case 0x41: { II ii = bit_N_R<0,C>(); NEXT; }
1297  case 0x42: { II ii = bit_N_R<0,D>(); NEXT; }
1298  case 0x43: { II ii = bit_N_R<0,E>(); NEXT; }
1299  case 0x44: { II ii = bit_N_R<0,H>(); NEXT; }
1300  case 0x45: { II ii = bit_N_R<0,L>(); NEXT; }
1301  case 0x47: { II ii = bit_N_R<0,A>(); NEXT; }
1302  case 0x48: { II ii = bit_N_R<1,B>(); NEXT; }
1303  case 0x49: { II ii = bit_N_R<1,C>(); NEXT; }
1304  case 0x4a: { II ii = bit_N_R<1,D>(); NEXT; }
1305  case 0x4b: { II ii = bit_N_R<1,E>(); NEXT; }
1306  case 0x4c: { II ii = bit_N_R<1,H>(); NEXT; }
1307  case 0x4d: { II ii = bit_N_R<1,L>(); NEXT; }
1308  case 0x4f: { II ii = bit_N_R<1,A>(); NEXT; }
1309  case 0x50: { II ii = bit_N_R<2,B>(); NEXT; }
1310  case 0x51: { II ii = bit_N_R<2,C>(); NEXT; }
1311  case 0x52: { II ii = bit_N_R<2,D>(); NEXT; }
1312  case 0x53: { II ii = bit_N_R<2,E>(); NEXT; }
1313  case 0x54: { II ii = bit_N_R<2,H>(); NEXT; }
1314  case 0x55: { II ii = bit_N_R<2,L>(); NEXT; }
1315  case 0x57: { II ii = bit_N_R<2,A>(); NEXT; }
1316  case 0x58: { II ii = bit_N_R<3,B>(); NEXT; }
1317  case 0x59: { II ii = bit_N_R<3,C>(); NEXT; }
1318  case 0x5a: { II ii = bit_N_R<3,D>(); NEXT; }
1319  case 0x5b: { II ii = bit_N_R<3,E>(); NEXT; }
1320  case 0x5c: { II ii = bit_N_R<3,H>(); NEXT; }
1321  case 0x5d: { II ii = bit_N_R<3,L>(); NEXT; }
1322  case 0x5f: { II ii = bit_N_R<3,A>(); NEXT; }
1323  case 0x60: { II ii = bit_N_R<4,B>(); NEXT; }
1324  case 0x61: { II ii = bit_N_R<4,C>(); NEXT; }
1325  case 0x62: { II ii = bit_N_R<4,D>(); NEXT; }
1326  case 0x63: { II ii = bit_N_R<4,E>(); NEXT; }
1327  case 0x64: { II ii = bit_N_R<4,H>(); NEXT; }
1328  case 0x65: { II ii = bit_N_R<4,L>(); NEXT; }
1329  case 0x67: { II ii = bit_N_R<4,A>(); NEXT; }
1330  case 0x68: { II ii = bit_N_R<5,B>(); NEXT; }
1331  case 0x69: { II ii = bit_N_R<5,C>(); NEXT; }
1332  case 0x6a: { II ii = bit_N_R<5,D>(); NEXT; }
1333  case 0x6b: { II ii = bit_N_R<5,E>(); NEXT; }
1334  case 0x6c: { II ii = bit_N_R<5,H>(); NEXT; }
1335  case 0x6d: { II ii = bit_N_R<5,L>(); NEXT; }
1336  case 0x6f: { II ii = bit_N_R<5,A>(); NEXT; }
1337  case 0x70: { II ii = bit_N_R<6,B>(); NEXT; }
1338  case 0x71: { II ii = bit_N_R<6,C>(); NEXT; }
1339  case 0x72: { II ii = bit_N_R<6,D>(); NEXT; }
1340  case 0x73: { II ii = bit_N_R<6,E>(); NEXT; }
1341  case 0x74: { II ii = bit_N_R<6,H>(); NEXT; }
1342  case 0x75: { II ii = bit_N_R<6,L>(); NEXT; }
1343  case 0x77: { II ii = bit_N_R<6,A>(); NEXT; }
1344  case 0x78: { II ii = bit_N_R<7,B>(); NEXT; }
1345  case 0x79: { II ii = bit_N_R<7,C>(); NEXT; }
1346  case 0x7a: { II ii = bit_N_R<7,D>(); NEXT; }
1347  case 0x7b: { II ii = bit_N_R<7,E>(); NEXT; }
1348  case 0x7c: { II ii = bit_N_R<7,H>(); NEXT; }
1349  case 0x7d: { II ii = bit_N_R<7,L>(); NEXT; }
1350  case 0x7f: { II ii = bit_N_R<7,A>(); NEXT; }
1351  case 0x46: { II ii = bit_N_xhl<0>(); NEXT; }
1352  case 0x4e: { II ii = bit_N_xhl<1>(); NEXT; }
1353  case 0x56: { II ii = bit_N_xhl<2>(); NEXT; }
1354  case 0x5e: { II ii = bit_N_xhl<3>(); NEXT; }
1355  case 0x66: { II ii = bit_N_xhl<4>(); NEXT; }
1356  case 0x6e: { II ii = bit_N_xhl<5>(); NEXT; }
1357  case 0x76: { II ii = bit_N_xhl<6>(); NEXT; }
1358  case 0x7e: { II ii = bit_N_xhl<7>(); NEXT; }
1359 
1360  case 0x80: { II ii = res_N_R<0,B>(); NEXT; }
1361  case 0x81: { II ii = res_N_R<0,C>(); NEXT; }
1362  case 0x82: { II ii = res_N_R<0,D>(); NEXT; }
1363  case 0x83: { II ii = res_N_R<0,E>(); NEXT; }
1364  case 0x84: { II ii = res_N_R<0,H>(); NEXT; }
1365  case 0x85: { II ii = res_N_R<0,L>(); NEXT; }
1366  case 0x87: { II ii = res_N_R<0,A>(); NEXT; }
1367  case 0x88: { II ii = res_N_R<1,B>(); NEXT; }
1368  case 0x89: { II ii = res_N_R<1,C>(); NEXT; }
1369  case 0x8a: { II ii = res_N_R<1,D>(); NEXT; }
1370  case 0x8b: { II ii = res_N_R<1,E>(); NEXT; }
1371  case 0x8c: { II ii = res_N_R<1,H>(); NEXT; }
1372  case 0x8d: { II ii = res_N_R<1,L>(); NEXT; }
1373  case 0x8f: { II ii = res_N_R<1,A>(); NEXT; }
1374  case 0x90: { II ii = res_N_R<2,B>(); NEXT; }
1375  case 0x91: { II ii = res_N_R<2,C>(); NEXT; }
1376  case 0x92: { II ii = res_N_R<2,D>(); NEXT; }
1377  case 0x93: { II ii = res_N_R<2,E>(); NEXT; }
1378  case 0x94: { II ii = res_N_R<2,H>(); NEXT; }
1379  case 0x95: { II ii = res_N_R<2,L>(); NEXT; }
1380  case 0x97: { II ii = res_N_R<2,A>(); NEXT; }
1381  case 0x98: { II ii = res_N_R<3,B>(); NEXT; }
1382  case 0x99: { II ii = res_N_R<3,C>(); NEXT; }
1383  case 0x9a: { II ii = res_N_R<3,D>(); NEXT; }
1384  case 0x9b: { II ii = res_N_R<3,E>(); NEXT; }
1385  case 0x9c: { II ii = res_N_R<3,H>(); NEXT; }
1386  case 0x9d: { II ii = res_N_R<3,L>(); NEXT; }
1387  case 0x9f: { II ii = res_N_R<3,A>(); NEXT; }
1388  case 0xa0: { II ii = res_N_R<4,B>(); NEXT; }
1389  case 0xa1: { II ii = res_N_R<4,C>(); NEXT; }
1390  case 0xa2: { II ii = res_N_R<4,D>(); NEXT; }
1391  case 0xa3: { II ii = res_N_R<4,E>(); NEXT; }
1392  case 0xa4: { II ii = res_N_R<4,H>(); NEXT; }
1393  case 0xa5: { II ii = res_N_R<4,L>(); NEXT; }
1394  case 0xa7: { II ii = res_N_R<4,A>(); NEXT; }
1395  case 0xa8: { II ii = res_N_R<5,B>(); NEXT; }
1396  case 0xa9: { II ii = res_N_R<5,C>(); NEXT; }
1397  case 0xaa: { II ii = res_N_R<5,D>(); NEXT; }
1398  case 0xab: { II ii = res_N_R<5,E>(); NEXT; }
1399  case 0xac: { II ii = res_N_R<5,H>(); NEXT; }
1400  case 0xad: { II ii = res_N_R<5,L>(); NEXT; }
1401  case 0xaf: { II ii = res_N_R<5,A>(); NEXT; }
1402  case 0xb0: { II ii = res_N_R<6,B>(); NEXT; }
1403  case 0xb1: { II ii = res_N_R<6,C>(); NEXT; }
1404  case 0xb2: { II ii = res_N_R<6,D>(); NEXT; }
1405  case 0xb3: { II ii = res_N_R<6,E>(); NEXT; }
1406  case 0xb4: { II ii = res_N_R<6,H>(); NEXT; }
1407  case 0xb5: { II ii = res_N_R<6,L>(); NEXT; }
1408  case 0xb7: { II ii = res_N_R<6,A>(); NEXT; }
1409  case 0xb8: { II ii = res_N_R<7,B>(); NEXT; }
1410  case 0xb9: { II ii = res_N_R<7,C>(); NEXT; }
1411  case 0xba: { II ii = res_N_R<7,D>(); NEXT; }
1412  case 0xbb: { II ii = res_N_R<7,E>(); NEXT; }
1413  case 0xbc: { II ii = res_N_R<7,H>(); NEXT; }
1414  case 0xbd: { II ii = res_N_R<7,L>(); NEXT; }
1415  case 0xbf: { II ii = res_N_R<7,A>(); NEXT; }
1416  case 0x86: { II ii = res_N_xhl<0>(); NEXT; }
1417  case 0x8e: { II ii = res_N_xhl<1>(); NEXT; }
1418  case 0x96: { II ii = res_N_xhl<2>(); NEXT; }
1419  case 0x9e: { II ii = res_N_xhl<3>(); NEXT; }
1420  case 0xa6: { II ii = res_N_xhl<4>(); NEXT; }
1421  case 0xae: { II ii = res_N_xhl<5>(); NEXT; }
1422  case 0xb6: { II ii = res_N_xhl<6>(); NEXT; }
1423  case 0xbe: { II ii = res_N_xhl<7>(); NEXT; }
1424 
1425  case 0xc0: { II ii = set_N_R<0,B>(); NEXT; }
1426  case 0xc1: { II ii = set_N_R<0,C>(); NEXT; }
1427  case 0xc2: { II ii = set_N_R<0,D>(); NEXT; }
1428  case 0xc3: { II ii = set_N_R<0,E>(); NEXT; }
1429  case 0xc4: { II ii = set_N_R<0,H>(); NEXT; }
1430  case 0xc5: { II ii = set_N_R<0,L>(); NEXT; }
1431  case 0xc7: { II ii = set_N_R<0,A>(); NEXT; }
1432  case 0xc8: { II ii = set_N_R<1,B>(); NEXT; }
1433  case 0xc9: { II ii = set_N_R<1,C>(); NEXT; }
1434  case 0xca: { II ii = set_N_R<1,D>(); NEXT; }
1435  case 0xcb: { II ii = set_N_R<1,E>(); NEXT; }
1436  case 0xcc: { II ii = set_N_R<1,H>(); NEXT; }
1437  case 0xcd: { II ii = set_N_R<1,L>(); NEXT; }
1438  case 0xcf: { II ii = set_N_R<1,A>(); NEXT; }
1439  case 0xd0: { II ii = set_N_R<2,B>(); NEXT; }
1440  case 0xd1: { II ii = set_N_R<2,C>(); NEXT; }
1441  case 0xd2: { II ii = set_N_R<2,D>(); NEXT; }
1442  case 0xd3: { II ii = set_N_R<2,E>(); NEXT; }
1443  case 0xd4: { II ii = set_N_R<2,H>(); NEXT; }
1444  case 0xd5: { II ii = set_N_R<2,L>(); NEXT; }
1445  case 0xd7: { II ii = set_N_R<2,A>(); NEXT; }
1446  case 0xd8: { II ii = set_N_R<3,B>(); NEXT; }
1447  case 0xd9: { II ii = set_N_R<3,C>(); NEXT; }
1448  case 0xda: { II ii = set_N_R<3,D>(); NEXT; }
1449  case 0xdb: { II ii = set_N_R<3,E>(); NEXT; }
1450  case 0xdc: { II ii = set_N_R<3,H>(); NEXT; }
1451  case 0xdd: { II ii = set_N_R<3,L>(); NEXT; }
1452  case 0xdf: { II ii = set_N_R<3,A>(); NEXT; }
1453  case 0xe0: { II ii = set_N_R<4,B>(); NEXT; }
1454  case 0xe1: { II ii = set_N_R<4,C>(); NEXT; }
1455  case 0xe2: { II ii = set_N_R<4,D>(); NEXT; }
1456  case 0xe3: { II ii = set_N_R<4,E>(); NEXT; }
1457  case 0xe4: { II ii = set_N_R<4,H>(); NEXT; }
1458  case 0xe5: { II ii = set_N_R<4,L>(); NEXT; }
1459  case 0xe7: { II ii = set_N_R<4,A>(); NEXT; }
1460  case 0xe8: { II ii = set_N_R<5,B>(); NEXT; }
1461  case 0xe9: { II ii = set_N_R<5,C>(); NEXT; }
1462  case 0xea: { II ii = set_N_R<5,D>(); NEXT; }
1463  case 0xeb: { II ii = set_N_R<5,E>(); NEXT; }
1464  case 0xec: { II ii = set_N_R<5,H>(); NEXT; }
1465  case 0xed: { II ii = set_N_R<5,L>(); NEXT; }
1466  case 0xef: { II ii = set_N_R<5,A>(); NEXT; }
1467  case 0xf0: { II ii = set_N_R<6,B>(); NEXT; }
1468  case 0xf1: { II ii = set_N_R<6,C>(); NEXT; }
1469  case 0xf2: { II ii = set_N_R<6,D>(); NEXT; }
1470  case 0xf3: { II ii = set_N_R<6,E>(); NEXT; }
1471  case 0xf4: { II ii = set_N_R<6,H>(); NEXT; }
1472  case 0xf5: { II ii = set_N_R<6,L>(); NEXT; }
1473  case 0xf7: { II ii = set_N_R<6,A>(); NEXT; }
1474  case 0xf8: { II ii = set_N_R<7,B>(); NEXT; }
1475  case 0xf9: { II ii = set_N_R<7,C>(); NEXT; }
1476  case 0xfa: { II ii = set_N_R<7,D>(); NEXT; }
1477  case 0xfb: { II ii = set_N_R<7,E>(); NEXT; }
1478  case 0xfc: { II ii = set_N_R<7,H>(); NEXT; }
1479  case 0xfd: { II ii = set_N_R<7,L>(); NEXT; }
1480  case 0xff: { II ii = set_N_R<7,A>(); NEXT; }
1481  case 0xc6: { II ii = set_N_xhl<0>(); NEXT; }
1482  case 0xce: { II ii = set_N_xhl<1>(); NEXT; }
1483  case 0xd6: { II ii = set_N_xhl<2>(); NEXT; }
1484  case 0xde: { II ii = set_N_xhl<3>(); NEXT; }
1485  case 0xe6: { II ii = set_N_xhl<4>(); NEXT; }
1486  case 0xee: { II ii = set_N_xhl<5>(); NEXT; }
1487  case 0xf6: { II ii = set_N_xhl<6>(); NEXT; }
1488  case 0xfe: { II ii = set_N_xhl<7>(); NEXT; }
1489  default: UNREACHABLE; return;
1490  }
1491 }
1492 CASE(ED) {
1493  setPC(getPC() + 1); // M1 cycle at this point
1494  byte ed_opcode = RDMEM_OPCODE<0>(T::CC_PREFIX);
1495  incR(1);
1496  switch (ed_opcode) {
1497  case 0x00: case 0x01: case 0x02: case 0x03:
1498  case 0x04: case 0x05: case 0x06: case 0x07:
1499  case 0x08: case 0x09: case 0x0a: case 0x0b:
1500  case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1501  case 0x10: case 0x11: case 0x12: case 0x13:
1502  case 0x14: case 0x15: case 0x16: case 0x17:
1503  case 0x18: case 0x19: case 0x1a: case 0x1b:
1504  case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1505  case 0x20: case 0x21: case 0x22: case 0x23:
1506  case 0x24: case 0x25: case 0x26: case 0x27:
1507  case 0x28: case 0x29: case 0x2a: case 0x2b:
1508  case 0x2c: case 0x2d: case 0x2e: case 0x2f:
1509  case 0x30: case 0x31: case 0x32: case 0x33:
1510  case 0x34: case 0x35: case 0x36: case 0x37:
1511  case 0x38: case 0x39: case 0x3a: case 0x3b:
1512  case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1513 
1514  case 0x77: case 0x7f:
1515 
1516  case 0x80: case 0x81: case 0x82: case 0x83:
1517  case 0x84: case 0x85: case 0x86: case 0x87:
1518  case 0x88: case 0x89: case 0x8a: case 0x8b:
1519  case 0x8c: case 0x8d: case 0x8e: case 0x8f:
1520  case 0x90: case 0x91: case 0x92: case 0x93:
1521  case 0x94: case 0x95: case 0x96: case 0x97:
1522  case 0x98: case 0x99: case 0x9a: case 0x9b:
1523  case 0x9c: case 0x9d: case 0x9e: case 0x9f:
1524  case 0xa4: case 0xa5: case 0xa6: case 0xa7:
1525  case 0xac: case 0xad: case 0xae: case 0xaf:
1526  case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1527  case 0xbc: case 0xbd: case 0xbe: case 0xbf:
1528 
1529  case 0xc0: case 0xc2:
1530  case 0xc4: case 0xc5: case 0xc6: case 0xc7:
1531  case 0xc8: case 0xca: case 0xcb:
1532  case 0xcc: case 0xcd: case 0xce: case 0xcf:
1533  case 0xd0: case 0xd2: case 0xd3:
1534  case 0xd4: case 0xd5: case 0xd6: case 0xd7:
1535  case 0xd8: case 0xda: case 0xdb:
1536  case 0xdc: case 0xdd: case 0xde: case 0xdf:
1537  case 0xe0: case 0xe1: case 0xe2: case 0xe3:
1538  case 0xe4: case 0xe5: case 0xe6: case 0xe7:
1539  case 0xe8: case 0xe9: case 0xea: case 0xeb:
1540  case 0xec: case 0xed: case 0xee: case 0xef:
1541  case 0xf0: case 0xf1: case 0xf2:
1542  case 0xf4: case 0xf5: case 0xf6: case 0xf7:
1543  case 0xf8: case 0xf9: case 0xfa: case 0xfb:
1544  case 0xfc: case 0xfd: case 0xfe: case 0xff:
1545  { II ii = nop(); NEXT; }
1546 
1547  case 0x40: { II ii = in_R_c<B>(); NEXT; }
1548  case 0x48: { II ii = in_R_c<C>(); NEXT; }
1549  case 0x50: { II ii = in_R_c<D>(); NEXT; }
1550  case 0x58: { II ii = in_R_c<E>(); NEXT; }
1551  case 0x60: { II ii = in_R_c<H>(); NEXT; }
1552  case 0x68: { II ii = in_R_c<L>(); NEXT; }
1553  case 0x70: { II ii = in_R_c<DUMMY>(); NEXT; }
1554  case 0x78: { II ii = in_R_c<A>(); NEXT; }
1555 
1556  case 0x41: { II ii = out_c_R<B>(); NEXT; }
1557  case 0x49: { II ii = out_c_R<C>(); NEXT; }
1558  case 0x51: { II ii = out_c_R<D>(); NEXT; }
1559  case 0x59: { II ii = out_c_R<E>(); NEXT; }
1560  case 0x61: { II ii = out_c_R<H>(); NEXT; }
1561  case 0x69: { II ii = out_c_R<L>(); NEXT; }
1562  case 0x71: { II ii = out_c_0(); NEXT; }
1563  case 0x79: { II ii = out_c_R<A>(); NEXT; }
1564 
1565  case 0x42: { II ii = sbc_hl_SS<BC>(); NEXT; }
1566  case 0x52: { II ii = sbc_hl_SS<DE>(); NEXT; }
1567  case 0x62: { II ii = sbc_hl_hl (); NEXT; }
1568  case 0x72: { II ii = sbc_hl_SS<SP>(); NEXT; }
1569 
1570  case 0x4a: { II ii = adc_hl_SS<BC>(); NEXT; }
1571  case 0x5a: { II ii = adc_hl_SS<DE>(); NEXT; }
1572  case 0x6a: { II ii = adc_hl_hl (); NEXT; }
1573  case 0x7a: { II ii = adc_hl_SS<SP>(); NEXT; }
1574 
1575  case 0x43: { II ii = ld_xword_SS_ED<BC>(); NEXT; }
1576  case 0x53: { II ii = ld_xword_SS_ED<DE>(); NEXT; }
1577  case 0x63: { II ii = ld_xword_SS_ED<HL>(); NEXT; }
1578  case 0x73: { II ii = ld_xword_SS_ED<SP>(); NEXT; }
1579 
1580  case 0x4b: { II ii = ld_SS_xword_ED<BC>(); NEXT; }
1581  case 0x5b: { II ii = ld_SS_xword_ED<DE>(); NEXT; }
1582  case 0x6b: { II ii = ld_SS_xword_ED<HL>(); NEXT; }
1583  case 0x7b: { II ii = ld_SS_xword_ED<SP>(); NEXT; }
1584 
1585  case 0x47: { II ii = ld_i_a(); NEXT; }
1586  case 0x4f: { II ii = ld_r_a(); NEXT; }
1587  case 0x57: { II ii = ld_a_IR<REG_I>(); if (T::IS_R800) { NEXT; } else { NEXT_STOP; }}
1588  case 0x5f: { II ii = ld_a_IR<REG_R>(); if (T::IS_R800) { NEXT; } else { NEXT_STOP; }}
1589 
1590  case 0x67: { II ii = rrd(); NEXT; }
1591  case 0x6f: { II ii = rld(); NEXT; }
1592 
1593  case 0x45: case 0x4d: case 0x55: case 0x5d:
1594  case 0x65: case 0x6d: case 0x75: case 0x7d:
1595  { II ii = retn(); NEXT_STOP; }
1596  case 0x46: case 0x4e: case 0x66: case 0x6e:
1597  { II ii = im_N<0>(); NEXT; }
1598  case 0x56: case 0x76:
1599  { II ii = im_N<1>(); NEXT; }
1600  case 0x5e: case 0x7e:
1601  { II ii = im_N<2>(); NEXT; }
1602  case 0x44: case 0x4c: case 0x54: case 0x5c:
1603  case 0x64: case 0x6c: case 0x74: case 0x7c:
1604  { II ii = neg(); NEXT; }
1605 
1606  case 0xa0: { II ii = ldi(); NEXT; }
1607  case 0xa1: { II ii = cpi(); NEXT; }
1608  case 0xa2: { II ii = ini(); NEXT; }
1609  case 0xa3: { II ii = outi(); NEXT; }
1610  case 0xa8: { II ii = ldd(); NEXT; }
1611  case 0xa9: { II ii = cpd(); NEXT; }
1612  case 0xaa: { II ii = ind(); NEXT; }
1613  case 0xab: { II ii = outd(); NEXT; }
1614  case 0xb0: { II ii = ldir(); NEXT; }
1615  case 0xb1: { II ii = cpir(); NEXT; }
1616  case 0xb2: { II ii = inir(); NEXT; }
1617  case 0xb3: { II ii = otir(); NEXT; }
1618  case 0xb8: { II ii = lddr(); NEXT; }
1619  case 0xb9: { II ii = cpdr(); NEXT; }
1620  case 0xba: { II ii = indr(); NEXT; }
1621  case 0xbb: { II ii = otdr(); NEXT; }
1622 
1623  case 0xc1: { II ii = T::IS_R800 ? mulub_a_R<B>() : nop(); NEXT; }
1624  case 0xc9: { II ii = T::IS_R800 ? mulub_a_R<C>() : nop(); NEXT; }
1625  case 0xd1: { II ii = T::IS_R800 ? mulub_a_R<D>() : nop(); NEXT; }
1626  case 0xd9: { II ii = T::IS_R800 ? mulub_a_R<E>() : nop(); NEXT; }
1627  case 0xc3: { II ii = T::IS_R800 ? muluw_hl_SS<BC>() : nop(); NEXT; }
1628  case 0xf3: { II ii = T::IS_R800 ? muluw_hl_SS<SP>() : nop(); NEXT; }
1629  default: UNREACHABLE; return;
1630  }
1631 }
1632 opDD_2:
1633 CASE(DD) {
1634  setPC(getPC() + 1); // M1 cycle at this point
1635  byte opcodeDD = RDMEM_OPCODE<0>(T::CC_DD + T::CC_MAIN);
1636  incR(1);
1637  switch (opcodeDD) {
1638  case 0x00: // nop();
1639  case 0x01: // ld_bc_word();
1640  case 0x02: // ld_xbc_a();
1641  case 0x03: // inc_bc();
1642  case 0x04: // inc_b();
1643  case 0x05: // dec_b();
1644  case 0x06: // ld_b_byte();
1645  case 0x07: // rlca();
1646  case 0x08: // ex_af_af();
1647  case 0x0a: // ld_a_xbc();
1648  case 0x0b: // dec_bc();
1649  case 0x0c: // inc_c();
1650  case 0x0d: // dec_c();
1651  case 0x0e: // ld_c_byte();
1652  case 0x0f: // rrca();
1653  case 0x10: // djnz();
1654  case 0x11: // ld_de_word();
1655  case 0x12: // ld_xde_a();
1656  case 0x13: // inc_de();
1657  case 0x14: // inc_d();
1658  case 0x15: // dec_d();
1659  case 0x16: // ld_d_byte();
1660  case 0x17: // rla();
1661  case 0x18: // jr();
1662  case 0x1a: // ld_a_xde();
1663  case 0x1b: // dec_de();
1664  case 0x1c: // inc_e();
1665  case 0x1d: // dec_e();
1666  case 0x1e: // ld_e_byte();
1667  case 0x1f: // rra();
1668  case 0x20: // jr_nz();
1669  case 0x27: // daa();
1670  case 0x28: // jr_z();
1671  case 0x2f: // cpl();
1672  case 0x30: // jr_nc();
1673  case 0x31: // ld_sp_word();
1674  case 0x32: // ld_xbyte_a();
1675  case 0x33: // inc_sp();
1676  case 0x37: // scf();
1677  case 0x38: // jr_c();
1678  case 0x3a: // ld_a_xbyte();
1679  case 0x3b: // dec_sp();
1680  case 0x3c: // inc_a();
1681  case 0x3d: // dec_a();
1682  case 0x3e: // ld_a_byte();
1683  case 0x3f: // ccf();
1684 
1685  case 0x40: // ld_b_b();
1686  case 0x41: // ld_b_c();
1687  case 0x42: // ld_b_d();
1688  case 0x43: // ld_b_e();
1689  case 0x47: // ld_b_a();
1690  case 0x48: // ld_c_b();
1691  case 0x49: // ld_c_c();
1692  case 0x4a: // ld_c_d();
1693  case 0x4b: // ld_c_e();
1694  case 0x4f: // ld_c_a();
1695  case 0x50: // ld_d_b();
1696  case 0x51: // ld_d_c();
1697  case 0x52: // ld_d_d();
1698  case 0x53: // ld_d_e();
1699  case 0x57: // ld_d_a();
1700  case 0x58: // ld_e_b();
1701  case 0x59: // ld_e_c();
1702  case 0x5a: // ld_e_d();
1703  case 0x5b: // ld_e_e();
1704  case 0x5f: // ld_e_a();
1705  case 0x64: // ld_ixh_ixh(); == nop
1706  case 0x6d: // ld_ixl_ixl(); == nop
1707  case 0x76: // halt();
1708  case 0x78: // ld_a_b();
1709  case 0x79: // ld_a_c();
1710  case 0x7a: // ld_a_d();
1711  case 0x7b: // ld_a_e();
1712  case 0x7f: // ld_a_a();
1713 
1714  case 0x80: // add_a_b();
1715  case 0x81: // add_a_c();
1716  case 0x82: // add_a_d();
1717  case 0x83: // add_a_e();
1718  case 0x87: // add_a_a();
1719  case 0x88: // adc_a_b();
1720  case 0x89: // adc_a_c();
1721  case 0x8a: // adc_a_d();
1722  case 0x8b: // adc_a_e();
1723  case 0x8f: // adc_a_a();
1724  case 0x90: // sub_b();
1725  case 0x91: // sub_c();
1726  case 0x92: // sub_d();
1727  case 0x93: // sub_e();
1728  case 0x97: // sub_a();
1729  case 0x98: // sbc_a_b();
1730  case 0x99: // sbc_a_c();
1731  case 0x9a: // sbc_a_d();
1732  case 0x9b: // sbc_a_e();
1733  case 0x9f: // sbc_a_a();
1734  case 0xa0: // and_b();
1735  case 0xa1: // and_c();
1736  case 0xa2: // and_d();
1737  case 0xa3: // and_e();
1738  case 0xa7: // and_a();
1739  case 0xa8: // xor_b();
1740  case 0xa9: // xor_c();
1741  case 0xaa: // xor_d();
1742  case 0xab: // xor_e();
1743  case 0xaf: // xor_a();
1744  case 0xb0: // or_b();
1745  case 0xb1: // or_c();
1746  case 0xb2: // or_d();
1747  case 0xb3: // or_e();
1748  case 0xb7: // or_a();
1749  case 0xb8: // cp_b();
1750  case 0xb9: // cp_c();
1751  case 0xba: // cp_d();
1752  case 0xbb: // cp_e();
1753  case 0xbf: // cp_a();
1754 
1755  case 0xc0: // ret_nz();
1756  case 0xc1: // pop_bc();
1757  case 0xc2: // jp_nz();
1758  case 0xc3: // jp();
1759  case 0xc4: // call_nz();
1760  case 0xc5: // push_bc();
1761  case 0xc6: // add_a_byte();
1762  case 0xc7: // rst_00();
1763  case 0xc8: // ret_z();
1764  case 0xc9: // ret();
1765  case 0xca: // jp_z();
1766  case 0xcc: // call_z();
1767  case 0xcd: // call();
1768  case 0xce: // adc_a_byte();
1769  case 0xcf: // rst_08();
1770  case 0xd0: // ret_nc();
1771  case 0xd1: // pop_de();
1772  case 0xd2: // jp_nc();
1773  case 0xd3: // out_byte_a();
1774  case 0xd4: // call_nc();
1775  case 0xd5: // push_de();
1776  case 0xd6: // sub_byte();
1777  case 0xd7: // rst_10();
1778  case 0xd8: // ret_c();
1779  case 0xd9: // exx();
1780  case 0xda: // jp_c();
1781  case 0xdb: // in_a_byte();
1782  case 0xdc: // call_c();
1783  case 0xde: // sbc_a_byte();
1784  case 0xdf: // rst_18();
1785  case 0xe0: // ret_po();
1786  case 0xe2: // jp_po();
1787  case 0xe4: // call_po();
1788  case 0xe6: // and_byte();
1789  case 0xe7: // rst_20();
1790  case 0xe8: // ret_pe();
1791  case 0xea: // jp_pe();
1792  case 0xeb: // ex_de_hl();
1793  case 0xec: // call_pe();
1794  case 0xed: // ed();
1795  case 0xee: // xor_byte();
1796  case 0xef: // rst_28();
1797  case 0xf0: // ret_p();
1798  case 0xf1: // pop_af();
1799  case 0xf2: // jp_p();
1800  case 0xf3: // di();
1801  case 0xf4: // call_p();
1802  case 0xf5: // push_af();
1803  case 0xf6: // or_byte();
1804  case 0xf7: // rst_30();
1805  case 0xf8: // ret_m();
1806  case 0xfa: // jp_m();
1807  case 0xfb: // ei();
1808  case 0xfc: // call_m();
1809  case 0xfe: // cp_byte();
1810  case 0xff: // rst_38();
1811  if /*constexpr*/ (T::IS_R800) {
1812  II ii = nop();
1813  ii.cycles += T::CC_DD;
1814  NEXT;
1815  } else {
1816  T::add(T::CC_DD);
1817  #ifdef USE_COMPUTED_GOTO
1818  goto *(opcodeTable[opcodeDD]);
1819  #else
1820  opcodeMain = opcodeDD;
1821  goto switchopcode;
1822  #endif
1823  }
1824 
1825  case 0x09: { II ii = add_SS_TT<IX,BC,T::CC_DD>(); NEXT; }
1826  case 0x19: { II ii = add_SS_TT<IX,DE,T::CC_DD>(); NEXT; }
1827  case 0x29: { II ii = add_SS_SS<IX ,T::CC_DD>(); NEXT; }
1828  case 0x39: { II ii = add_SS_TT<IX,SP,T::CC_DD>(); NEXT; }
1829  case 0x21: { II ii = ld_SS_word<IX,T::CC_DD>(); NEXT; }
1830  case 0x22: { II ii = ld_xword_SS<IX,T::CC_DD>(); NEXT; }
1831  case 0x2a: { II ii = ld_SS_xword<IX,T::CC_DD>(); NEXT; }
1832  case 0x23: { II ii = inc_SS<IX,T::CC_DD>(); NEXT; }
1833  case 0x2b: { II ii = dec_SS<IX,T::CC_DD>(); NEXT; }
1834  case 0x24: { II ii = inc_R<IXH,T::CC_DD>(); NEXT; }
1835  case 0x2c: { II ii = inc_R<IXL,T::CC_DD>(); NEXT; }
1836  case 0x25: { II ii = dec_R<IXH,T::CC_DD>(); NEXT; }
1837  case 0x2d: { II ii = dec_R<IXL,T::CC_DD>(); NEXT; }
1838  case 0x26: { II ii = ld_R_byte<IXH,T::CC_DD>(); NEXT; }
1839  case 0x2e: { II ii = ld_R_byte<IXL,T::CC_DD>(); NEXT; }
1840  case 0x34: { II ii = inc_xix<IX>(); NEXT; }
1841  case 0x35: { II ii = dec_xix<IX>(); NEXT; }
1842  case 0x36: { II ii = ld_xix_byte<IX>(); NEXT; }
1843 
1844  case 0x44: { II ii = ld_R_R<B,IXH,T::CC_DD>(); NEXT; }
1845  case 0x45: { II ii = ld_R_R<B,IXL,T::CC_DD>(); NEXT; }
1846  case 0x4c: { II ii = ld_R_R<C,IXH,T::CC_DD>(); NEXT; }
1847  case 0x4d: { II ii = ld_R_R<C,IXL,T::CC_DD>(); NEXT; }
1848  case 0x54: { II ii = ld_R_R<D,IXH,T::CC_DD>(); NEXT; }
1849  case 0x55: { II ii = ld_R_R<D,IXL,T::CC_DD>(); NEXT; }
1850  case 0x5c: { II ii = ld_R_R<E,IXH,T::CC_DD>(); NEXT; }
1851  case 0x5d: { II ii = ld_R_R<E,IXL,T::CC_DD>(); NEXT; }
1852  case 0x7c: { II ii = ld_R_R<A,IXH,T::CC_DD>(); NEXT; }
1853  case 0x7d: { II ii = ld_R_R<A,IXL,T::CC_DD>(); NEXT; }
1854  case 0x60: { II ii = ld_R_R<IXH,B,T::CC_DD>(); NEXT; }
1855  case 0x61: { II ii = ld_R_R<IXH,C,T::CC_DD>(); NEXT; }
1856  case 0x62: { II ii = ld_R_R<IXH,D,T::CC_DD>(); NEXT; }
1857  case 0x63: { II ii = ld_R_R<IXH,E,T::CC_DD>(); NEXT; }
1858  case 0x65: { II ii = ld_R_R<IXH,IXL,T::CC_DD>(); NEXT; }
1859  case 0x67: { II ii = ld_R_R<IXH,A,T::CC_DD>(); NEXT; }
1860  case 0x68: { II ii = ld_R_R<IXL,B,T::CC_DD>(); NEXT; }
1861  case 0x69: { II ii = ld_R_R<IXL,C,T::CC_DD>(); NEXT; }
1862  case 0x6a: { II ii = ld_R_R<IXL,D,T::CC_DD>(); NEXT; }
1863  case 0x6b: { II ii = ld_R_R<IXL,E,T::CC_DD>(); NEXT; }
1864  case 0x6c: { II ii = ld_R_R<IXL,IXH,T::CC_DD>(); NEXT; }
1865  case 0x6f: { II ii = ld_R_R<IXL,A,T::CC_DD>(); NEXT; }
1866  case 0x70: { II ii = ld_xix_R<IX,B>(); NEXT; }
1867  case 0x71: { II ii = ld_xix_R<IX,C>(); NEXT; }
1868  case 0x72: { II ii = ld_xix_R<IX,D>(); NEXT; }
1869  case 0x73: { II ii = ld_xix_R<IX,E>(); NEXT; }
1870  case 0x74: { II ii = ld_xix_R<IX,H>(); NEXT; }
1871  case 0x75: { II ii = ld_xix_R<IX,L>(); NEXT; }
1872  case 0x77: { II ii = ld_xix_R<IX,A>(); NEXT; }
1873  case 0x46: { II ii = ld_R_xix<B,IX>(); NEXT; }
1874  case 0x4e: { II ii = ld_R_xix<C,IX>(); NEXT; }
1875  case 0x56: { II ii = ld_R_xix<D,IX>(); NEXT; }
1876  case 0x5e: { II ii = ld_R_xix<E,IX>(); NEXT; }
1877  case 0x66: { II ii = ld_R_xix<H,IX>(); NEXT; }
1878  case 0x6e: { II ii = ld_R_xix<L,IX>(); NEXT; }
1879  case 0x7e: { II ii = ld_R_xix<A,IX>(); NEXT; }
1880 
1881  case 0x84: { II ii = add_a_R<IXH,T::CC_DD>(); NEXT; }
1882  case 0x85: { II ii = add_a_R<IXL,T::CC_DD>(); NEXT; }
1883  case 0x86: { II ii = add_a_xix<IX>(); NEXT; }
1884  case 0x8c: { II ii = adc_a_R<IXH,T::CC_DD>(); NEXT; }
1885  case 0x8d: { II ii = adc_a_R<IXL,T::CC_DD>(); NEXT; }
1886  case 0x8e: { II ii = adc_a_xix<IX>(); NEXT; }
1887  case 0x94: { II ii = sub_R<IXH,T::CC_DD>(); NEXT; }
1888  case 0x95: { II ii = sub_R<IXL,T::CC_DD>(); NEXT; }
1889  case 0x96: { II ii = sub_xix<IX>(); NEXT; }
1890  case 0x9c: { II ii = sbc_a_R<IXH,T::CC_DD>(); NEXT; }
1891  case 0x9d: { II ii = sbc_a_R<IXL,T::CC_DD>(); NEXT; }
1892  case 0x9e: { II ii = sbc_a_xix<IX>(); NEXT; }
1893  case 0xa4: { II ii = and_R<IXH,T::CC_DD>(); NEXT; }
1894  case 0xa5: { II ii = and_R<IXL,T::CC_DD>(); NEXT; }
1895  case 0xa6: { II ii = and_xix<IX>(); NEXT; }
1896  case 0xac: { II ii = xor_R<IXH,T::CC_DD>(); NEXT; }
1897  case 0xad: { II ii = xor_R<IXL,T::CC_DD>(); NEXT; }
1898  case 0xae: { II ii = xor_xix<IX>(); NEXT; }
1899  case 0xb4: { II ii = or_R<IXH,T::CC_DD>(); NEXT; }
1900  case 0xb5: { II ii = or_R<IXL,T::CC_DD>(); NEXT; }
1901  case 0xb6: { II ii = or_xix<IX>(); NEXT; }
1902  case 0xbc: { II ii = cp_R<IXH,T::CC_DD>(); NEXT; }
1903  case 0xbd: { II ii = cp_R<IXL,T::CC_DD>(); NEXT; }
1904  case 0xbe: { II ii = cp_xix<IX>(); NEXT; }
1905 
1906  case 0xe1: { II ii = pop_SS <IX,T::CC_DD>(); NEXT; }
1907  case 0xe5: { II ii = push_SS<IX,T::CC_DD>(); NEXT; }
1908  case 0xe3: { II ii = ex_xsp_SS<IX,T::CC_DD>(); NEXT; }
1909  case 0xe9: { II ii = jp_SS<IX,T::CC_DD>(); NEXT; }
1910  case 0xf9: { II ii = ld_sp_SS<IX,T::CC_DD>(); NEXT; }
1911  case 0xcb: ixy = getIX(); goto xx_cb;
1912  case 0xdd: T::add(T::CC_DD); goto opDD_2;
1913  case 0xfd: T::add(T::CC_DD); goto opFD_2;
1914  default: UNREACHABLE; return;
1915  }
1916 }
1917 opFD_2:
1918 CASE(FD) {
1919  setPC(getPC() + 1); // M1 cycle at this point
1920  byte opcodeFD = RDMEM_OPCODE<0>(T::CC_DD + T::CC_MAIN);
1921  incR(1);
1922  switch (opcodeFD) {
1923  case 0x00: // nop();
1924  case 0x01: // ld_bc_word();
1925  case 0x02: // ld_xbc_a();
1926  case 0x03: // inc_bc();
1927  case 0x04: // inc_b();
1928  case 0x05: // dec_b();
1929  case 0x06: // ld_b_byte();
1930  case 0x07: // rlca();
1931  case 0x08: // ex_af_af();
1932  case 0x0a: // ld_a_xbc();
1933  case 0x0b: // dec_bc();
1934  case 0x0c: // inc_c();
1935  case 0x0d: // dec_c();
1936  case 0x0e: // ld_c_byte();
1937  case 0x0f: // rrca();
1938  case 0x10: // djnz();
1939  case 0x11: // ld_de_word();
1940  case 0x12: // ld_xde_a();
1941  case 0x13: // inc_de();
1942  case 0x14: // inc_d();
1943  case 0x15: // dec_d();
1944  case 0x16: // ld_d_byte();
1945  case 0x17: // rla();
1946  case 0x18: // jr();
1947  case 0x1a: // ld_a_xde();
1948  case 0x1b: // dec_de();
1949  case 0x1c: // inc_e();
1950  case 0x1d: // dec_e();
1951  case 0x1e: // ld_e_byte();
1952  case 0x1f: // rra();
1953  case 0x20: // jr_nz();
1954  case 0x27: // daa();
1955  case 0x28: // jr_z();
1956  case 0x2f: // cpl();
1957  case 0x30: // jr_nc();
1958  case 0x31: // ld_sp_word();
1959  case 0x32: // ld_xbyte_a();
1960  case 0x33: // inc_sp();
1961  case 0x37: // scf();
1962  case 0x38: // jr_c();
1963  case 0x3a: // ld_a_xbyte();
1964  case 0x3b: // dec_sp();
1965  case 0x3c: // inc_a();
1966  case 0x3d: // dec_a();
1967  case 0x3e: // ld_a_byte();
1968  case 0x3f: // ccf();
1969 
1970  case 0x40: // ld_b_b();
1971  case 0x41: // ld_b_c();
1972  case 0x42: // ld_b_d();
1973  case 0x43: // ld_b_e();
1974  case 0x47: // ld_b_a();
1975  case 0x48: // ld_c_b();
1976  case 0x49: // ld_c_c();
1977  case 0x4a: // ld_c_d();
1978  case 0x4b: // ld_c_e();
1979  case 0x4f: // ld_c_a();
1980  case 0x50: // ld_d_b();
1981  case 0x51: // ld_d_c();
1982  case 0x52: // ld_d_d();
1983  case 0x53: // ld_d_e();
1984  case 0x57: // ld_d_a();
1985  case 0x58: // ld_e_b();
1986  case 0x59: // ld_e_c();
1987  case 0x5a: // ld_e_d();
1988  case 0x5b: // ld_e_e();
1989  case 0x5f: // ld_e_a();
1990  case 0x64: // ld_ixh_ixh(); == nop
1991  case 0x6d: // ld_ixl_ixl(); == nop
1992  case 0x76: // halt();
1993  case 0x78: // ld_a_b();
1994  case 0x79: // ld_a_c();
1995  case 0x7a: // ld_a_d();
1996  case 0x7b: // ld_a_e();
1997  case 0x7f: // ld_a_a();
1998 
1999  case 0x80: // add_a_b();
2000  case 0x81: // add_a_c();
2001  case 0x82: // add_a_d();
2002  case 0x83: // add_a_e();
2003  case 0x87: // add_a_a();
2004  case 0x88: // adc_a_b();
2005  case 0x89: // adc_a_c();
2006  case 0x8a: // adc_a_d();
2007  case 0x8b: // adc_a_e();
2008  case 0x8f: // adc_a_a();
2009  case 0x90: // sub_b();
2010  case 0x91: // sub_c();
2011  case 0x92: // sub_d();
2012  case 0x93: // sub_e();
2013  case 0x97: // sub_a();
2014  case 0x98: // sbc_a_b();
2015  case 0x99: // sbc_a_c();
2016  case 0x9a: // sbc_a_d();
2017  case 0x9b: // sbc_a_e();
2018  case 0x9f: // sbc_a_a();
2019  case 0xa0: // and_b();
2020  case 0xa1: // and_c();
2021  case 0xa2: // and_d();
2022  case 0xa3: // and_e();
2023  case 0xa7: // and_a();
2024  case 0xa8: // xor_b();
2025  case 0xa9: // xor_c();
2026  case 0xaa: // xor_d();
2027  case 0xab: // xor_e();
2028  case 0xaf: // xor_a();
2029  case 0xb0: // or_b();
2030  case 0xb1: // or_c();
2031  case 0xb2: // or_d();
2032  case 0xb3: // or_e();
2033  case 0xb7: // or_a();
2034  case 0xb8: // cp_b();
2035  case 0xb9: // cp_c();
2036  case 0xba: // cp_d();
2037  case 0xbb: // cp_e();
2038  case 0xbf: // cp_a();
2039 
2040  case 0xc0: // ret_nz();
2041  case 0xc1: // pop_bc();
2042  case 0xc2: // jp_nz();
2043  case 0xc3: // jp();
2044  case 0xc4: // call_nz();
2045  case 0xc5: // push_bc();
2046  case 0xc6: // add_a_byte();
2047  case 0xc7: // rst_00();
2048  case 0xc8: // ret_z();
2049  case 0xc9: // ret();
2050  case 0xca: // jp_z();
2051  case 0xcc: // call_z();
2052  case 0xcd: // call();
2053  case 0xce: // adc_a_byte();
2054  case 0xcf: // rst_08();
2055  case 0xd0: // ret_nc();
2056  case 0xd1: // pop_de();
2057  case 0xd2: // jp_nc();
2058  case 0xd3: // out_byte_a();
2059  case 0xd4: // call_nc();
2060  case 0xd5: // push_de();
2061  case 0xd6: // sub_byte();
2062  case 0xd7: // rst_10();
2063  case 0xd8: // ret_c();
2064  case 0xd9: // exx();
2065  case 0xda: // jp_c();
2066  case 0xdb: // in_a_byte();
2067  case 0xdc: // call_c();
2068  case 0xde: // sbc_a_byte();
2069  case 0xdf: // rst_18();
2070  case 0xe0: // ret_po();
2071  case 0xe2: // jp_po();
2072  case 0xe4: // call_po();
2073  case 0xe6: // and_byte();
2074  case 0xe7: // rst_20();
2075  case 0xe8: // ret_pe();
2076  case 0xea: // jp_pe();
2077  case 0xeb: // ex_de_hl();
2078  case 0xec: // call_pe();
2079  case 0xed: // ed();
2080  case 0xee: // xor_byte();
2081  case 0xef: // rst_28();
2082  case 0xf0: // ret_p();
2083  case 0xf1: // pop_af();
2084  case 0xf2: // jp_p();
2085  case 0xf3: // di();
2086  case 0xf4: // call_p();
2087  case 0xf5: // push_af();
2088  case 0xf6: // or_byte();
2089  case 0xf7: // rst_30();
2090  case 0xf8: // ret_m();
2091  case 0xfa: // jp_m();
2092  case 0xfb: // ei();
2093  case 0xfc: // call_m();
2094  case 0xfe: // cp_byte();
2095  case 0xff: // rst_38();
2096  if constexpr (T::IS_R800) {
2097  II ii = nop();
2098  ii.cycles += T::CC_DD;
2099  NEXT;
2100  } else {
2101  T::add(T::CC_DD);
2102  #ifdef USE_COMPUTED_GOTO
2103  goto *(opcodeTable[opcodeFD]);
2104  #else
2105  opcodeMain = opcodeFD;
2106  goto switchopcode;
2107  #endif
2108  }
2109 
2110  case 0x09: { II ii = add_SS_TT<IY,BC,T::CC_DD>(); NEXT; }
2111  case 0x19: { II ii = add_SS_TT<IY,DE,T::CC_DD>(); NEXT; }
2112  case 0x29: { II ii = add_SS_SS<IY ,T::CC_DD>(); NEXT; }
2113  case 0x39: { II ii = add_SS_TT<IY,SP,T::CC_DD>(); NEXT; }
2114  case 0x21: { II ii = ld_SS_word<IY,T::CC_DD>(); NEXT; }
2115  case 0x22: { II ii = ld_xword_SS<IY,T::CC_DD>(); NEXT; }
2116  case 0x2a: { II ii = ld_SS_xword<IY,T::CC_DD>(); NEXT; }
2117  case 0x23: { II ii = inc_SS<IY,T::CC_DD>(); NEXT; }
2118  case 0x2b: { II ii = dec_SS<IY,T::CC_DD>(); NEXT; }
2119  case 0x24: { II ii = inc_R<IYH,T::CC_DD>(); NEXT; }
2120  case 0x2c: { II ii = inc_R<IYL,T::CC_DD>(); NEXT; }
2121  case 0x25: { II ii = dec_R<IYH,T::CC_DD>(); NEXT; }
2122  case 0x2d: { II ii = dec_R<IYL,T::CC_DD>(); NEXT; }
2123  case 0x26: { II ii = ld_R_byte<IYH,T::CC_DD>(); NEXT; }
2124  case 0x2e: { II ii = ld_R_byte<IYL,T::CC_DD>(); NEXT; }
2125  case 0x34: { II ii = inc_xix<IY>(); NEXT; }
2126  case 0x35: { II ii = dec_xix<IY>(); NEXT; }
2127  case 0x36: { II ii = ld_xix_byte<IY>(); NEXT; }
2128 
2129  case 0x44: { II ii = ld_R_R<B,IYH,T::CC_DD>(); NEXT; }
2130  case 0x45: { II ii = ld_R_R<B,IYL,T::CC_DD>(); NEXT; }
2131  case 0x4c: { II ii = ld_R_R<C,IYH,T::CC_DD>(); NEXT; }
2132  case 0x4d: { II ii = ld_R_R<C,IYL,T::CC_DD>(); NEXT; }
2133  case 0x54: { II ii = ld_R_R<D,IYH,T::CC_DD>(); NEXT; }
2134  case 0x55: { II ii = ld_R_R<D,IYL,T::CC_DD>(); NEXT; }
2135  case 0x5c: { II ii = ld_R_R<E,IYH,T::CC_DD>(); NEXT; }
2136  case 0x5d: { II ii = ld_R_R<E,IYL,T::CC_DD>(); NEXT; }
2137  case 0x7c: { II ii = ld_R_R<A,IYH,T::CC_DD>(); NEXT; }
2138  case 0x7d: { II ii = ld_R_R<A,IYL,T::CC_DD>(); NEXT; }
2139  case 0x60: { II ii = ld_R_R<IYH,B,T::CC_DD>(); NEXT; }
2140  case 0x61: { II ii = ld_R_R<IYH,C,T::CC_DD>(); NEXT; }
2141  case 0x62: { II ii = ld_R_R<IYH,D,T::CC_DD>(); NEXT; }
2142  case 0x63: { II ii = ld_R_R<IYH,E,T::CC_DD>(); NEXT; }
2143  case 0x65: { II ii = ld_R_R<IYH,IYL,T::CC_DD>(); NEXT; }
2144  case 0x67: { II ii = ld_R_R<IYH,A,T::CC_DD>(); NEXT; }
2145  case 0x68: { II ii = ld_R_R<IYL,B,T::CC_DD>(); NEXT; }
2146  case 0x69: { II ii = ld_R_R<IYL,C,T::CC_DD>(); NEXT; }
2147  case 0x6a: { II ii = ld_R_R<IYL,D,T::CC_DD>(); NEXT; }
2148  case 0x6b: { II ii = ld_R_R<IYL,E,T::CC_DD>(); NEXT; }
2149  case 0x6c: { II ii = ld_R_R<IYL,IYH,T::CC_DD>(); NEXT; }
2150  case 0x6f: { II ii = ld_R_R<IYL,A,T::CC_DD>(); NEXT; }
2151  case 0x70: { II ii = ld_xix_R<IY,B>(); NEXT; }
2152  case 0x71: { II ii = ld_xix_R<IY,C>(); NEXT; }
2153  case 0x72: { II ii = ld_xix_R<IY,D>(); NEXT; }
2154  case 0x73: { II ii = ld_xix_R<IY,E>(); NEXT; }
2155  case 0x74: { II ii = ld_xix_R<IY,H>(); NEXT; }
2156  case 0x75: { II ii = ld_xix_R<IY,L>(); NEXT; }
2157  case 0x77: { II ii = ld_xix_R<IY,A>(); NEXT; }
2158  case 0x46: { II ii = ld_R_xix<B,IY>(); NEXT; }
2159  case 0x4e: { II ii = ld_R_xix<C,IY>(); NEXT; }
2160  case 0x56: { II ii = ld_R_xix<D,IY>(); NEXT; }
2161  case 0x5e: { II ii = ld_R_xix<E,IY>(); NEXT; }
2162  case 0x66: { II ii = ld_R_xix<H,IY>(); NEXT; }
2163  case 0x6e: { II ii = ld_R_xix<L,IY>(); NEXT; }
2164  case 0x7e: { II ii = ld_R_xix<A,IY>(); NEXT; }
2165 
2166  case 0x84: { II ii = add_a_R<IYH,T::CC_DD>(); NEXT; }
2167  case 0x85: { II ii = add_a_R<IYL,T::CC_DD>(); NEXT; }
2168  case 0x86: { II ii = add_a_xix<IY>(); NEXT; }
2169  case 0x8c: { II ii = adc_a_R<IYH,T::CC_DD>(); NEXT; }
2170  case 0x8d: { II ii = adc_a_R<IYL,T::CC_DD>(); NEXT; }
2171  case 0x8e: { II ii = adc_a_xix<IY>(); NEXT; }
2172  case 0x94: { II ii = sub_R<IYH,T::CC_DD>(); NEXT; }
2173  case 0x95: { II ii = sub_R<IYL,T::CC_DD>(); NEXT; }
2174  case 0x96: { II ii = sub_xix<IY>(); NEXT; }
2175  case 0x9c: { II ii = sbc_a_R<IYH,T::CC_DD>(); NEXT; }
2176  case 0x9d: { II ii = sbc_a_R<IYL,T::CC_DD>(); NEXT; }
2177  case 0x9e: { II ii = sbc_a_xix<IY>(); NEXT; }
2178  case 0xa4: { II ii = and_R<IYH,T::CC_DD>(); NEXT; }
2179  case 0xa5: { II ii = and_R<IYL,T::CC_DD>(); NEXT; }
2180  case 0xa6: { II ii = and_xix<IY>(); NEXT; }
2181  case 0xac: { II ii = xor_R<IYH,T::CC_DD>(); NEXT; }
2182  case 0xad: { II ii = xor_R<IYL,T::CC_DD>(); NEXT; }
2183  case 0xae: { II ii = xor_xix<IY>(); NEXT; }
2184  case 0xb4: { II ii = or_R<IYH,T::CC_DD>(); NEXT; }
2185  case 0xb5: { II ii = or_R<IYL,T::CC_DD>(); NEXT; }
2186  case 0xb6: { II ii = or_xix<IY>(); NEXT; }
2187  case 0xbc: { II ii = cp_R<IYH,T::CC_DD>(); NEXT; }
2188  case 0xbd: { II ii = cp_R<IYL,T::CC_DD>(); NEXT; }
2189  case 0xbe: { II ii = cp_xix<IY>(); NEXT; }
2190 
2191  case 0xe1: { II ii = pop_SS <IY,T::CC_DD>(); NEXT; }
2192  case 0xe5: { II ii = push_SS<IY,T::CC_DD>(); NEXT; }
2193  case 0xe3: { II ii = ex_xsp_SS<IY,T::CC_DD>(); NEXT; }
2194  case 0xe9: { II ii = jp_SS<IY,T::CC_DD>(); NEXT; }
2195  case 0xf9: { II ii = ld_sp_SS<IY,T::CC_DD>(); NEXT; }
2196  case 0xcb: ixy = getIY(); goto xx_cb;
2197  case 0xdd: T::add(T::CC_DD); goto opDD_2;
2198  case 0xfd: T::add(T::CC_DD); goto opFD_2;
2199  default: UNREACHABLE; return;
2200  }
2201 }
2202 #ifndef USE_COMPUTED_GOTO
2203  default: UNREACHABLE; return;
2204 }
2205 #endif
2206 
2207 xx_cb: {
2208  unsigned tmp = RD_WORD_PC<1>(T::CC_DD + T::CC_DD_CB);
2209  int8_t ofst = tmp & 0xFF;
2210  unsigned addr = (ixy + ofst) & 0xFFFF;
2211  byte xxcb_opcode = tmp >> 8;
2212  switch (xxcb_opcode) {
2213  case 0x00: { II ii = rlc_xix_R<B>(addr); NEXT; }
2214  case 0x01: { II ii = rlc_xix_R<C>(addr); NEXT; }
2215  case 0x02: { II ii = rlc_xix_R<D>(addr); NEXT; }
2216  case 0x03: { II ii = rlc_xix_R<E>(addr); NEXT; }
2217  case 0x04: { II ii = rlc_xix_R<H>(addr); NEXT; }
2218  case 0x05: { II ii = rlc_xix_R<L>(addr); NEXT; }
2219  case 0x06: { II ii = rlc_xix_R<DUMMY>(addr); NEXT; }
2220  case 0x07: { II ii = rlc_xix_R<A>(addr); NEXT; }
2221  case 0x08: { II ii = rrc_xix_R<B>(addr); NEXT; }
2222  case 0x09: { II ii = rrc_xix_R<C>(addr); NEXT; }
2223  case 0x0a: { II ii = rrc_xix_R<D>(addr); NEXT; }
2224  case 0x0b: { II ii = rrc_xix_R<E>(addr); NEXT; }
2225  case 0x0c: { II ii = rrc_xix_R<H>(addr); NEXT; }
2226  case 0x0d: { II ii = rrc_xix_R<L>(addr); NEXT; }
2227  case 0x0e: { II ii = rrc_xix_R<DUMMY>(addr); NEXT; }
2228  case 0x0f: { II ii = rrc_xix_R<A>(addr); NEXT; }
2229  case 0x10: { II ii = rl_xix_R<B>(addr); NEXT; }
2230  case 0x11: { II ii = rl_xix_R<C>(addr); NEXT; }
2231  case 0x12: { II ii = rl_xix_R<D>(addr); NEXT; }
2232  case 0x13: { II ii = rl_xix_R<E>(addr); NEXT; }
2233  case 0x14: { II ii = rl_xix_R<H>(addr); NEXT; }
2234  case 0x15: { II ii = rl_xix_R<L>(addr); NEXT; }
2235  case 0x16: { II ii = rl_xix_R<DUMMY>(addr); NEXT; }
2236  case 0x17: { II ii = rl_xix_R<A>(addr); NEXT; }
2237  case 0x18: { II ii = rr_xix_R<B>(addr); NEXT; }
2238  case 0x19: { II ii = rr_xix_R<C>(addr); NEXT; }
2239  case 0x1a: { II ii = rr_xix_R<D>(addr); NEXT; }
2240  case 0x1b: { II ii = rr_xix_R<E>(addr); NEXT; }
2241  case 0x1c: { II ii = rr_xix_R<H>(addr); NEXT; }
2242  case 0x1d: { II ii = rr_xix_R<L>(addr); NEXT; }
2243  case 0x1e: { II ii = rr_xix_R<DUMMY>(addr); NEXT; }
2244  case 0x1f: { II ii = rr_xix_R<A>(addr); NEXT; }
2245  case 0x20: { II ii = sla_xix_R<B>(addr); NEXT; }
2246  case 0x21: { II ii = sla_xix_R<C>(addr); NEXT; }
2247  case 0x22: { II ii = sla_xix_R<D>(addr); NEXT; }
2248  case 0x23: { II ii = sla_xix_R<E>(addr); NEXT; }
2249  case 0x24: { II ii = sla_xix_R<H>(addr); NEXT; }
2250  case 0x25: { II ii = sla_xix_R<L>(addr); NEXT; }
2251  case 0x26: { II ii = sla_xix_R<DUMMY>(addr); NEXT; }
2252  case 0x27: { II ii = sla_xix_R<A>(addr); NEXT; }
2253  case 0x28: { II ii = sra_xix_R<B>(addr); NEXT; }
2254  case 0x29: { II ii = sra_xix_R<C>(addr); NEXT; }
2255  case 0x2a: { II ii = sra_xix_R<D>(addr); NEXT; }
2256  case 0x2b: { II ii = sra_xix_R<E>(addr); NEXT; }
2257  case 0x2c: { II ii = sra_xix_R<H>(addr); NEXT; }
2258  case 0x2d: { II ii = sra_xix_R<L>(addr); NEXT; }
2259  case 0x2e: { II ii = sra_xix_R<DUMMY>(addr); NEXT; }
2260  case 0x2f: { II ii = sra_xix_R<A>(addr); NEXT; }
2261  case 0x30: { II ii = T::IS_R800 ? sll2() : sll_xix_R<B>(addr); NEXT; }
2262  case 0x31: { II ii = T::IS_R800 ? sll2() : sll_xix_R<C>(addr); NEXT; }
2263  case 0x32: { II ii = T::IS_R800 ? sll2() : sll_xix_R<D>(addr); NEXT; }
2264  case 0x33: { II ii = T::IS_R800 ? sll2() : sll_xix_R<E>(addr); NEXT; }
2265  case 0x34: { II ii = T::IS_R800 ? sll2() : sll_xix_R<H>(addr); NEXT; }
2266  case 0x35: { II ii = T::IS_R800 ? sll2() : sll_xix_R<L>(addr); NEXT; }
2267  case 0x36: { II ii = T::IS_R800 ? sll2() : sll_xix_R<DUMMY>(addr); NEXT; }
2268  case 0x37: { II ii = T::IS_R800 ? sll2() : sll_xix_R<A>(addr); NEXT; }
2269  case 0x38: { II ii = srl_xix_R<B>(addr); NEXT; }
2270  case 0x39: { II ii = srl_xix_R<C>(addr); NEXT; }
2271  case 0x3a: { II ii = srl_xix_R<D>(addr); NEXT; }
2272  case 0x3b: { II ii = srl_xix_R<E>(addr); NEXT; }
2273  case 0x3c: { II ii = srl_xix_R<H>(addr); NEXT; }
2274  case 0x3d: { II ii = srl_xix_R<L>(addr); NEXT; }
2275  case 0x3e: { II ii = srl_xix_R<DUMMY>(addr); NEXT; }
2276  case 0x3f: { II ii = srl_xix_R<A>(addr); NEXT; }
2277 
2278  case 0x40: case 0x41: case 0x42: case 0x43:
2279  case 0x44: case 0x45: case 0x46: case 0x47:
2280  { II ii = bit_N_xix<0>(addr); NEXT; }
2281  case 0x48: case 0x49: case 0x4a: case 0x4b:
2282  case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2283  { II ii = bit_N_xix<1>(addr); NEXT; }
2284  case 0x50: case 0x51: case 0x52: case 0x53:
2285  case 0x54: case 0x55: case 0x56: case 0x57:
2286  { II ii = bit_N_xix<2>(addr); NEXT; }
2287  case 0x58: case 0x59: case 0x5a: case 0x5b:
2288  case 0x5c: case 0x5d: case 0x5e: case 0x5f:
2289  { II ii = bit_N_xix<3>(addr); NEXT; }
2290  case 0x60: case 0x61: case 0x62: case 0x63:
2291  case 0x64: case 0x65: case 0x66: case 0x67:
2292  { II ii = bit_N_xix<4>(addr); NEXT; }
2293  case 0x68: case 0x69: case 0x6a: case 0x6b:
2294  case 0x6c: case 0x6d: case 0x6e: case 0x6f:
2295  { II ii = bit_N_xix<5>(addr); NEXT; }
2296  case 0x70: case 0x71: case 0x72: case 0x73:
2297  case 0x74: case 0x75: case 0x76: case 0x77:
2298  { II ii = bit_N_xix<6>(addr); NEXT; }
2299  case 0x78: case 0x79: case 0x7a: case 0x7b:
2300  case 0x7c: case 0x7d: case 0x7e: case 0x7f:
2301  { II ii = bit_N_xix<7>(addr); NEXT; }
2302 
2303  case 0x80: { II ii = res_N_xix_R<0,B>(addr); NEXT; }
2304  case 0x81: { II ii = res_N_xix_R<0,C>(addr); NEXT; }
2305  case 0x82: { II ii = res_N_xix_R<0,D>(addr); NEXT; }
2306  case 0x83: { II ii = res_N_xix_R<0,E>(addr); NEXT; }
2307  case 0x84: { II ii = res_N_xix_R<0,H>(addr); NEXT; }
2308  case 0x85: { II ii = res_N_xix_R<0,L>(addr); NEXT; }
2309  case 0x87: { II ii = res_N_xix_R<0,A>(addr); NEXT; }
2310  case 0x88: { II ii = res_N_xix_R<1,B>(addr); NEXT; }
2311  case 0x89: { II ii = res_N_xix_R<1,C>(addr); NEXT; }
2312  case 0x8a: { II ii = res_N_xix_R<1,D>(addr); NEXT; }
2313  case 0x8b: { II ii = res_N_xix_R<1,E>(addr); NEXT; }
2314  case 0x8c: { II ii = res_N_xix_R<1,H>(addr); NEXT; }
2315  case 0x8d: { II ii = res_N_xix_R<1,L>(addr); NEXT; }
2316  case 0x8f: { II ii = res_N_xix_R<1,A>(addr); NEXT; }
2317  case 0x90: { II ii = res_N_xix_R<2,B>(addr); NEXT; }
2318  case 0x91: { II ii = res_N_xix_R<2,C>(addr); NEXT; }
2319  case 0x92: { II ii = res_N_xix_R<2,D>(addr); NEXT; }
2320  case 0x93: { II ii = res_N_xix_R<2,E>(addr); NEXT; }
2321  case 0x94: { II ii = res_N_xix_R<2,H>(addr); NEXT; }
2322  case 0x95: { II ii = res_N_xix_R<2,L>(addr); NEXT; }
2323  case 0x97: { II ii = res_N_xix_R<2,A>(addr); NEXT; }
2324  case 0x98: { II ii = res_N_xix_R<3,B>(addr); NEXT; }
2325  case 0x99: { II ii = res_N_xix_R<3,C>(addr); NEXT; }
2326  case 0x9a: { II ii = res_N_xix_R<3,D>(addr); NEXT; }
2327  case 0x9b: { II ii = res_N_xix_R<3,E>(addr); NEXT; }
2328  case 0x9c: { II ii = res_N_xix_R<3,H>(addr); NEXT; }
2329  case 0x9d: { II ii = res_N_xix_R<3,L>(addr); NEXT; }
2330  case 0x9f: { II ii = res_N_xix_R<3,A>(addr); NEXT; }
2331  case 0xa0: { II ii = res_N_xix_R<4,B>(addr); NEXT; }
2332  case 0xa1: { II ii = res_N_xix_R<4,C>(addr); NEXT; }
2333  case 0xa2: { II ii = res_N_xix_R<4,D>(addr); NEXT; }
2334  case 0xa3: { II ii = res_N_xix_R<4,E>(addr); NEXT; }
2335  case 0xa4: { II ii = res_N_xix_R<4,H>(addr); NEXT; }
2336  case 0xa5: { II ii = res_N_xix_R<4,L>(addr); NEXT; }
2337  case 0xa7: { II ii = res_N_xix_R<4,A>(addr); NEXT; }
2338  case 0xa8: { II ii = res_N_xix_R<5,B>(addr); NEXT; }
2339  case 0xa9: { II ii = res_N_xix_R<5,C>(addr); NEXT; }
2340  case 0xaa: { II ii = res_N_xix_R<5,D>(addr); NEXT; }
2341  case 0xab: { II ii = res_N_xix_R<5,E>(addr); NEXT; }
2342  case 0xac: { II ii = res_N_xix_R<5,H>(addr); NEXT; }
2343  case 0xad: { II ii = res_N_xix_R<5,L>(addr); NEXT; }
2344  case 0xaf: { II ii = res_N_xix_R<5,A>(addr); NEXT; }
2345  case 0xb0: { II ii = res_N_xix_R<6,B>(addr); NEXT; }
2346  case 0xb1: { II ii = res_N_xix_R<6,C>(addr); NEXT; }
2347  case 0xb2: { II ii = res_N_xix_R<6,D>(addr); NEXT; }
2348  case 0xb3: { II ii = res_N_xix_R<6,E>(addr); NEXT; }
2349  case 0xb4: { II ii = res_N_xix_R<6,H>(addr); NEXT; }
2350  case 0xb5: { II ii = res_N_xix_R<6,L>(addr); NEXT; }
2351  case 0xb7: { II ii = res_N_xix_R<6,A>(addr); NEXT; }
2352  case 0xb8: { II ii = res_N_xix_R<7,B>(addr); NEXT; }
2353  case 0xb9: { II ii = res_N_xix_R<7,C>(addr); NEXT; }
2354  case 0xba: { II ii = res_N_xix_R<7,D>(addr); NEXT; }
2355  case 0xbb: { II ii = res_N_xix_R<7,E>(addr); NEXT; }
2356  case 0xbc: { II ii = res_N_xix_R<7,H>(addr); NEXT; }
2357  case 0xbd: { II ii = res_N_xix_R<7,L>(addr); NEXT; }
2358  case 0xbf: { II ii = res_N_xix_R<7,A>(addr); NEXT; }
2359  case 0x86: { II ii = res_N_xix_R<0,DUMMY>(addr); NEXT; }
2360  case 0x8e: { II ii = res_N_xix_R<1,DUMMY>(addr); NEXT; }
2361  case 0x96: { II ii = res_N_xix_R<2,DUMMY>(addr); NEXT; }
2362  case 0x9e: { II ii = res_N_xix_R<3,DUMMY>(addr); NEXT; }
2363  case 0xa6: { II ii = res_N_xix_R<4,DUMMY>(addr); NEXT; }
2364  case 0xae: { II ii = res_N_xix_R<5,DUMMY>(addr); NEXT; }
2365  case 0xb6: { II ii = res_N_xix_R<6,DUMMY>(addr); NEXT; }
2366  case 0xbe: { II ii = res_N_xix_R<7,DUMMY>(addr); NEXT; }
2367 
2368  case 0xc0: { II ii = set_N_xix_R<0,B>(addr); NEXT; }
2369  case 0xc1: { II ii = set_N_xix_R<0,C>(addr); NEXT; }
2370  case 0xc2: { II ii = set_N_xix_R<0,D>(addr); NEXT; }
2371  case 0xc3: { II ii = set_N_xix_R<0,E>(addr); NEXT; }
2372  case 0xc4: { II ii = set_N_xix_R<0,H>(addr); NEXT; }
2373  case 0xc5: { II ii = set_N_xix_R<0,L>(addr); NEXT; }
2374  case 0xc7: { II ii = set_N_xix_R<0,A>(addr); NEXT; }
2375  case 0xc8: { II ii = set_N_xix_R<1,B>(addr); NEXT; }
2376  case 0xc9: { II ii = set_N_xix_R<1,C>(addr); NEXT; }
2377  case 0xca: { II ii = set_N_xix_R<1,D>(addr); NEXT; }
2378  case 0xcb: { II ii = set_N_xix_R<1,E>(addr); NEXT; }
2379  case 0xcc: { II ii = set_N_xix_R<1,H>(addr); NEXT; }
2380  case 0xcd: { II ii = set_N_xix_R<1,L>(addr); NEXT; }
2381  case 0xcf: { II ii = set_N_xix_R<1,A>(addr); NEXT; }
2382  case 0xd0: { II ii = set_N_xix_R<2,B>(addr); NEXT; }
2383  case 0xd1: { II ii = set_N_xix_R<2,C>(addr); NEXT; }
2384  case 0xd2: { II ii = set_N_xix_R<2,D>(addr); NEXT; }
2385  case 0xd3: { II ii = set_N_xix_R<2,E>(addr); NEXT; }
2386  case 0xd4: { II ii = set_N_xix_R<2,H>(addr); NEXT; }
2387  case 0xd5: { II ii = set_N_xix_R<2,L>(addr); NEXT; }
2388  case 0xd7: { II ii = set_N_xix_R<2,A>(addr); NEXT; }
2389  case 0xd8: { II ii = set_N_xix_R<3,B>(addr); NEXT; }
2390  case 0xd9: { II ii = set_N_xix_R<3,C>(addr); NEXT; }
2391  case 0xda: { II ii = set_N_xix_R<3,D>(addr); NEXT; }
2392  case 0xdb: { II ii = set_N_xix_R<3,E>(addr); NEXT; }
2393  case 0xdc: { II ii = set_N_xix_R<3,H>(addr); NEXT; }
2394  case 0xdd: { II ii = set_N_xix_R<3,L>(addr); NEXT; }
2395  case 0xdf: { II ii = set_N_xix_R<3,A>(addr); NEXT; }
2396  case 0xe0: { II ii = set_N_xix_R<4,B>(addr); NEXT; }
2397  case 0xe1: { II ii = set_N_xix_R<4,C>(addr); NEXT; }
2398  case 0xe2: { II ii = set_N_xix_R<4,D>(addr); NEXT; }
2399  case 0xe3: { II ii = set_N_xix_R<4,E>(addr); NEXT; }
2400  case 0xe4: { II ii = set_N_xix_R<4,H>(addr); NEXT; }
2401  case 0xe5: { II ii = set_N_xix_R<4,L>(addr); NEXT; }
2402  case 0xe7: { II ii = set_N_xix_R<4,A>(addr); NEXT; }
2403  case 0xe8: { II ii = set_N_xix_R<5,B>(addr); NEXT; }
2404  case 0xe9: { II ii = set_N_xix_R<5,C>(addr); NEXT; }
2405  case 0xea: { II ii = set_N_xix_R<5,D>(addr); NEXT; }
2406  case 0xeb: { II ii = set_N_xix_R<5,E>(addr); NEXT; }
2407  case 0xec: { II ii = set_N_xix_R<5,H>(addr); NEXT; }
2408  case 0xed: { II ii = set_N_xix_R<5,L>(addr); NEXT; }
2409  case 0xef: { II ii = set_N_xix_R<5,A>(addr); NEXT; }
2410  case 0xf0: { II ii = set_N_xix_R<6,B>(addr); NEXT; }
2411  case 0xf1: { II ii = set_N_xix_R<6,C>(addr); NEXT; }
2412  case 0xf2: { II ii = set_N_xix_R<6,D>(addr); NEXT; }
2413  case 0xf3: { II ii = set_N_xix_R<6,E>(addr); NEXT; }
2414  case 0xf4: { II ii = set_N_xix_R<6,H>(addr); NEXT; }
2415  case 0xf5: { II ii = set_N_xix_R<6,L>(addr); NEXT; }
2416  case 0xf7: { II ii = set_N_xix_R<6,A>(addr); NEXT; }
2417  case 0xf8: { II ii = set_N_xix_R<7,B>(addr); NEXT; }
2418  case 0xf9: { II ii = set_N_xix_R<7,C>(addr); NEXT; }
2419  case 0xfa: { II ii = set_N_xix_R<7,D>(addr); NEXT; }
2420  case 0xfb: { II ii = set_N_xix_R<7,E>(addr); NEXT; }
2421  case 0xfc: { II ii = set_N_xix_R<7,H>(addr); NEXT; }
2422  case 0xfd: { II ii = set_N_xix_R<7,L>(addr); NEXT; }
2423  case 0xff: { II ii = set_N_xix_R<7,A>(addr); NEXT; }
2424  case 0xc6: { II ii = set_N_xix_R<0,DUMMY>(addr); NEXT; }
2425  case 0xce: { II ii = set_N_xix_R<1,DUMMY>(addr); NEXT; }
2426  case 0xd6: { II ii = set_N_xix_R<2,DUMMY>(addr); NEXT; }
2427  case 0xde: { II ii = set_N_xix_R<3,DUMMY>(addr); NEXT; }
2428  case 0xe6: { II ii = set_N_xix_R<4,DUMMY>(addr); NEXT; }
2429  case 0xee: { II ii = set_N_xix_R<5,DUMMY>(addr); NEXT; }
2430  case 0xf6: { II ii = set_N_xix_R<6,DUMMY>(addr); NEXT; }
2431  case 0xfe: { II ii = set_N_xix_R<7,DUMMY>(addr); NEXT; }
2432  default: UNREACHABLE;
2433  }
2434  }
2435 }
2436 
2437 template<typename T> inline void CPUCore<T>::cpuTracePre()
2438 {
2439  start_pc = getPC();
2440 }
2441 template<typename T> inline void CPUCore<T>::cpuTracePost()
2442 {
2443  if (unlikely(tracingEnabled)) {
2444  cpuTracePost_slow();
2445  }
2446 }
2447 template<typename T> void CPUCore<T>::cpuTracePost_slow()
2448 {
2449  byte opBuf[4];
2450  string dasmOutput;
2451  dasm(*interface, start_pc, opBuf, dasmOutput, T::getTimeFast());
2452  std::cout << strCat(hex_string<4>(start_pc),
2453  " : ", dasmOutput,
2454  " AF=", hex_string<4>(getAF()),
2455  " BC=", hex_string<4>(getBC()),
2456  " DE=", hex_string<4>(getDE()),
2457  " HL=", hex_string<4>(getHL()),
2458  " IX=", hex_string<4>(getIX()),
2459  " IY=", hex_string<4>(getIY()),
2460  " SP=", hex_string<4>(getSP()),
2461  '\n')
2462  << std::flush;
2463 }
2464 
2465 template<typename T> ExecIRQ CPUCore<T>::getExecIRQ() const
2466 {
2467  if (unlikely(nmiEdge)) return ExecIRQ::NMI;
2468  if (unlikely(IRQStatus && getIFF1() && !prevWasEI())) return ExecIRQ::IRQ;
2469  return ExecIRQ::NONE;
2470 }
2471 
2472 template<typename T> void CPUCore<T>::executeSlow(ExecIRQ execIRQ)
2473 {
2474  if (unlikely(execIRQ == ExecIRQ::NMI)) {
2475  nmiEdge = false;
2476  nmi(); // NMI occurred
2477  } else if (unlikely(execIRQ == ExecIRQ::IRQ)) {
2478  // normal interrupt
2479  if (unlikely(prevWasLDAI())) {
2480  // HACK!!!
2481  // The 'ld a,i' or 'ld a,r' instruction copies the IFF2
2482  // bit to the V flag. Though when the Z80 accepts an
2483  // IRQ directly after this instruction, the V flag is 0
2484  // (instead of the expected value 1). This can probably
2485  // be explained if you look at the pipeline of the Z80.
2486  // But for speed reasons we implement it here as a
2487  // fix-up (a hack) in the IRQ routine. This behaviour
2488  // is actually a bug in the Z80.
2489  // Thanks to n_n for reporting this behaviour. I think
2490  // this was discovered by GuyveR800. Also thanks to
2491  // n_n for writing a test program that demonstrates
2492  // this quirk.
2493  // I also wrote a test program that demonstrates this
2494  // behaviour is the same whether 'ld a,i' is preceded
2495  // by a 'ei' instruction or not (so it's not caused by
2496  // the 'delayed IRQ acceptance of ei').
2497  assert(getF() & V_FLAG);
2498  setF(getF() & ~V_FLAG);
2499  }
2500  IRQAccept.signal();
2501  switch (getIM()) {
2502  case 0: irq0();
2503  break;
2504  case 1: irq1();
2505  break;
2506  case 2: irq2();
2507  break;
2508  default:
2509  UNREACHABLE;
2510  }
2511  } else if (unlikely(getHALT())) {
2512  // in halt mode
2513  incR(T::advanceHalt(T::HALT_STATES, scheduler.getNext()));
2514  setSlowInstructions();
2515  } else {
2516  cpuTracePre();
2517  assert(T::limitReached()); // we want only one instruction
2518  executeInstructions();
2519  endInstruction();
2520 
2521  if constexpr (T::IS_R800) {
2522  if (unlikely(prev2WasCall()) && likely(!prevWasPopRet())) {
2523  // On R800 a CALL or RST instruction not _immediately_
2524  // followed by a (single-byte) POP or RET instruction
2525  // causes an extra cycle in that following instruction.
2526  // No idea why yet. See doc/internal/r800-call.txt
2527  // for more information.
2528  //
2529  // TODO this implementation adds the extra cycle at
2530  // the end of the instruction POP/RET. It is not known
2531  // where in the instruction the real R800 adds this cycle.
2532  T::add(1);
2533  }
2534  }
2535  cpuTracePost();
2536  }
2537 }
2538 
2539 template<typename T> void CPUCore<T>::execute(bool fastForward)
2540 {
2541  // In fast-forward mode, breakpoints, watchpoints or debug condtions
2542  // won't trigger. It is possible we already are in break mode, but
2543  // break is ignored in fast-forward mode.
2544  assert(fastForward || !interface->isBreaked());
2545  if (fastForward) {
2546  interface->setFastForward(true);
2547  }
2548  execute2(fastForward);
2549  interface->setFastForward(false);
2550 }
2551 
2552 template<typename T> void CPUCore<T>::execute2(bool fastForward)
2553 {
2554  // note: Don't use getTimeFast() here, because 'once in a while' we
2555  // need to CPUClock::sync() to avoid overflow.
2556  // Should be done at least once per second (approx). So only
2557  // once in this method is enough.
2558  scheduler.schedule(T::getTime());
2559  setSlowInstructions();
2560 
2561  // Note: we call scheduler _after_ executing the instruction and before
2562  // deciding between executeFast() and executeSlow() (because a
2563  // SyncPoint could set an IRQ and then we must choose executeSlow())
2564  if (fastForward ||
2565  (!interface->anyBreakPoints() && !tracingEnabled)) {
2566  // fast path, no breakpoints, no tracing
2567  do {
2568  if (slowInstructions) {
2569  --slowInstructions;
2570  executeSlow(getExecIRQ());
2571  scheduler.schedule(T::getTimeFast());
2572  } else {
2573  while (slowInstructions == 0) {
2574  T::enableLimit(); // does CPUClock::sync()
2575  if (likely(!T::limitReached())) {
2576  // multiple instructions
2577  executeInstructions();
2578  // note: pipeline only shifted one
2579  // step for multiple instructions
2580  endInstruction();
2581  }
2582  scheduler.schedule(T::getTimeFast());
2583  if (needExitCPULoop()) return;
2584  }
2585  }
2586  } while (!needExitCPULoop());
2587  } else {
2588  do {
2589  if (slowInstructions == 0) {
2590  cpuTracePre();
2591  assert(T::limitReached()); // only one instruction
2592  executeInstructions();
2593  endInstruction();
2594  cpuTracePost();
2595  } else {
2596  --slowInstructions;
2597  executeSlow(getExecIRQ());
2598  }
2599  // Don't use getTimeFast() here, we need a call to
2600  // CPUClock::sync() 'once in a while'. (During a
2601  // reverse fast-forward this wasn't always the case).
2602  scheduler.schedule(T::getTime());
2603 
2604  // Only check for breakpoints when we're not about to jump to an IRQ handler.
2605  //
2606  // This fixes the following problem reported by Grauw:
2607  //
2608  // I found a breakpoints bug: sometimes a breakpoint gets hit twice even
2609  // though the code is executed once. This manifests itself in my profiler
2610  // as an imbalance between section begin- and end-calls.
2611  //
2612  // Turns out this occurs when an interrupt occurs exactly on the line of
2613  // the breakpoint, then the breakpoint gets hit before immediately going
2614  // to the ISR, as well as when returning from the ISR.
2615  //
2616  // The IRQ is handled by the Z80 at the end of an instruction. So it
2617  // should change the PC before the next instruction is fetched and the
2618  // breakpoints should be evaluated during instruction fetch.
2619  //
2620  // I think Grauw's analysis is correct. Though for performance reasons we
2621  // don't emulate the Z80 like that: we don't check for IRQs at the end of
2622  // every instruction. In the openMSX emulation model, we can only enter an
2623  // ISR:
2624  // - (One instruction after) switching from DI to EI mode.
2625  // - After emulating device code. This can be:
2626  // * When the Z80 communicated with the device (IO or memory mapped IO).
2627  // * The device had set a synchronization point.
2628  // In all cases disableLimit() gets called which will cause
2629  // limitReached() to return true (and possibly slowInstructions to be > 0).
2630  // So after most emulated Z80 instructions there can't be a pending IRQ, so
2631  // checking for it is wasteful. Also synchronization points are handled
2632  // between emulated Z80 instructions, that means me must check for pending
2633  // IRQs at the start (instead of end) of an instruction.
2634  //
2635  auto execIRQ = getExecIRQ();
2636  if ((execIRQ == ExecIRQ::NONE) &&
2637  interface->checkBreakPoints(getPC(), motherboard)) {
2638  assert(interface->isBreaked());
2639  break;
2640  }
2641  } while (!needExitCPULoop());
2642  }
2643 }
2644 
2645 template<typename T> template<Reg8 R8> ALWAYS_INLINE byte CPUCore<T>::get8() const {
2646  if constexpr (R8 == A) { return getA(); }
2647  else if constexpr (R8 == F) { return getF(); }
2648  else if constexpr (R8 == B) { return getB(); }
2649  else if constexpr (R8 == C) { return getC(); }
2650  else if constexpr (R8 == D) { return getD(); }
2651  else if constexpr (R8 == E) { return getE(); }
2652  else if constexpr (R8 == H) { return getH(); }
2653  else if constexpr (R8 == L) { return getL(); }
2654  else if constexpr (R8 == IXH) { return getIXh(); }
2655  else if constexpr (R8 == IXL) { return getIXl(); }
2656  else if constexpr (R8 == IYH) { return getIYh(); }
2657  else if constexpr (R8 == IYL) { return getIYl(); }
2658  else if constexpr (R8 == REG_I) { return getI(); }
2659  else if constexpr (R8 == REG_R) { return getR(); }
2660  else if constexpr (R8 == DUMMY) { return 0; }
2661  else { UNREACHABLE; return 0; }
2662 }
2663 template<typename T> template<Reg16 R16> ALWAYS_INLINE unsigned CPUCore<T>::get16() const {
2664  if constexpr (R16 == AF) { return getAF(); }
2665  else if constexpr (R16 == BC) { return getBC(); }
2666  else if constexpr (R16 == DE) { return getDE(); }
2667  else if constexpr (R16 == HL) { return getHL(); }
2668  else if constexpr (R16 == IX) { return getIX(); }
2669  else if constexpr (R16 == IY) { return getIY(); }
2670  else if constexpr (R16 == SP) { return getSP(); }
2671  else { UNREACHABLE; return 0; }
2672 }
2673 template<typename T> template<Reg8 R8> ALWAYS_INLINE void CPUCore<T>::set8(byte x) {
2674  if constexpr (R8 == A) { setA(x); }
2675  else if constexpr (R8 == F) { setF(x); }
2676  else if constexpr (R8 == B) { setB(x); }
2677  else if constexpr (R8 == C) { setC(x); }
2678  else if constexpr (R8 == D) { setD(x); }
2679  else if constexpr (R8 == E) { setE(x); }
2680  else if constexpr (R8 == H) { setH(x); }
2681  else if constexpr (R8 == L) { setL(x); }
2682  else if constexpr (R8 == IXH) { setIXh(x); }
2683  else if constexpr (R8 == IXL) { setIXl(x); }
2684  else if constexpr (R8 == IYH) { setIYh(x); }
2685  else if constexpr (R8 == IYL) { setIYl(x); }
2686  else if constexpr (R8 == REG_I) { setI(x); }
2687  else if constexpr (R8 == REG_R) { setR(x); }
2688  else if constexpr (R8 == DUMMY) { /* nothing */ }
2689  else { UNREACHABLE; }
2690 }
2691 template<typename T> template<Reg16 R16> ALWAYS_INLINE void CPUCore<T>::set16(unsigned x) {
2692  if constexpr (R16 == AF) { setAF(x); }
2693  else if constexpr (R16 == BC) { setBC(x); }
2694  else if constexpr (R16 == DE) { setDE(x); }
2695  else if constexpr (R16 == HL) { setHL(x); }
2696  else if constexpr (R16 == IX) { setIX(x); }
2697  else if constexpr (R16 == IY) { setIY(x); }
2698  else if constexpr (R16 == SP) { setSP(x); }
2699  else { UNREACHABLE; }
2700 }
2701 
2702 // LD r,r
2703 template<typename T> template<Reg8 DST, Reg8 SRC, int EE> II CPUCore<T>::ld_R_R() {
2704  set8<DST>(get8<SRC>()); return {1, T::CC_LD_R_R + EE};
2705 }
2706 
2707 // LD SP,ss
2708 template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ld_sp_SS() {
2709  setSP(get16<REG>()); return {1, T::CC_LD_SP_HL + EE};
2710 }
2711 
2712 // LD (ss),a
2713 template<typename T> template<Reg16 REG> II CPUCore<T>::ld_SS_a() {
2714  T::setMemPtr((getA() << 8) | ((get16<REG>() + 1) & 0xFF));
2715  WRMEM(get16<REG>(), getA(), T::CC_LD_SS_A_1);
2716  return {1, T::CC_LD_SS_A};
2717 }
2718 
2719 // LD (HL),r
2720 template<typename T> template<Reg8 SRC> II CPUCore<T>::ld_xhl_R() {
2721  WRMEM(getHL(), get8<SRC>(), T::CC_LD_HL_R_1);
2722  return {1, T::CC_LD_HL_R};
2723 }
2724 
2725 // LD (IXY+e),r
2726 template<typename T> template<Reg16 IXY, Reg8 SRC> II CPUCore<T>::ld_xix_R() {
2727  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_LD_XIX_R_1);
2728  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2729  T::setMemPtr(addr);
2730  WRMEM(addr, get8<SRC>(), T::CC_DD + T::CC_LD_XIX_R_2);
2731  return {2, T::CC_DD + T::CC_LD_XIX_R};
2732 }
2733 
2734 // LD (HL),n
2735 template<typename T> II CPUCore<T>::ld_xhl_byte() {
2736  byte val = RDMEM_OPCODE<1>(T::CC_LD_HL_N_1);
2737  WRMEM(getHL(), val, T::CC_LD_HL_N_2);
2738  return {2, T::CC_LD_HL_N};
2739 }
2740 
2741 // LD (IXY+e),n
2742 template<typename T> template<Reg16 IXY> II CPUCore<T>::ld_xix_byte() {
2743  unsigned tmp = RD_WORD_PC<1>(T::CC_DD + T::CC_LD_XIX_N_1);
2744  int8_t ofst = tmp & 0xFF;
2745  byte val = tmp >> 8;
2746  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2747  T::setMemPtr(addr);
2748  WRMEM(addr, val, T::CC_DD + T::CC_LD_XIX_N_2);
2749  return {3, T::CC_DD + T::CC_LD_XIX_N};
2750 }
2751 
2752 // LD (nn),A
2753 template<typename T> II CPUCore<T>::ld_xbyte_a() {
2754  unsigned x = RD_WORD_PC<1>(T::CC_LD_NN_A_1);
2755  T::setMemPtr((getA() << 8) | ((x + 1) & 0xFF));
2756  WRMEM(x, getA(), T::CC_LD_NN_A_2);
2757  return {3, T::CC_LD_NN_A};
2758 }
2759 
2760 // LD (nn),ss
2761 template<typename T> template<int EE> inline II CPUCore<T>::WR_NN_Y(unsigned reg) {
2762  unsigned addr = RD_WORD_PC<1>(T::CC_LD_XX_HL_1 + EE);
2763  T::setMemPtr(addr + 1);
2764  WR_WORD(addr, reg, T::CC_LD_XX_HL_2 + EE);
2765  return {3, T::CC_LD_XX_HL + EE};
2766 }
2767 template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ld_xword_SS() {
2768  return WR_NN_Y<EE >(get16<REG>());
2769 }
2770 template<typename T> template<Reg16 REG> II CPUCore<T>::ld_xword_SS_ED() {
2771  return WR_NN_Y<T::EE_ED>(get16<REG>());
2772 }
2773 
2774 // LD A,(ss)
2775 template<typename T> template<Reg16 REG> II CPUCore<T>::ld_a_SS() {
2776  T::setMemPtr(get16<REG>() + 1);
2777  setA(RDMEM(get16<REG>(), T::CC_LD_A_SS_1));
2778  return {1, T::CC_LD_A_SS};
2779 }
2780 
2781 // LD A,(nn)
2782 template<typename T> II CPUCore<T>::ld_a_xbyte() {
2783  unsigned addr = RD_WORD_PC<1>(T::CC_LD_A_NN_1);
2784  T::setMemPtr(addr + 1);
2785  setA(RDMEM(addr, T::CC_LD_A_NN_2));
2786  return {3, T::CC_LD_A_NN};
2787 }
2788 
2789 // LD r,n
2790 template<typename T> template<Reg8 DST, int EE> II CPUCore<T>::ld_R_byte() {
2791  set8<DST>(RDMEM_OPCODE<1>(T::CC_LD_R_N_1 + EE)); return {2, T::CC_LD_R_N + EE};
2792 }
2793 
2794 // LD r,(hl)
2795 template<typename T> template<Reg8 DST> II CPUCore<T>::ld_R_xhl() {
2796  set8<DST>(RDMEM(getHL(), T::CC_LD_R_HL_1)); return {1, T::CC_LD_R_HL};
2797 }
2798 
2799 // LD r,(IXY+e)
2800 template<typename T> template<Reg8 DST, Reg16 IXY> II CPUCore<T>::ld_R_xix() {
2801  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_LD_R_XIX_1);
2802  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2803  T::setMemPtr(addr);
2804  set8<DST>(RDMEM(addr, T::CC_DD + T::CC_LD_R_XIX_2));
2805  return {2, T::CC_DD + T::CC_LD_R_XIX};
2806 }
2807 
2808 // LD ss,(nn)
2809 template<typename T> template<int EE> inline unsigned CPUCore<T>::RD_P_XX() {
2810  unsigned addr = RD_WORD_PC<1>(T::CC_LD_HL_XX_1 + EE);
2811  T::setMemPtr(addr + 1);
2812  unsigned result = RD_WORD(addr, T::CC_LD_HL_XX_2 + EE);
2813  return result;
2814 }
2815 template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ld_SS_xword() {
2816  set16<REG>(RD_P_XX<EE>()); return {3, T::CC_LD_HL_XX + EE};
2817 }
2818 template<typename T> template<Reg16 REG> II CPUCore<T>::ld_SS_xword_ED() {
2819  set16<REG>(RD_P_XX<T::EE_ED>()); return {3, T::CC_LD_HL_XX + T::EE_ED};
2820 }
2821 
2822 // LD ss,nn
2823 template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ld_SS_word() {
2824  set16<REG>(RD_WORD_PC<1>(T::CC_LD_SS_NN_1 + EE)); return {3, T::CC_LD_SS_NN + EE};
2825 }
2826 
2827 
2828 // ADC A,r
2829 template<typename T> inline void CPUCore<T>::ADC(byte reg) {
2830  unsigned res = getA() + reg + ((getF() & C_FLAG) ? 1 : 0);
2831  byte f = ((res & 0x100) ? C_FLAG : 0) |
2832  ((getA() ^ res ^ reg) & H_FLAG) |
2833  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2834  0; // N_FLAG
2835  if constexpr (T::IS_R800) {
2836  f |= table.ZS[res & 0xFF];
2837  f |= getF() & (X_FLAG | Y_FLAG);
2838  } else {
2839  f |= table.ZSXY[res & 0xFF];
2840  }
2841  setF(f);
2842  setA(res);
2843 }
2844 template<typename T> inline II CPUCore<T>::adc_a_a() {
2845  unsigned res = 2 * getA() + ((getF() & C_FLAG) ? 1 : 0);
2846  byte f = ((res & 0x100) ? C_FLAG : 0) |
2847  (res & H_FLAG) |
2848  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2849  0; // N_FLAG
2850  if constexpr (T::IS_R800) {
2851  f |= table.ZS[res & 0xFF];
2852  f |= getF() & (X_FLAG | Y_FLAG);
2853  } else {
2854  f |= table.ZSXY[res & 0xFF];
2855  }
2856  setF(f);
2857  setA(res);
2858  return {1, T::CC_CP_R};
2859 }
2860 template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::adc_a_R() {
2861  ADC(get8<SRC>()); return {1, T::CC_CP_R + EE};
2862 }
2863 template<typename T> II CPUCore<T>::adc_a_byte() {
2864  ADC(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2865 }
2866 template<typename T> II CPUCore<T>::adc_a_xhl() {
2867  ADC(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2868 }
2869 template<typename T> template<Reg16 IXY> II CPUCore<T>::adc_a_xix() {
2870  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2871  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2872  T::setMemPtr(addr);
2873  ADC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2874  return {2, T::CC_DD + T::CC_CP_XIX};
2875 }
2876 
2877 // ADD A,r
2878 template<typename T> inline void CPUCore<T>::ADD(byte reg) {
2879  unsigned res = getA() + reg;
2880  byte f = ((res & 0x100) ? C_FLAG : 0) |
2881  ((getA() ^ res ^ reg) & H_FLAG) |
2882  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2883  0; // N_FLAG
2884  if constexpr (T::IS_R800) {
2885  f |= table.ZS[res & 0xFF];
2886  f |= getF() & (X_FLAG | Y_FLAG);
2887  } else {
2888  f |= table.ZSXY[res & 0xFF];
2889  }
2890  setF(f);
2891  setA(res);
2892 }
2893 template<typename T> inline II CPUCore<T>::add_a_a() {
2894  unsigned res = 2 * getA();
2895  byte f = ((res & 0x100) ? C_FLAG : 0) |
2896  (res & H_FLAG) |
2897  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2898  0; // N_FLAG
2899  if constexpr (T::IS_R800) {
2900  f |= table.ZS[res & 0xFF];
2901  f |= getF() & (X_FLAG | Y_FLAG);
2902  } else {
2903  f |= table.ZSXY[res & 0xFF];
2904  }
2905  setF(f);
2906  setA(res);
2907  return {1, T::CC_CP_R};
2908 }
2909 template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::add_a_R() {
2910  ADD(get8<SRC>()); return {1, T::CC_CP_R + EE};
2911 }
2912 template<typename T> II CPUCore<T>::add_a_byte() {
2913  ADD(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2914 }
2915 template<typename T> II CPUCore<T>::add_a_xhl() {
2916  ADD(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2917 }
2918 template<typename T> template<Reg16 IXY> II CPUCore<T>::add_a_xix() {
2919  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2920  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2921  T::setMemPtr(addr);
2922  ADD(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2923  return {2, T::CC_DD + T::CC_CP_XIX};
2924 }
2925 
2926 // AND r
2927 template<typename T> inline void CPUCore<T>::AND(byte reg) {
2928  setA(getA() & reg);
2929  byte f = 0;
2930  if constexpr (T::IS_R800) {
2931  f |= table.ZSPH[getA()];
2932  f |= getF() & (X_FLAG | Y_FLAG);
2933  } else {
2934  f |= table.ZSPXY[getA()] | H_FLAG;
2935  }
2936  setF(f);
2937 }
2938 template<typename T> II CPUCore<T>::and_a() {
2939  byte f = 0;
2940  if constexpr (T::IS_R800) {
2941  f |= table.ZSPH[getA()];
2942  f |= getF() & (X_FLAG | Y_FLAG);
2943  } else {
2944  f |= table.ZSPXY[getA()] | H_FLAG;
2945  }
2946  setF(f);
2947  return {1, T::CC_CP_R};
2948 }
2949 template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::and_R() {
2950  AND(get8<SRC>()); return {1, T::CC_CP_R + EE};
2951 }
2952 template<typename T> II CPUCore<T>::and_byte() {
2953  AND(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2954 }
2955 template<typename T> II CPUCore<T>::and_xhl() {
2956  AND(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2957 }
2958 template<typename T> template<Reg16 IXY> II CPUCore<T>::and_xix() {
2959  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2960  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2961  T::setMemPtr(addr);
2962  AND(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2963  return {2, T::CC_DD + T::CC_CP_XIX};
2964 }
2965 
2966 // CP r
2967 template<typename T> inline void CPUCore<T>::CP(byte reg) {
2968  unsigned q = getA() - reg;
2969  byte f = table.ZS[q & 0xFF] |
2970  ((q & 0x100) ? C_FLAG : 0) |
2971  N_FLAG |
2972  ((getA() ^ q ^ reg) & H_FLAG) |
2973  (((reg ^ getA()) & (getA() ^ q) & 0x80) >> 5); // V_FLAG
2974  if constexpr (T::IS_R800) {
2975  f |= getF() & (X_FLAG | Y_FLAG);
2976  } else {
2977  f |= reg & (X_FLAG | Y_FLAG); // XY from operand, not from result
2978  }
2979  setF(f);
2980 }
2981 template<typename T> II CPUCore<T>::cp_a() {
2982  byte f = ZS0 | N_FLAG;
2983  if constexpr (T::IS_R800) {
2984  f |= getF() & (X_FLAG | Y_FLAG);
2985  } else {
2986  f |= getA() & (X_FLAG | Y_FLAG); // XY from operand, not from result
2987  }
2988  setF(f);
2989  return {1, T::CC_CP_R};
2990 }
2991 template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::cp_R() {
2992  CP(get8<SRC>()); return {1, T::CC_CP_R + EE};
2993 }
2994 template<typename T> II CPUCore<T>::cp_byte() {
2995  CP(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2996 }
2997 template<typename T> II CPUCore<T>::cp_xhl() {
2998  CP(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2999 }
3000 template<typename T> template<Reg16 IXY> II CPUCore<T>::cp_xix() {
3001  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3002  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3003  T::setMemPtr(addr);
3004  CP(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3005  return {2, T::CC_DD + T::CC_CP_XIX};
3006 }
3007 
3008 // OR r
3009 template<typename T> inline void CPUCore<T>::OR(byte reg) {
3010  setA(getA() | reg);
3011  byte f = 0;
3012  if constexpr (T::IS_R800) {
3013  f |= table.ZSP[getA()];
3014  f |= getF() & (X_FLAG | Y_FLAG);
3015  } else {
3016  f |= table.ZSPXY[getA()];
3017  }
3018  setF(f);
3019 }
3020 template<typename T> II CPUCore<T>::or_a() {
3021  byte f = 0;
3022  if constexpr (T::IS_R800) {
3023  f |= table.ZSP[getA()];
3024  f |= getF() & (X_FLAG | Y_FLAG);
3025  } else {
3026  f |= table.ZSPXY[getA()];
3027  }
3028  setF(f);
3029  return {1, T::CC_CP_R};
3030 }
3031 template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::or_R() {
3032  OR(get8<SRC>()); return {1, T::CC_CP_R + EE};
3033 }
3034 template<typename T> II CPUCore<T>::or_byte() {
3035  OR(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3036 }
3037 template<typename T> II CPUCore<T>::or_xhl() {
3038  OR(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3039 }
3040 template<typename T> template<Reg16 IXY> II CPUCore<T>::or_xix() {
3041  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3042  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3043  T::setMemPtr(addr);
3044  OR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3045  return {2, T::CC_DD + T::CC_CP_XIX};
3046 }
3047 
3048 // SBC A,r
3049 template<typename T> inline void CPUCore<T>::SBC(byte reg) {
3050  unsigned res = getA() - reg - ((getF() & C_FLAG) ? 1 : 0);
3051  byte f = ((res & 0x100) ? C_FLAG : 0) |
3052  N_FLAG |
3053  ((getA() ^ res ^ reg) & H_FLAG) |
3054  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3055  if constexpr (T::IS_R800) {
3056  f |= table.ZS[res & 0xFF];
3057  f |= getF() & (X_FLAG | Y_FLAG);
3058  } else {
3059  f |= table.ZSXY[res & 0xFF];
3060  }
3061  setF(f);
3062  setA(res);
3063 }
3064 template<typename T> II CPUCore<T>::sbc_a_a() {
3065  if constexpr (T::IS_R800) {
3066  word t = (getF() & C_FLAG)
3067  ? (255 * 256 | ZS255 | C_FLAG | H_FLAG | N_FLAG)
3068  : ( 0 * 256 | ZS0 | N_FLAG);
3069  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3070  } else {
3071  setAF((getF() & C_FLAG) ?
3072  (255 * 256 | ZSXY255 | C_FLAG | H_FLAG | N_FLAG) :
3073  ( 0 * 256 | ZSXY0 | N_FLAG));
3074  }
3075  return {1, T::CC_CP_R};
3076 }
3077 template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::sbc_a_R() {
3078  SBC(get8<SRC>()); return {1, T::CC_CP_R + EE};
3079 }
3080 template<typename T> II CPUCore<T>::sbc_a_byte() {
3081  SBC(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3082 }
3083 template<typename T> II CPUCore<T>::sbc_a_xhl() {
3084  SBC(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3085 }
3086 template<typename T> template<Reg16 IXY> II CPUCore<T>::sbc_a_xix() {
3087  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3088  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3089  T::setMemPtr(addr);
3090  SBC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3091  return {2, T::CC_DD + T::CC_CP_XIX};
3092 }
3093 
3094 // SUB r
3095 template<typename T> inline void CPUCore<T>::SUB(byte reg) {
3096  unsigned res = getA() - reg;
3097  byte f = ((res & 0x100) ? C_FLAG : 0) |
3098  N_FLAG |
3099  ((getA() ^ res ^ reg) & H_FLAG) |
3100  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3101  if constexpr (T::IS_R800) {
3102  f |= table.ZS[res & 0xFF];
3103  f |= getF() & (X_FLAG | Y_FLAG);
3104  } else {
3105  f |= table.ZSXY[res & 0xFF];
3106  }
3107  setF(f);
3108  setA(res);
3109 }
3110 template<typename T> II CPUCore<T>::sub_a() {
3111  if constexpr (T::IS_R800) {
3112  word t = 0 * 256 | ZS0 | N_FLAG;
3113  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3114  } else {
3115  setAF(0 * 256 | ZSXY0 | N_FLAG);
3116  }
3117  return {1, T::CC_CP_R};
3118 }
3119 template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::sub_R() {
3120  SUB(get8<SRC>()); return {1, T::CC_CP_R + EE};
3121 }
3122 template<typename T> II CPUCore<T>::sub_byte() {
3123  SUB(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3124 }
3125 template<typename T> II CPUCore<T>::sub_xhl() {
3126  SUB(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3127 }
3128 template<typename T> template<Reg16 IXY> II CPUCore<T>::sub_xix() {
3129  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3130  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3131  T::setMemPtr(addr);
3132  SUB(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3133  return {2, T::CC_DD + T::CC_CP_XIX};
3134 }
3135 
3136 // XOR r
3137 template<typename T> inline void CPUCore<T>::XOR(byte reg) {
3138  setA(getA() ^ reg);
3139  byte f = 0;
3140  if constexpr (T::IS_R800) {
3141  f |= table.ZSP[getA()];
3142  f |= getF() & (X_FLAG | Y_FLAG);
3143  } else {
3144  f |= table.ZSPXY[getA()];
3145  }
3146  setF(f);
3147 }
3148 template<typename T> II CPUCore<T>::xor_a() {
3149  if constexpr (T::IS_R800) {
3150  word t = 0 * 256 + ZSP0;
3151  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3152  } else {
3153  setAF(0 * 256 + ZSPXY0);
3154  }
3155  return {1, T::CC_CP_R};
3156 }
3157 template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::xor_R() {
3158  XOR(get8<SRC>()); return {1, T::CC_CP_R + EE};
3159 }
3160 template<typename T> II CPUCore<T>::xor_byte() {
3161  XOR(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3162 }
3163 template<typename T> II CPUCore<T>::xor_xhl() {
3164  XOR(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3165 }
3166 template<typename T> template<Reg16 IXY> II CPUCore<T>::xor_xix() {
3167  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3168  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3169  T::setMemPtr(addr);
3170  XOR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3171  return {2, T::CC_DD + T::CC_CP_XIX};
3172 }
3173 
3174 
3175 // DEC r
3176 template<typename T> inline byte CPUCore<T>::DEC(byte reg) {
3177  byte res = reg - 1;
3178  byte f = ((reg & ~res & 0x80) >> 5) | // V_FLAG
3179  (((res & 0x0F) + 1) & H_FLAG) |
3180  N_FLAG;
3181  if constexpr (T::IS_R800) {
3182  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3183  f |= table.ZS[res];
3184  } else {
3185  f |= getF() & C_FLAG;
3186  f |= table.ZSXY[res];
3187  }
3188  setF(f);
3189  return res;
3190 }
3191 template<typename T> template<Reg8 REG, int EE> II CPUCore<T>::dec_R() {
3192  set8<REG>(DEC(get8<REG>())); return {1, T::CC_INC_R + EE};
3193 }
3194 template<typename T> template<int EE> inline void CPUCore<T>::DEC_X(unsigned x) {
3195  byte val = DEC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3196  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3197 }
3198 template<typename T> II CPUCore<T>::dec_xhl() {
3199  DEC_X<0>(getHL());
3200  return {1, T::CC_INC_XHL};
3201 }
3202 template<typename T> template<Reg16 IXY> II CPUCore<T>::dec_xix() {
3203  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_INC_XIX_1);
3204  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3205  T::setMemPtr(addr);
3206  DEC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3207  return {2, T::CC_INC_XHL + T::CC_DD + T::EE_INC_XIX};
3208 }
3209 
3210 // INC r
3211 template<typename T> inline byte CPUCore<T>::INC(byte reg) {
3212  reg++;
3213  byte f = ((reg & -reg & 0x80) >> 5) | // V_FLAG
3214  (((reg & 0x0F) - 1) & H_FLAG) |
3215  0; // N_FLAG
3216  if constexpr (T::IS_R800) {
3217  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3218  f |= table.ZS[reg];
3219  } else {
3220  f |= getF() & C_FLAG;
3221  f |= table.ZSXY[reg];
3222  }
3223  setF(f);
3224  return reg;
3225 }
3226 template<typename T> template<Reg8 REG, int EE> II CPUCore<T>::inc_R() {
3227  set8<REG>(INC(get8<REG>())); return {1, T::CC_INC_R + EE};
3228 }
3229 template<typename T> template<int EE> inline void CPUCore<T>::INC_X(unsigned x) {
3230  byte val = INC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3231  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3232 }
3233 template<typename T> II CPUCore<T>::inc_xhl() {
3234  INC_X<0>(getHL());
3235  return {1, T::CC_INC_XHL};
3236 }
3237 template<typename T> template<Reg16 IXY> II CPUCore<T>::inc_xix() {
3238  int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_INC_XIX_1);
3239  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3240  T::setMemPtr(addr);
3241  INC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3242  return {2, T::CC_INC_XHL + T::CC_DD + T::EE_INC_XIX};
3243 }
3244 
3245 
3246 // ADC HL,ss
3247 template<typename T> template<Reg16 REG> inline II CPUCore<T>::adc_hl_SS() {
3248  unsigned reg = get16<REG>();
3249  T::setMemPtr(getHL() + 1);
3250  unsigned res = getHL() + reg + ((getF() & C_FLAG) ? 1 : 0);
3251  byte f = (res >> 16) | // C_FLAG
3252  0; // N_FLAG
3253  if constexpr (T::IS_R800) {
3254  f |= getF() & (X_FLAG | Y_FLAG);
3255  }
3256  if (res & 0xFFFF) {
3257  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3258  f |= 0; // Z_FLAG
3259  f |= ((getHL() ^ res) & (reg ^ res) & 0x8000) >> 13; // V_FLAG
3260  if constexpr (T::IS_R800) {
3261  f |= (res >> 8) & S_FLAG;
3262  } else {
3263  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3264  }
3265  } else {
3266  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3267  f |= Z_FLAG;
3268  f |= (getHL() & reg & 0x8000) >> 13; // V_FLAG
3269  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3270  }
3271  setF(f);
3272  setHL(res);
3273  return {1, T::CC_ADC_HL_SS};
3274 }
3275 template<typename T> II CPUCore<T>::adc_hl_hl() {
3276  T::setMemPtr(getHL() + 1);
3277  unsigned res = 2 * getHL() + ((getF() & C_FLAG) ? 1 : 0);
3278  byte f = (res >> 16) | // C_FLAG
3279  0; // N_FLAG
3280  if constexpr (T::IS_R800) {
3281  f |= getF() & (X_FLAG | Y_FLAG);
3282  }
3283  if (res & 0xFFFF) {
3284  f |= 0; // Z_FLAG
3285  f |= ((getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3286  if constexpr (T::IS_R800) {
3287  f |= (res >> 8) & (H_FLAG | S_FLAG);
3288  } else {
3289  f |= (res >> 8) & (H_FLAG | S_FLAG | X_FLAG | Y_FLAG);
3290  }
3291  } else {
3292  f |= Z_FLAG;
3293  f |= (getHL() & 0x8000) >> 13; // V_FLAG
3294  f |= 0; // H_FLAG S_FLAG (X_FLAG Y_FLAG)
3295  }
3296  setF(f);
3297  setHL(res);
3298  return {1, T::CC_ADC_HL_SS};
3299 }
3300 
3301 // ADD HL/IX/IY,ss
3302 template<typename T> template<Reg16 REG1, Reg16 REG2, int EE> II CPUCore<T>::add_SS_TT() {
3303  unsigned reg1 = get16<REG1>();
3304  unsigned reg2 = get16<REG2>();
3305  T::setMemPtr(reg1 + 1);
3306  unsigned res = reg1 + reg2;
3307  byte f = (((reg1 ^ res ^ reg2) >> 8) & H_FLAG) |
3308  (res >> 16) | // C_FLAG
3309  0; // N_FLAG
3310  if constexpr (T::IS_R800) {
3311  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3312  } else {
3313  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3314  f |= (res >> 8) & (X_FLAG | Y_FLAG);
3315  }
3316  setF(f);
3317  set16<REG1>(res & 0xFFFF);
3318  return {1, T::CC_ADD_HL_SS + EE};
3319 }
3320 template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::add_SS_SS() {
3321  unsigned reg = get16<REG>();
3322  T::setMemPtr(reg + 1);
3323  unsigned res = 2 * reg;
3324  byte f = (res >> 16) | // C_FLAG
3325  0; // N_FLAG
3326  if constexpr (T::IS_R800) {
3327  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3328  f |= (res >> 8) & H_FLAG;
3329  } else {
3330  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3331  f |= (res >> 8) & (H_FLAG | X_FLAG | Y_FLAG);
3332  }
3333  setF(f);
3334  set16<REG>(res & 0xFFFF);
3335  return {1, T::CC_ADD_HL_SS + EE};
3336 }
3337 
3338 // SBC HL,ss
3339 template<typename T> template<Reg16 REG> inline II CPUCore<T>::sbc_hl_SS() {
3340  unsigned reg = get16<REG>();
3341  T::setMemPtr(getHL() + 1);
3342  unsigned res = getHL() - reg - ((getF() & C_FLAG) ? 1 : 0);
3343  byte f = ((res & 0x10000) ? C_FLAG : 0) |
3344  N_FLAG;
3345  if constexpr (T::IS_R800) {
3346  f |= getF() & (X_FLAG | Y_FLAG);
3347  }
3348  if (res & 0xFFFF) {
3349  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3350  f |= 0; // Z_FLAG
3351  f |= ((reg ^ getHL()) & (getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3352  if constexpr (T::IS_R800) {
3353  f |= (res >> 8) & S_FLAG;
3354  } else {
3355  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3356  }
3357  } else {
3358  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3359  f |= Z_FLAG;
3360  f |= ((reg ^ getHL()) & getHL() & 0x8000) >> 13; // V_FLAG
3361  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3362  }
3363  setF(f);
3364  setHL(res);
3365  return {1, T::CC_ADC_HL_SS};
3366 }
3367 template<typename T> II CPUCore<T>::sbc_hl_hl() {
3368  T::setMemPtr(getHL() + 1);
3369  byte f = T::IS_R800 ? (getF() & (X_FLAG | Y_FLAG)) : 0;
3370  if (getF() & C_FLAG) {
3371  f |= C_FLAG | H_FLAG | S_FLAG | N_FLAG;
3372  if constexpr (!T::IS_R800) {
3373  f |= X_FLAG | Y_FLAG;
3374  }
3375  setHL(0xFFFF);
3376  } else {
3377  f |= Z_FLAG | N_FLAG;
3378  setHL(0);
3379  }
3380  setF(f);
3381  return {1, T::CC_ADC_HL_SS};
3382 }
3383 
3384 // DEC ss
3385 template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::dec_SS() {
3386  set16<REG>(get16<REG>() - 1); return {1, T::CC_INC_SS + EE};
3387 }
3388 
3389 // INC ss
3390 template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::inc_SS() {
3391  set16<REG>(get16<REG>() + 1); return {1, T::CC_INC_SS + EE};
3392 }
3393 
3394 
3395 // BIT n,r
3396 template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::bit_N_R() {
3397  byte reg = get8<REG>();
3398  byte f = 0; // N_FLAG
3399  if constexpr (T::IS_R800) {
3400  // this is very different from Z80 (not only XY flags)
3401  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3402  f |= H_FLAG;
3403  f |= (reg & (1 << N)) ? 0 : Z_FLAG;
3404  } else {
3405  f |= table.ZSPH[reg & (1 << N)];
3406  f |= getF() & C_FLAG;
3407  f |= reg & (X_FLAG | Y_FLAG);
3408  }
3409  setF(f);
3410  return {1, T::CC_BIT_R};
3411 }
3412 template<typename T> template<unsigned N> inline II CPUCore<T>::bit_N_xhl() {
3413  byte m = RDMEM(getHL(), T::CC_BIT_XHL_1) & (1 << N);
3414  byte f = 0; // N_FLAG
3415  if constexpr (T::IS_R800) {
3416  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3417  f |= H_FLAG;
3418  f |= m ? 0 : Z_FLAG;
3419  } else {
3420  f |= table.ZSPH[m];
3421  f |= getF() & C_FLAG;
3422  f |= (T::getMemPtr() >> 8) & (X_FLAG | Y_FLAG);
3423  }
3424  setF(f);
3425  return {1, T::CC_BIT_XHL};
3426 }
3427 template<typename T> template<unsigned N> inline II CPUCore<T>::bit_N_xix(unsigned addr) {
3428  T::setMemPtr(addr);
3429  byte m = RDMEM(addr, T::CC_DD + T::CC_BIT_XIX_1) & (1 << N);
3430  byte f = 0; // N_FLAG
3431  if constexpr (T::IS_R800) {
3432  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3433  f |= H_FLAG;
3434  f |= m ? 0 : Z_FLAG;
3435  } else {
3436  f |= table.ZSPH[m];
3437  f |= getF() & C_FLAG;
3438  f |= (addr >> 8) & (X_FLAG | Y_FLAG);
3439  }
3440  setF(f);
3441  return {3, T::CC_DD + T::CC_BIT_XIX};
3442 }
3443 
3444 // RES n,r
3445 static constexpr byte RES(unsigned b, byte reg) {
3446  return reg & ~(1 << b);
3447 }
3448 template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::res_N_R() {
3449  set8<REG>(RES(N, get8<REG>())); return {1, T::CC_SET_R};
3450 }
3451 template<typename T> template<int EE> inline byte CPUCore<T>::RES_X(unsigned bit, unsigned addr) {
3452  byte res = RES(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3453  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3454  return res;
3455 }
3456 template<typename T> template<unsigned N> II CPUCore<T>::res_N_xhl() {
3457  RES_X<0>(N, getHL()); return {1, T::CC_SET_XHL};
3458 }
3459 template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::res_N_xix_R(unsigned a) {
3460  T::setMemPtr(a);
3461  set8<REG>(RES_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3462  return {3, T::CC_DD + T::CC_SET_XIX};
3463 }
3464 
3465 // SET n,r
3466 static constexpr byte SET(unsigned b, byte reg) {
3467  return reg | (1 << b);
3468 }
3469 template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::set_N_R() {
3470  set8<REG>(SET(N, get8<REG>())); return {1, T::CC_SET_R};
3471 }
3472 template<typename T> template<int EE> inline byte CPUCore<T>::SET_X(unsigned bit, unsigned addr) {
3473  byte res = SET(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3474  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3475  return res;
3476 }
3477 template<typename T> template<unsigned N> II CPUCore<T>::set_N_xhl() {
3478  SET_X<0>(N, getHL()); return {1, T::CC_SET_XHL};
3479 }
3480 template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::set_N_xix_R(unsigned a) {
3481  T::setMemPtr(a);
3482  set8<REG>(SET_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3483  return {3, T::CC_DD + T::CC_SET_XIX};
3484 }
3485 
3486 // RL r
3487 template<typename T> inline byte CPUCore<T>::RL(byte reg) {
3488  byte c = reg >> 7;
3489  reg = (reg << 1) | ((getF() & C_FLAG) ? 0x01 : 0);
3490  byte f = c ? C_FLAG : 0;
3491  if constexpr (T::IS_R800) {
3492  f |= table.ZSP[reg];
3493  f |= getF() & (X_FLAG | Y_FLAG);
3494  } else {
3495  f |= table.ZSPXY[reg];
3496  }
3497  setF(f);
3498  return reg;
3499 }
3500 template<typename T> template<int EE> inline byte CPUCore<T>::RL_X(unsigned x) {
3501  byte res = RL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3502  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3503  return res;
3504 }
3505 template<typename T> template<Reg8 REG> II CPUCore<T>::rl_R() {
3506  set8<REG>(RL(get8<REG>())); return {1, T::CC_SET_R};
3507 }
3508 template<typename T> II CPUCore<T>::rl_xhl() {
3509  RL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3510 }
3511 template<typename T> template<Reg8 REG> II CPUCore<T>::rl_xix_R(unsigned a) {
3512  T::setMemPtr(a);
3513  set8<REG>(RL_X<T::CC_DD + T::EE_SET_XIX>(a));
3514  return {3, T::CC_DD + T::CC_SET_XIX};
3515 }
3516 
3517 // RLC r
3518 template<typename T> inline byte CPUCore<T>::RLC(byte reg) {
3519  byte c = reg >> 7;
3520  reg = (reg << 1) | c;
3521  byte f = c ? C_FLAG : 0;
3522  if constexpr (T::IS_R800) {
3523  f |= table.ZSP[reg];
3524  f |= getF() & (X_FLAG | Y_FLAG);
3525  } else {
3526  f |= table.ZSPXY[reg];
3527  }
3528  setF(f);
3529  return reg;
3530 }
3531 template<typename T> template<int EE> inline byte CPUCore<T>::RLC_X(unsigned x) {
3532  byte res = RLC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3533  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3534  return res;
3535 }
3536 template<typename T> template<Reg8 REG> II CPUCore<T>::rlc_R() {
3537  set8<REG>(RLC(get8<REG>())); return {1, T::CC_SET_R};
3538 }
3539 template<typename T> II CPUCore<T>::rlc_xhl() {
3540  RLC_X<0>(getHL()); return {1, T::CC_SET_XHL};
3541 }
3542 template<typename T> template<Reg8 REG> II CPUCore<T>::rlc_xix_R(unsigned a) {
3543  T::setMemPtr(a);
3544  set8<REG>(RLC_X<T::CC_DD + T::EE_SET_XIX>(a));
3545  return {3, T::CC_DD + T::CC_SET_XIX};
3546 }
3547 
3548 // RR r
3549 template<typename T> inline byte CPUCore<T>::RR(byte reg) {
3550  byte c = reg & 1;
3551  reg = (reg >> 1) | ((getF() & C_FLAG) << 7);
3552  byte f = c ? C_FLAG : 0;
3553  if constexpr (T::IS_R800) {
3554  f |= table.ZSP[reg];
3555  f |= getF() & (X_FLAG | Y_FLAG);
3556  } else {
3557  f |= table.ZSPXY[reg];
3558  }
3559  setF(f);
3560  return reg;
3561 }
3562 template<typename T> template<int EE> inline byte CPUCore<T>::RR_X(unsigned x) {
3563  byte res = RR(RDMEM(x, T::CC_SET_XHL_1 + EE));
3564  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3565  return res;
3566 }
3567 template<typename T> template<Reg8 REG> II CPUCore<T>::rr_R() {
3568  set8<REG>(RR(get8<REG>())); return {1, T::CC_SET_R};
3569 }
3570 template<typename T> II CPUCore<T>::rr_xhl() {
3571  RR_X<0>(getHL()); return {1, T::CC_SET_XHL};
3572 }
3573 template<typename T> template<Reg8 REG> II CPUCore<T>::rr_xix_R(unsigned a) {
3574  T::setMemPtr(a);
3575  set8<REG>(RR_X<T::CC_DD + T::EE_SET_XIX>(a));
3576  return {3, T::CC_DD + T::CC_SET_XIX};
3577 }
3578 
3579 // RRC r
3580 template<typename T> inline byte CPUCore<T>::RRC(byte reg) {
3581  byte c = reg & 1;
3582  reg = (reg >> 1) | (c << 7);
3583  byte f = c ? C_FLAG : 0;
3584  if constexpr (T::IS_R800) {
3585  f |= table.ZSP[reg];
3586  f |= getF() & (X_FLAG | Y_FLAG);
3587  } else {
3588  f |= table.ZSPXY[reg];
3589  }
3590  setF(f);
3591  return reg;
3592 }
3593 template<typename T> template<int EE> inline byte CPUCore<T>::RRC_X(unsigned x) {
3594  byte res = RRC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3595  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3596  return res;
3597 }
3598 template<typename T> template<Reg8 REG> II CPUCore<T>::rrc_R() {
3599  set8<REG>(RRC(get8<REG>())); return {1, T::CC_SET_R};
3600 }
3601 template<typename T> II CPUCore<T>::rrc_xhl() {
3602  RRC_X<0>(getHL()); return {1, T::CC_SET_XHL};
3603 }
3604 template<typename T> template<Reg8 REG> II CPUCore<T>::rrc_xix_R(unsigned a) {
3605  T::setMemPtr(a);
3606  set8<REG>(RRC_X<T::CC_DD + T::EE_SET_XIX>(a));
3607  return {3, T::CC_DD + T::CC_SET_XIX};
3608 }
3609 
3610 // SLA r
3611 template<typename T> inline byte CPUCore<T>::SLA(byte reg) {
3612  byte c = reg >> 7;
3613  reg <<= 1;
3614  byte f = c ? C_FLAG : 0;
3615  if constexpr (T::IS_R800) {
3616  f |= table.ZSP[reg];
3617  f |= getF() & (X_FLAG | Y_FLAG);
3618  } else {
3619  f |= table.ZSPXY[reg];
3620  }
3621  setF(f);
3622  return reg;
3623 }
3624 template<typename T> template<int EE> inline byte CPUCore<T>::SLA_X(unsigned x) {
3625  byte res = SLA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3626  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3627  return res;
3628 }
3629 template<typename T> template<Reg8 REG> II CPUCore<T>::sla_R() {
3630  set8<REG>(SLA(get8<REG>())); return {1, T::CC_SET_R};
3631 }
3632 template<typename T> II CPUCore<T>::sla_xhl() {
3633  SLA_X<0>(getHL()); return {1, T::CC_SET_XHL};
3634 }
3635 template<typename T> template<Reg8 REG> II CPUCore<T>::sla_xix_R(unsigned a) {
3636  T::setMemPtr(a);
3637  set8<REG>(SLA_X<T::CC_DD + T::EE_SET_XIX>(a));
3638  return {3, T::CC_DD + T::CC_SET_XIX};
3639 }
3640 
3641 // SLL r
3642 template<typename T> inline byte CPUCore<T>::SLL(byte reg) {
3643  assert(!T::IS_R800); // this instruction is Z80-only
3644  byte c = reg >> 7;
3645  reg = (reg << 1) | 1;
3646  byte f = c ? C_FLAG : 0;
3647  f |= table.ZSPXY[reg];
3648  setF(f);
3649  return reg;
3650 }
3651 template<typename T> template<int EE> inline byte CPUCore<T>::SLL_X(unsigned x) {
3652  byte res = SLL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3653  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3654  return res;
3655 }
3656 template<typename T> template<Reg8 REG> II CPUCore<T>::sll_R() {
3657  set8<REG>(SLL(get8<REG>())); return {1, T::CC_SET_R};
3658 }
3659 template<typename T> II CPUCore<T>::sll_xhl() {
3660  SLL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3661 }
3662 template<typename T> template<Reg8 REG> II CPUCore<T>::sll_xix_R(unsigned a) {
3663  T::setMemPtr(a);
3664  set8<REG>(SLL_X<T::CC_DD + T::EE_SET_XIX>(a));
3665  return {3, T::CC_DD + T::CC_SET_XIX};
3666 }
3667 template<typename T> II CPUCore<T>::sll2() {
3668  assert(T::IS_R800); // this instruction is R800-only
3669  byte f = (getF() & (X_FLAG | Y_FLAG)) |
3670  (getA() >> 7) | // C_FLAG
3671  0; // all other flags zero
3672  setF(f);
3673  return {3, T::CC_DD + T::CC_SET_XIX}; // TODO
3674 }
3675 
3676 // SRA r
3677 template<typename T> inline byte CPUCore<T>::SRA(byte reg) {
3678  byte c = reg & 1;
3679  reg = (reg >> 1) | (reg & 0x80);
3680  byte f = c ? C_FLAG : 0;
3681  if constexpr (T::IS_R800) {
3682  f |= table.ZSP[reg];
3683  f |= getF() & (X_FLAG | Y_FLAG);
3684  } else {
3685  f |= table.ZSPXY[reg];
3686  }
3687  setF(f);
3688  return reg;
3689 }
3690 template<typename T> template<int EE> inline byte CPUCore<T>::SRA_X(unsigned x) {
3691  byte res = SRA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3692  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3693  return res;
3694 }
3695 template<typename T> template<Reg8 REG> II CPUCore<T>::sra_R() {
3696  set8<REG>(SRA(get8<REG>())); return {1, T::CC_SET_R};
3697 }
3698 template<typename T> II CPUCore<T>::sra_xhl() {
3699  SRA_X<0>(getHL()); return {1, T::CC_SET_XHL};
3700 }
3701 template<typename T> template<Reg8 REG> II CPUCore<T>::sra_xix_R(unsigned a) {
3702  T::setMemPtr(a);
3703  set8<REG>(SRA_X<T::CC_DD + T::EE_SET_XIX>(a));
3704  return {3, T::CC_DD + T::CC_SET_XIX};
3705 }
3706 
3707 // SRL R
3708 template<typename T> inline byte CPUCore<T>::SRL(byte reg) {
3709  byte c = reg & 1;
3710  reg >>= 1;
3711  byte f = c ? C_FLAG : 0;
3712  if constexpr (T::IS_R800) {
3713  f |= table.ZSP[reg];
3714  f |= getF() & (X_FLAG | Y_FLAG);
3715  } else {
3716  f |= table.ZSPXY[reg];
3717  }
3718  setF(f);
3719  return reg;
3720 }
3721 template<typename T> template<int EE> inline byte CPUCore<T>::SRL_X(unsigned x) {
3722  byte res = SRL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3723  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3724  return res;
3725 }
3726 template<typename T> template<Reg8 REG> II CPUCore<T>::srl_R() {
3727  set8<REG>(SRL(get8<REG>())); return {1, T::CC_SET_R};
3728 }
3729 template<typename T> II CPUCore<T>::srl_xhl() {
3730  SRL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3731 }
3732 template<typename T> template<Reg8 REG> II CPUCore<T>::srl_xix_R(unsigned a) {
3733  T::setMemPtr(a);
3734  set8<REG>(SRL_X<T::CC_DD + T::EE_SET_XIX>(a));
3735  return {3, T::CC_DD + T::CC_SET_XIX};
3736 }
3737 
3738 // RLA RLCA RRA RRCA
3739 template<typename T> II CPUCore<T>::rla() {
3740  byte c = getF() & C_FLAG;
3741  byte f = (getA() & 0x80) ? C_FLAG : 0;
3742  if constexpr (T::IS_R800) {
3743  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3744  } else {
3745  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3746  }
3747  setA((getA() << 1) | (c ? 1 : 0));
3748  if constexpr (!T::IS_R800) {
3749  f |= getA() & (X_FLAG | Y_FLAG);
3750  }
3751  setF(f);
3752  return {1, T::CC_RLA};
3753 }
3754 template<typename T> II CPUCore<T>::rlca() {
3755  setA((getA() << 1) | (getA() >> 7));
3756  byte f = 0;
3757  if constexpr (T::IS_R800) {
3758  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3759  f |= getA() & C_FLAG;
3760  } else {
3761  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3762  f |= getA() & (Y_FLAG | X_FLAG | C_FLAG);
3763  }
3764  setF(f);
3765  return {1, T::CC_RLA};
3766 }
3767 template<typename T> II CPUCore<T>::rra() {
3768  byte c = (getF() & C_FLAG) << 7;
3769  byte f = (getA() & 0x01) ? C_FLAG : 0;
3770  if constexpr (T::IS_R800) {
3771  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3772  } else {
3773  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3774  }
3775  setA((getA() >> 1) | c);
3776  if constexpr (!T::IS_R800) {
3777  f |= getA() & (X_FLAG | Y_FLAG);
3778  }
3779  setF(f);
3780  return {1, T::CC_RLA};
3781 }
3782 template<typename T> II CPUCore<T>::rrca() {
3783  byte f = getA() & C_FLAG;
3784  if constexpr (T::IS_R800) {
3785  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3786  } else {
3787  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3788  }
3789  setA((getA() >> 1) | (getA() << 7));
3790  if constexpr (!T::IS_R800) {
3791  f |= getA() & (X_FLAG | Y_FLAG);
3792  }
3793  setF(f);
3794  return {1, T::CC_RLA};
3795 }
3796 
3797 
3798 // RLD
3799 template<typename T> II CPUCore<T>::rld() {
3800  byte val = RDMEM(getHL(), T::CC_RLD_1);
3801  T::setMemPtr(getHL() + 1);
3802  WRMEM(getHL(), (val << 4) | (getA() & 0x0F), T::CC_RLD_2);
3803  setA((getA() & 0xF0) | (val >> 4));
3804  byte f = 0;
3805  if constexpr (T::IS_R800) {
3806  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3807  f |= table.ZSP[getA()];
3808  } else {
3809  f |= getF() & C_FLAG;
3810  f |= table.ZSPXY[getA()];
3811  }
3812  setF(f);
3813  return {1, T::CC_RLD};
3814 }
3815 
3816 // RRD
3817 template<typename T> II CPUCore<T>::rrd() {
3818  byte val = RDMEM(getHL(), T::CC_RLD_1);
3819  T::setMemPtr(getHL() + 1);
3820  WRMEM(getHL(), (val >> 4) | (getA() << 4), T::CC_RLD_2);
3821  setA((getA() & 0xF0) | (val & 0x0F));
3822  byte f = 0;
3823  if constexpr (T::IS_R800) {
3824  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3825  f |= table.ZSP[getA()];
3826  } else {
3827  f |= getF() & C_FLAG;
3828  f |= table.ZSPXY[getA()];
3829  }
3830  setF(f);
3831  return {1, T::CC_RLD};
3832 }
3833 
3834 
3835 // PUSH ss
3836 template<typename T> template<int EE> inline void CPUCore<T>::PUSH(unsigned reg) {
3837  setSP(getSP() - 2);
3838  WR_WORD_rev<true, true>(getSP(), reg, T::CC_PUSH_1 + EE);
3839 }
3840 template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::push_SS() {
3841  PUSH<EE>(get16<REG>()); return {1, T::CC_PUSH + EE};
3842 }
3843 
3844 // POP ss
3845 template<typename T> template<int EE> inline unsigned CPUCore<T>::POP() {
3846  unsigned addr = getSP();
3847  setSP(addr + 2);
3848  if constexpr (T::IS_R800) {
3849  // handles both POP and RET instructions (RET with condition = true)
3850  if constexpr (EE == 0) { // not reti/retn, not pop ix/iy
3851  setCurrentPopRet();
3852  // No need for setSlowInstructions()
3853  // -> this only matters directly after a CALL
3854  // instruction and in that case we're still
3855  // executing slow instructions.
3856  }
3857  }
3858  return RD_WORD(addr, T::CC_POP_1 + EE);
3859 }
3860 template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::pop_SS() {
3861  set16<REG>(POP<EE>()); return {1, T::CC_POP + EE};
3862 }
3863 
3864 
3865 // CALL nn / CALL cc,nn
3866 template<typename T> template<typename COND> II CPUCore<T>::call(COND cond) {
3867  unsigned addr = RD_WORD_PC<1>(T::CC_CALL_1);
3868  T::setMemPtr(addr);
3869  if (cond(getF())) {
3870  PUSH<T::EE_CALL>(getPC() + 3);
3871  setPC(addr);
3872  if constexpr (T::IS_R800) {
3873  setCurrentCall();
3874  setSlowInstructions();
3875  }
3876  return {0/*3*/, T::CC_CALL_A};
3877  } else {
3878  return {3, T::CC_CALL_B};
3879  }
3880 }
3881 
3882 
3883 // RST n
3884 template<typename T> template<unsigned ADDR> II CPUCore<T>::rst() {
3885  PUSH<0>(getPC() + 1);
3886  T::setMemPtr(ADDR);
3887  setPC(ADDR);
3888  if constexpr (T::IS_R800) {
3889  setCurrentCall();
3890  setSlowInstructions();
3891  }
3892  return {0/*1*/, T::CC_RST};
3893 }
3894 
3895 
3896 // RET
3897 template<typename T> template<int EE, typename COND> inline II CPUCore<T>::RET(COND cond) {
3898  if (cond(getF())) {
3899  unsigned addr = POP<EE>();
3900  T::setMemPtr(addr);
3901  setPC(addr);
3902  return {0/*1*/, T::CC_RET_A + EE};
3903  } else {
3904  return {1, T::CC_RET_B + EE};
3905  }
3906 }
3907 template<typename T> template<typename COND> II CPUCore<T>::ret(COND cond) {
3908  return RET<T::EE_RET_C>(cond);
3909 }
3910 template<typename T> II CPUCore<T>::ret() {
3911  return RET<0>(CondTrue());
3912 }
3913 template<typename T> II CPUCore<T>::retn() { // also reti
3914  setIFF1(getIFF2());
3915  setSlowInstructions();
3916  return RET<T::EE_RETN>(CondTrue());
3917 }
3918 
3919 
3920 // JP ss
3921 template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::jp_SS() {
3922  setPC(get16<REG>()); T::R800ForcePageBreak(); return {0/*1*/, T::CC_JP_HL + EE};
3923 }
3924 
3925 // JP nn / JP cc,nn
3926 template<typename T> template<typename COND> II CPUCore<T>::jp(COND cond) {
3927  unsigned addr = RD_WORD_PC<1>(T::CC_JP_1);
3928  T::setMemPtr(addr);
3929  if (cond(getF())) {
3930  setPC(addr);
3931  T::R800ForcePageBreak();
3932  return {0/*3*/, T::CC_JP_A};
3933  } else {
3934  return {3, T::CC_JP_B};
3935  }
3936 }
3937 
3938 // JR e
3939 template<typename T> template<typename COND> II CPUCore<T>::jr(COND cond) {
3940  int8_t ofst = RDMEM_OPCODE<1>(T::CC_JR_1);
3941  if (cond(getF())) {
3942  if (((getPC() + 2) & 0xFF) == 0) {
3943  // On R800, when this instruction is located in the
3944  // last two byte of a page (a page is a 256-byte
3945  // (aligned) memory block) and even if we jump back,
3946  // thus fetching the next opcode byte does not cause a
3947  // page-break, there still is one cycle overhead. It's
3948  // as-if there is a page-break.
3949  //
3950  // This could be explained by some (very limited)
3951  // pipeline behaviour in R800: it seems that the
3952  // decision to cause a page-break on the next
3953  // instruction is already made before the jump
3954  // destination address for the current instruction is
3955  // calculated (though a destination address in another
3956  // page is also a reason for a page-break).
3957  //
3958  // It's likely all instructions behave like this, but I
3959  // think we can get away with only explicitly emulating
3960  // this behaviour in the djnz and the jr (conditional
3961  // or not) instructions: all other instructions that
3962  // cause the PC to change in a non-incremental way do
3963  // already force a pagebreak for another reason, so
3964  // this effect is masked. Examples of such instructions
3965  // are: JP, RET, CALL, RST, all repeated block
3966  // instructions, accepting an IRQ, (are there more
3967  // instructions or events that change PC?)
3968  //
3969  // See doc/r800-djnz.txt for more details.
3970  T::R800ForcePageBreak();
3971  }
3972  setPC((getPC() + 2 + ofst) & 0xFFFF);
3973  T::setMemPtr(getPC());
3974  return {0/*2*/, T::CC_JR_A};
3975  } else {
3976  return {2, T::CC_JR_B};
3977  }
3978 }
3979 
3980 // DJNZ e
3981 template<typename T> II CPUCore<T>::djnz() {
3982  byte b = getB() - 1;
3983  setB(b);
3984  int8_t ofst = RDMEM_OPCODE<1>(T::CC_JR_1 + T::EE_DJNZ);
3985  if (b) {
3986  if (((getPC() + 2) & 0xFF) == 0) {
3987  // See comment in jr()
3988  T::R800ForcePageBreak();
3989  }
3990  setPC((getPC() + 2 + ofst) & 0xFFFF);
3991  T::setMemPtr(getPC());
3992  return {0/*2*/, T::CC_JR_A + T::EE_DJNZ};
3993  } else {
3994  return {2, T::CC_JR_B + T::EE_DJNZ};
3995  }
3996 }
3997 
3998 // EX (SP),ss
3999 template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ex_xsp_SS() {
4000  unsigned res = RD_WORD_impl<true, false>(getSP(), T::CC_EX_SP_HL_1 + EE);
4001  T::setMemPtr(res);
4002  WR_WORD_rev<false, true>(getSP(), get16<REG>(), T::CC_EX_SP_HL_2 + EE);
4003  set16<REG>(res);
4004  return {1, T::CC_EX_SP_HL + EE};
4005 }
4006 
4007 // IN r,(c)
4008 template<typename T> template<Reg8 REG> II CPUCore<T>::in_R_c() {
4009  if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_IN_R_C_1);
4010  T::setMemPtr(getBC() + 1);
4011  byte res = READ_PORT(getBC(), T::CC_IN_R_C_1);
4012  byte f = 0;
4013  if constexpr (T::IS_R800) {
4014  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4015  f |= table.ZSP[res];
4016  } else {
4017  f |= getF() & C_FLAG;
4018  f |= table.ZSPXY[res];
4019  }
4020  setF(f);
4021  set8<REG>(res);
4022  return {1, T::CC_IN_R_C};
4023 }
4024 
4025 // IN a,(n)
4026 template<typename T> II CPUCore<T>::in_a_byte() {
4027  unsigned y = RDMEM_OPCODE<1>(T::CC_IN_A_N_1) + 256 * getA();
4028  T::setMemPtr(y + 1);
4029  if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_IN_A_N_2);
4030  setA(READ_PORT(y, T::CC_IN_A_N_2));
4031  return {2, T::CC_IN_A_N};
4032 }
4033 
4034 // OUT (c),r
4035 template<typename T> template<Reg8 REG> II CPUCore<T>::out_c_R() {
4036  if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4037  T::setMemPtr(getBC() + 1);
4038  WRITE_PORT(getBC(), get8<REG>(), T::CC_OUT_C_R_1);
4039  return {1, T::CC_OUT_C_R};
4040 }
4041 template<typename T> II CPUCore<T>::out_c_0() {
4042  // TODO not on R800
4043  if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4044  T::setMemPtr(getBC() + 1);
4045  byte out_c_x = isTurboR ? 255 : 0;
4046  WRITE_PORT(getBC(), out_c_x, T::CC_OUT_C_R_1);
4047  return {1, T::CC_OUT_C_R};
4048 }
4049 
4050 // OUT (n),a
4051 template<typename T> II CPUCore<T>::out_byte_a() {
4052  byte port = RDMEM_OPCODE<1>(T::CC_OUT_N_A_1);
4053  unsigned y = (getA() << 8) | port;
4054  T::setMemPtr((getA() << 8) | ((port + 1) & 255));
4055  if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_OUT_N_A_2);
4056  WRITE_PORT(y, getA(), T::CC_OUT_N_A_2);
4057  return {2, T::CC_OUT_N_A};
4058 }
4059 
4060 
4061 // block CP
4062 template<typename T> inline II CPUCore<T>::BLOCK_CP(int increase, bool repeat) {
4063  T::setMemPtr(T::getMemPtr() + increase);
4064  byte val = RDMEM(getHL(), T::CC_CPI_1);
4065  byte res = getA() - val;
4066  setHL(getHL() + increase);
4067  setBC(getBC() - 1);
4068  byte f = ((getA() ^ val ^ res) & H_FLAG) |
4069  table.ZS[res] |
4070  N_FLAG |
4071  (getBC() ? V_FLAG : 0);
4072  if constexpr (T::IS_R800) {
4073  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4074  } else {
4075  f |= getF() & C_FLAG;
4076  unsigned k = res - ((f & H_FLAG) >> 4);
4077  f |= (k << 4) & Y_FLAG; // bit 1 -> flag 5
4078  f |= k & X_FLAG; // bit 3 -> flag 3
4079  }
4080  setF(f);
4081  if (repeat && getBC() && res) {
4082  //setPC(getPC() - 2);
4083  T::setMemPtr(getPC() + 1);
4084  return {-1/*1*/, T::CC_CPIR};
4085  } else {
4086  return {1, T::CC_CPI};
4087  }
4088 }
4089 template<typename T> II CPUCore<T>::cpd() { return BLOCK_CP(-1, false); }
4090 template<typename T> II CPUCore<T>::cpi() { return BLOCK_CP( 1, false); }
4091 template<typename T> II CPUCore<T>::cpdr() { return BLOCK_CP(-1, true ); }
4092 template<typename T> II CPUCore<T>::cpir() { return BLOCK_CP( 1, true ); }
4093 
4094 
4095 // block LD
4096 template<typename T> inline II CPUCore<T>::BLOCK_LD(int increase, bool repeat) {
4097  byte val = RDMEM(getHL(), T::CC_LDI_1);
4098  WRMEM(getDE(), val, T::CC_LDI_2);
4099  setHL(getHL() + increase);
4100  setDE(getDE() + increase);
4101  setBC(getBC() - 1);
4102  byte f = getBC() ? V_FLAG : 0;
4103  if constexpr (T::IS_R800) {
4104  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG | X_FLAG | Y_FLAG);
4105  } else {
4106  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG);
4107  f |= ((getA() + val) << 4) & Y_FLAG; // bit 1 -> flag 5
4108  f |= (getA() + val) & X_FLAG; // bit 3 -> flag 3
4109  }
4110  setF(f);
4111  if (repeat && getBC()) {
4112  //setPC(getPC() - 2);
4113  T::setMemPtr(getPC() + 1);
4114  return {-1/*1*/, T::CC_LDIR};
4115  } else {
4116  return {1, T::CC_LDI};
4117  }
4118 }
4119 template<typename T> II CPUCore<T>::ldd() { return BLOCK_LD(-1, false); }
4120 template<typename T> II CPUCore<T>::ldi() { return BLOCK_LD( 1, false); }
4121 template<typename T> II CPUCore<T>::lddr() { return BLOCK_LD(-1, true ); }
4122 template<typename T> II CPUCore<T>::ldir() { return BLOCK_LD( 1, true ); }
4123 
4124 
4125 // block IN
4126 template<typename T> inline II CPUCore<T>::BLOCK_IN(int increase, bool repeat) {
4127  // TODO R800 flags
4128  if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_INI_1);
4129  T::setMemPtr(getBC() + increase);
4130  setBC(getBC() - 0x100); // decr before use
4131  byte val = READ_PORT(getBC(), T::CC_INI_1);
4132  WRMEM(getHL(), val, T::CC_INI_2);
4133  setHL(getHL() + increase);
4134  unsigned k = val + ((getC() + increase) & 0xFF);
4135  byte b = getB();
4136  setF(((val & S_FLAG) >> 6) | // N_FLAG
4137  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4138  table.ZSXY[b] |
4139  (table.ZSPXY[(k & 0x07) ^ b] & P_FLAG));
4140  if (repeat && b) {
4141  //setPC(getPC() - 2);
4142  return {-1/*1*/, T::CC_INIR};
4143  } else {
4144  return {1, T::CC_INI};
4145  }
4146 }
4147 template<typename T> II CPUCore<T>::ind() { return BLOCK_IN(-1, false); }
4148 template<typename T> II CPUCore<T>::ini() { return BLOCK_IN( 1, false); }
4149 template<typename T> II CPUCore<T>::indr() { return BLOCK_IN(-1, true ); }
4150 template<typename T> II CPUCore<T>::inir() { return BLOCK_IN( 1, true ); }
4151 
4152 
4153 // block OUT
4154 template<typename T> inline II CPUCore<T>::BLOCK_OUT(int increase, bool repeat) {
4155  // TODO R800 flags
4156  byte val = RDMEM(getHL(), T::CC_OUTI_1);
4157  setHL(getHL() + increase);
4158  if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_OUTI_2);
4159  WRITE_PORT(getBC(), val, T::CC_OUTI_2);
4160  setBC(getBC() - 0x100); // decr after use
4161  T::setMemPtr(getBC() + increase);
4162  unsigned k = val + getL();
4163  byte b = getB();
4164  setF(((val & S_FLAG) >> 6) | // N_FLAG
4165  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4166  table.ZSXY[b] |
4167  (table.ZSPXY[(k & 0x07) ^ b] & P_FLAG));
4168  if (repeat && b) {
4169  //setPC(getPC() - 2);
4170  return {-1/*1*/, T::CC_OTIR};
4171  } else {
4172  return {1, T::CC_OUTI};
4173  }
4174 }
4175 template<typename T> II CPUCore<T>::outd() { return BLOCK_OUT(-1, false); }
4176 template<typename T> II CPUCore<T>::outi() { return BLOCK_OUT( 1, false); }
4177 template<typename T> II CPUCore<T>::otdr() { return BLOCK_OUT(-1, true ); }
4178 template<typename T> II CPUCore<T>::otir() { return BLOCK_OUT( 1, true ); }
4179 
4180 
4181 // various
4182 template<typename T> II CPUCore<T>::nop() { return {1, T::CC_NOP}; }
4183 template<typename T> II CPUCore<T>::ccf() {
4184  byte f = 0;
4185  if constexpr (T::IS_R800) {
4186  // H flag is different from Z80 (and as always XY flags as well)
4187  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | X_FLAG | Y_FLAG | H_FLAG);
4188  } else {
4189  f |= (getF() & C_FLAG) << 4; // H_FLAG
4190  // only set X(Y) flag (don't reset if already set)
4191  if (isTurboR) {
4192  // Y flag is not changed on a turboR-Z80
4193  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | Y_FLAG);
4194  f |= (getF() | getA()) & X_FLAG;
4195  } else {
4196  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4197  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4198  }
4199  }
4200  f ^= C_FLAG;
4201  setF(f);
4202  return {1, T::CC_CCF};
4203 }
4204 template<typename T> II CPUCore<T>::cpl() {
4205  setA(getA() ^ 0xFF);
4206  byte f = H_FLAG | N_FLAG;
4207  if constexpr (T::IS_R800) {
4208  f |= getF();
4209  } else {
4210  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4211  f |= getA() & (X_FLAG | Y_FLAG);
4212  }
4213  setF(f);
4214  return {1, T::CC_CPL};
4215 }
4216 template<typename T> II CPUCore<T>::daa() {
4217  byte a = getA();
4218  byte f = getF();
4219  byte adjust = 0;
4220  if ((f & H_FLAG) || ((getA() & 0xf) > 9)) adjust += 6;
4221  if ((f & C_FLAG) || (getA() > 0x99)) adjust += 0x60;
4222  if (f & N_FLAG) a -= adjust; else a += adjust;
4223  if constexpr (T::IS_R800) {
4224  f &= C_FLAG | N_FLAG | X_FLAG | Y_FLAG;
4225  f |= table.ZSP[a];
4226  } else {
4227  f &= C_FLAG | N_FLAG;
4228  f |= table.ZSPXY[a];
4229  }
4230  f |= (getA() > 0x99) | ((getA() ^ a) & H_FLAG);
4231  setA(a);
4232  setF(f);
4233  return {1, T::CC_DAA};
4234 }
4235 template<typename T> II CPUCore<T>::neg() {
4236  // alternative: LUT word negTable[256]
4237  unsigned a = getA();
4238  unsigned res = -signed(a);
4239  byte f = ((res & 0x100) ? C_FLAG : 0) |
4240  N_FLAG |
4241  ((res ^ a) & H_FLAG) |
4242  ((a & res & 0x80) >> 5); // V_FLAG
4243  if constexpr (T::IS_R800) {
4244  f |= table.ZS[res & 0xFF];
4245  f |= getF() & (X_FLAG | Y_FLAG);
4246  } else {
4247  f |= table.ZSXY[res & 0xFF];
4248  }
4249  setF(f);
4250  setA(res);
4251  return {1, T::CC_NEG};
4252 }
4253 template<typename T> II CPUCore<T>::scf() {
4254  byte f = C_FLAG;
4255  if constexpr (T::IS_R800) {
4256  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
4257  } else {
4258  // only set X(Y) flag (don't reset if already set)
4259  if (isTurboR) {
4260  // Y flag is not changed on a turboR-Z80
4261  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | Y_FLAG);
4262  f |= (getF() | getA()) & X_FLAG;
4263  } else {
4264  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
4265  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4266  }
4267  }
4268  setF(f);
4269  return {1, T::CC_SCF};
4270 }
4271 
4272 template<typename T> II CPUCore<T>::ex_af_af() {
4273  unsigned t = getAF2(); setAF2(getAF()); setAF(t);
4274  return {1, T::CC_EX};
4275 }
4276 template<typename T> II CPUCore<T>::ex_de_hl() {
4277  unsigned t = getDE(); setDE(getHL()); setHL(t);
4278  return {1, T::CC_EX};
4279 }
4280 template<typename T> II CPUCore<T>::exx() {
4281  unsigned t1 = getBC2(); setBC2(getBC()); setBC(t1);
4282  unsigned t2 = getDE2(); setDE2(getDE()); setDE(t2);
4283  unsigned t3 = getHL2(); setHL2(getHL()); setHL(t3);
4284  return {1, T::CC_EX};
4285 }
4286 
4287 template<typename T> II CPUCore<T>::di() {
4288  setIFF1(false);
4289  setIFF2(false);
4290  return {1, T::CC_DI};
4291 }
4292 template<typename T> II CPUCore<T>::ei() {
4293  setIFF1(true);
4294  setIFF2(true);
4295  setCurrentEI(); // no ints directly after this instr
4296  setSlowInstructions();
4297  return {1, T::CC_EI};
4298 }
4299 template<typename T> II CPUCore<T>::halt() {
4300  setHALT(true);
4301  setSlowInstructions();
4302 
4303  if (!(getIFF1() || getIFF2())) {
4304  diHaltCallback.execute();
4305  }
4306  return {1, T::CC_HALT};
4307 }
4308 template<typename T> template<unsigned N> II CPUCore<T>::im_N() {
4309  setIM(N); return {1, T::CC_IM};
4310 }
4311 
4312 // LD A,I/R
4313 template<typename T> template<Reg8 REG> II CPUCore<T>::ld_a_IR() {
4314  setA(get8<REG>());
4315  byte f = getIFF2() ? V_FLAG : 0;
4316  if constexpr (T::IS_R800) {
4317  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4318  f |= table.ZS[getA()];
4319  } else {
4320  f |= getF() & C_FLAG;
4321  f |= table.ZSXY[getA()];
4322  // see comment in the IRQ acceptance part of executeSlow().
4323  setCurrentLDAI(); // only Z80 (not R800) has this quirk
4324  setSlowInstructions();
4325  }
4326  setF(f);
4327  return {1, T::CC_LD_A_I};
4328 }
4329 
4330 // LD I/R,A
4331 template<typename T> II CPUCore<T>::ld_r_a() {
4332  // This code sequence:
4333  // XOR A / LD R,A / LD A,R
4334  // gives A=2 for Z80, but A=1 for R800. The difference can possibly be
4335  // explained by a difference in the relative time between writing the
4336  // new value to the R register and increasing the R register per M1
4337  // cycle. Here we implemented the R800 behaviour by storing 'A-1' into
4338  // R, that's good enough for now.
4339  byte val = getA();
4340  if constexpr (T::IS_R800) val -= 1;
4341  setR(val);
4342  return {1, T::CC_LD_A_I};
4343 }
4344 template<typename T> II CPUCore<T>::ld_i_a() {
4345  setI(getA());
4346  return {1, T::CC_LD_A_I};
4347 }
4348 
4349 // MULUB A,r
4350 template<typename T> template<Reg8 REG> II CPUCore<T>::mulub_a_R() {
4351  assert(T::IS_R800); // this instruction is R800-only
4352  // Verified on real R800:
4353  // YHXN flags are unchanged
4354  // SV flags are reset
4355  // Z flag is set when result is zero
4356  // C flag is set when result doesn't fit in 8-bit
4357  setHL(unsigned(getA()) * get8<REG>());
4358  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4359  0 | // S_FLAG V_FLAG
4360  (getHL() ? 0 : Z_FLAG) |
4361  ((getHL() & 0xFF00) ? C_FLAG : 0));
4362  return {1, T::CC_MULUB};
4363 }
4364 
4365 // MULUW HL,ss
4366 template<typename T> template<Reg16 REG> II CPUCore<T>::muluw_hl_SS() {
4367  assert(T::IS_R800); // this instruction is R800-only
4368  // Verified on real R800:
4369  // YHXN flags are unchanged
4370  // SV flags are reset
4371  // Z flag is set when result is zero
4372  // C flag is set when result doesn't fit in 16-bit
4373  unsigned res = unsigned(getHL()) * get16<REG>();
4374  setDE(res >> 16);
4375  setHL(res & 0xffff);
4376  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4377  0 | // S_FLAG V_FLAG
4378  (res ? 0 : Z_FLAG) |
4379  ((res & 0xFFFF0000) ? C_FLAG : 0));
4380  return {1, T::CC_MULUW};
4381 }
4382 
4383 
4384 // versions:
4385 // 1 -> initial version
4386 // 2 -> moved memptr from here to Z80TYPE (and not to R800TYPE)
4387 // 3 -> timing of the emulation changed (no changes in serialization)
4388 // 4 -> timing of the emulation changed again (see doc/internal/r800-call.txt)
4389 // 5 -> added serialization of nmiEdge
4390 template<typename T> template<typename Archive>
4391 void CPUCore<T>::serialize(Archive& ar, unsigned version)
4392 {
4393  T::serialize(ar, version);
4394  ar.serialize("regs", static_cast<CPURegs&>(*this));
4395  if (ar.versionBelow(version, 2)) {
4396  unsigned mPtr = 0; // dummy value (avoid warning)
4397  ar.serialize("memptr", mPtr);
4398  T::setMemPtr(mPtr);
4399  }
4400 
4401  if (ar.versionBelow(version, 5)) {
4402  // NMI is unused on MSX and even on systems where it is used nmiEdge
4403  // is true only between the moment the NMI request comes in and the
4404  // moment the Z80 jumps to the NMI handler, so defaulting to false
4405  // is pretty safe.
4406  nmiEdge = false;
4407  } else {
4408  // CPU is deserialized after devices, so nmiEdge is restored to the
4409  // saved version even if IRQHelpers set it on deserialization.
4410  ar.serialize("nmiEdge", nmiEdge);
4411  }
4412 
4413  // Don't serialize:
4414  // - IRQStatus, NMIStatus:
4415  // the IRQHelper deserialization makes sure these get the right value
4416  // - slowInstructions, exitLoop:
4417  // serialization happens outside the CPU emulation loop
4418 
4419  if constexpr (T::IS_R800) {
4420  if (ar.versionBelow(version, 4)) {
4421  motherboard.getMSXCliComm().printWarning(
4422  "Loading an old savestate: the timing of the R800 "
4423  "emulation has changed. This may cause synchronization "
4424  "problems in replay.");
4425  }
4426  }
4427 }
4428 
4429 // Force template instantiation
4430 template class CPUCore<Z80TYPE>;
4431 template class CPUCore<R800TYPE>;
4432 
4435 
4436 } // namespace openmsx
#define NEXT
#define NEXT_EI
#define CASE(X)
#define NEXT_STOP
TclObject t
void lowerIRQ()
Lowers the maskable interrupt count.
Definition: CPUCore.cc:441
void setNextSyncPoint(EmuTime::param time)
Definition: CPUCore.cc:496
void disasmCommand(Interpreter &interp, span< const TclObject > tokens, TclObject &result) const
Definition: CPUCore.cc:512
void setFreq(unsigned freq)
Change the clock freq.
Definition: CPUCore.cc:539
void execute(bool fastForward)
Definition: CPUCore.cc:2539
void warp(EmuTime::param time)
Definition: CPUCore.cc:323
CPUCore(MSXMotherBoard &motherboard, const std::string &name, const BooleanSetting &traceSetting, TclCallback &diHaltCallback, EmuTime::param time)
Definition: CPUCore.cc:283
void lowerNMI()
Lowers the non-maskable interrupt count.
Definition: CPUCore.cc:457
void exitCPULoopSync()
Request to exit the main CPU emulation loop.
Definition: CPUCore.cc:402
EmuTime::param getCurrentTime() const
Definition: CPUCore.cc:329
void exitCPULoopAsync()
Similar to exitCPULoopSync(), but this method may be called from any thread.
Definition: CPUCore.cc:397
void raiseNMI()
Raises the non-maskable interrupt count.
Definition: CPUCore.cc:447
void serialize(Archive &ar, unsigned version)
Definition: CPUCore.cc:4391
void doReset(EmuTime::param time)
Reset the CPU.
Definition: CPUCore.cc:334
void wait(EmuTime::param time)
Definition: CPUCore.cc:479
EmuTime waitCycles(EmuTime::param time, unsigned cycles)
Definition: CPUCore.cc:486
bool isM1Cycle(unsigned address) const
Definition: CPUCore.cc:463
void raiseIRQ()
Raises the maskable interrupt count.
Definition: CPUCore.cc:432
void addListElement(const T &t)
Definition: TclObject.hh:130
Definition: span.hh:126
constexpr index_type size() const noexcept
Definition: span.hh:296
#define NEVER_INLINE
Definition: inline.hh:17
#define ALWAYS_INLINE
Definition: inline.hh:16
#define likely(x)
Definition: likely.hh:14
#define unlikely(x)
Definition: likely.hh:15
ALWAYS_INLINE uint16_t read_UA_L16(const void *p)
Definition: endian.hh:213
ALWAYS_INLINE void write_UA_L16(void *p, uint16_t x)
Definition: endian.hh:181
constexpr unsigned LOW
Definition: CacheLine.hh:9
constexpr unsigned HIGH
Definition: CacheLine.hh:10
constexpr unsigned BITS
Definition: CacheLine.hh:6
bool isMainThread()
Returns true when called from the main thread.
Definition: Thread.cc:15
This file implemented 3 utility functions:
Definition: Autofire.cc:9
constexpr byte N_FLAG
Definition: CPUCore.cc:216
constexpr byte ZSXY0
Definition: CPUCore.cc:229
constexpr byte Y_FLAG
Definition: CPUCore.cc:211
constexpr byte Z_FLAG
Definition: CPUCore.cc:210
constexpr Table table
Definition: CPUCore.cc:264
constexpr unsigned N
Definition: ResampleHQ.cc:229
unsigned dasm(const MSXCPUInterface &interf, word pc, byte buf[4], std::string &dest, EmuTime::param time)
Disassemble.
Definition: Dasm.cc:18
@ REG_I
Definition: CPUCore.cc:205
@ REG_R
Definition: CPUCore.cc:205
@ DUMMY
Definition: CPUCore.cc:205
constexpr byte V_FLAG
Definition: CPUCore.cc:214
constexpr byte ZSXY255
Definition: CPUCore.cc:233
constexpr byte P_FLAG
Definition: CPUCore.cc:215
constexpr byte C_FLAG
Definition: CPUCore.cc:217
constexpr byte S_FLAG
Definition: CPUCore.cc:209
uint16_t word
16 bit unsigned integer
Definition: openmsx.hh:29
constexpr KeyMatrixPosition x
Keyboard bindings.
Definition: Keyboard.cc:124
void serialize(Archive &ar, T &t, unsigned version)
constexpr byte H_FLAG
Definition: CPUCore.cc:212
constexpr byte ZSPXY0
Definition: CPUCore.cc:231
constexpr byte ZSP0
Definition: CPUCore.cc:230
constexpr byte ZS0
Definition: CPUCore.cc:228
constexpr byte X_FLAG
Definition: CPUCore.cc:213
constexpr byte ZS255
Definition: CPUCore.cc:232
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
Definition: serialize.hh:983
TemporaryString tmpStrCat(Ts &&... ts)
Definition: strCat.hh:659
bool operator()(byte f) const
Definition: CPUCore.cc:273
bool operator()(byte f) const
Definition: CPUCore.cc:277
bool operator()(byte f) const
Definition: CPUCore.cc:274
bool operator()(byte f) const
Definition: CPUCore.cc:276
bool operator()(byte f) const
Definition: CPUCore.cc:279
bool operator()(byte f) const
Definition: CPUCore.cc:280
bool operator()(byte f) const
Definition: CPUCore.cc:278
bool operator()(byte) const
Definition: CPUCore.cc:281
bool operator()(byte f) const
Definition: CPUCore.cc:275
byte ZSP[256]
Definition: CPUCore.cc:223
byte ZSXY[256]
Definition: CPUCore.cc:222
byte ZSPH[256]
Definition: CPUCore.cc:225
byte ZSPXY[256]
Definition: CPUCore.cc:224
byte ZS[256]
Definition: CPUCore.cc:221
#define UNREACHABLE
Definition: unreachable.hh:38
constexpr void repeat(T n, Op op)
Repeat the given operation 'op' 'n' times.
Definition: xrange.hh:170
constexpr auto xrange(T e)
Definition: xrange.hh:155