openMSX
CPUCore.cc
Go to the documentation of this file.
1// MEMORY EMULATION
2// ----------------
3//
4// Memory access emulation is a very important part of the CPU emulation.
5// Because they happen so frequently they really need to be executed as fast as
6// possible otherwise they will completely bring down the speed of the CPU
7// emulation.
8//
9// A very fast way to emulate memory accesses is by simply reading/writing to a
10// 64kb array (for a 16-bit address space). Unfortunately this doesn't allow
11// for memory mapped IO (MMIO). These are memory regions where read/writes
12// trigger side effects, so where we need to execute device-specific code on
13// read or writes. An alternative that does work with MMIO is for every access
14// execute a virtual method call, (this is the approach taken by most current
15// MSX emulators). Unfortunately this is also a lot slower.
16//
17// It is possible to combine the speed of array accesses with the flexibility
18// of virtual methods. In openMSX it's implemented as follows: the 64kb address
19// space is divided in 256 regions of 256 bytes (called cacheLines in the code
20// below). For each such region we store a pointer, if this pointer is nullptr
21// then we have to use the slow way (=virtual method call). If it is not nullptr,
22// the pointer points to a block of memory that can be directly accessed. In
23// some contexts accesses via the pointer are known as backdoor accesses while
24// the accesses directly to the device are known as front-door accesses.
25//
26// We keep different pointers for read and write accesses. This allows to also
27// implement ROMs efficiently: read is handled as regular RAM, but writes end
28// up in some dummy memory region. This region is called 'unmappedWrite' in the
29// code. There is also a special region 'unmappedRead', this region is filled
30// with 0xFF and can be used to model (parts of) a device that don't react to
31// reads (so reads return 0xFF).
32//
33// Because of bank switching (the MSX slot select mechanism, but also e.g.
34// MegaROM back switching) the memory map as seen by the Z80 is not static. This
35// means that the cacheLine pointers also need to change during runtime. To
36// solve this we made the bank switch code also responsible for invalidating the
37// cacheLines of the switched region. These pointers are filled-in again in a
38// lazy way: the first read or write to a cache line will first get this
39// pointer (see getReadCacheLine() and getWriteCacheLine() in the code below),
40// from then on this pointer is used for all further accesses to this region,
41// until the cache is invalidated again.
42//
43//
44// INSTRUCTION EMULATION
45// ---------------------
46//
47// UPDATE: the 'threaded interpreter model' is not enabled by default
48// main reason is the huge memory requirement while compiling
49// and that it doesn't work on non-gcc compilers
50//
51// The current implementation is based on a 'threaded interpreter model'. In
52// the text below I'll call the older implementation the 'traditional
53// interpreter model'. From a very high level these two models look like this:
54//
55// Traditional model:
56// while (!needExit()) {
57// byte opcode = fetch(PC++);
58// switch (opcode) {
59// case 0x00: nop(); break;
60// case 0x01: ld_bc_nn(); break;
61// ...
62// }
63// }
64//
65// Threaded model:
66// byte opcode = fetch(PC++); //
67// goto *(table[opcode]); // fetch-and-dispatch
68// // note: the goto * syntax is a gcc extension called computed-gotos
69//
70// op00: nop(); if (!needExit()) [fetch-and-dispatch];
71// op01: ld_bc_nn(); if (!needExit()) [fetch-and-dispatch];
72// ...
73//
74// In the first model there is a central place in the code that fetches (the
75// first byte of) the instruction and based on this byte jumps to the
76// appropriate routine. In the second model, this fetch-and-dispatch logic is
77// duplicated at the end of each instruction.
78//
79// Typically the 'dispatch' part in above paragraph is implemented (either by
80// the compiler or manually using computed goto's) via a jump table. Thus on
81// assembler level via an indirect jump. For the host CPU it's hard to predict
82// the destination address of such an indirect jump, certainly if there's only
83// one such jump for all dispatching (the traditional model). If each
84// instruction has its own indirect jump instruction (the threaded model), it
85// becomes a bit easier, because often one particular z80 instructions is
86// followed by a specific other z80 instruction (or one from a small subset).
87// For example a z80 'cp' instruction is most likely followed by a 'conditional
88// jump' z80 instruction. Modern CPUs are quite sensitive to
89// branch-(mis)predictions, so the above optimization helps quite a lot. I
90// measured a speedup of more than 10%!
91//
92// There is another advantage to the threaded model. Because also the
93// needExit() test is duplicated for each instruction, it becomes possible to
94// tweak it for individual instructions. But first let me explain this
95// exit-test in more detail.
96//
97// These are the main reasons why the emulator should stop emulating CPU
98// instructions:
99// 1) When other devices than the CPU must be emulated (e.g. video frame
100// rendering). In openMSX this is handled by the Scheduler class and
101// actually we don't exit the CPU loop (anymore) for this. Instead we
102// simply execute the device code as a subroutine. Each time right before
103// we access an IO port or do a front-door memory access, there is a check
104// whether we should emulate device code (search for schedule() in the code
105// below).
106// 2) To keep the inner CPU loop as fast as possible we don't check for IRQ,
107// NMI or HALT status in this loop. Instead this condition is checked only
108// once at the beginning outside of the loop (if there wasn't a pending IRQ
109// on the first instruction there also won't be one on the second
110// instruction, if all we did was emulating cpu instructions). Now when one
111// of these conditions changes, we must exit the inner loop and re-evaluate
112// them. For example after an EI instruction we must check the IRQ status
113// again.
114// 3) Various reasons like:
115// * Z80/R800 switch
116// * executing a Tcl command (could be a cpu-register debug read)
117// * exit the emulator
118// 4) 'once-in-a-while': To avoid threading problems and race conditions,
119// several threads in openMSX only 'schedule' work that will later be
120// executed by the main emulation thread. The main thread checks for such
121// task outside of the cpu emulation loop. So once-in-a-while we need to
122// exit the loop. The exact timing doesn't matter here because anyway the
123// relative timing between threads is undefined.
124// So for 1) we don't need to do anything (we don't actually exit). For 2) and
125// 3) we need to exit the loop as soon as possible (right after the current
126// instruction is finished). For 4) it's OK to exit 'eventually' (a few hundred
127// z80 instructions late is still OK).
128//
129// Condition 2) is implemented with the 'slowInstructions' mechanism. Condition
130// 3) via exitCPULoopSync() (may only get called by the main emulation thread)
131// and condition 4) is implemented via exitCPULoopAsync() (can be called from
132// any thread).
133//
134// Now back to the exit-test optimization: in the threaded model each
135// instruction ends with:
136//
137// if (needExit()) return
138// byte opcode = fetch(PC++);
139// goto *(table[opcode]);
140//
141// And if we look in more detail at fetch():
142//
143// if (canDoBackdoor(addr)) {
144// doBackdoorAccess(addr);
145// } else {
146// doFrontdoorAccess(addr);
147// }
148//
149// So there are in fact two checks per instruction. This can be reduced to only
150// one check with the following trick:
151//
152// !!!WRONG!!!
153// In the past we optimized this to only check canDoBackdoor() (and make sure
154// canDoBackdoor() returned false when needExit() would return true). This
155// worked rather well, except for one case: when we exit the CPU loop we also
156// check for pending Syncronization points. It is possible such a SyncPoint
157// raises the IRQ line. So it is important to check for exit after every
158// instruction, otherwise we would enter the IRQ routine a couple of
159// instructions too late.
160
161#include "CPUCore.hh"
162
163#include "MSXCPUInterface.hh"
164#include "Scheduler.hh"
165#include "MSXMotherBoard.hh"
166#include "MSXCliComm.hh"
167#include "TclCallback.hh"
168#include "Dasm.hh"
169#include "Z80.hh"
170#include "R800.hh"
171#include "Thread.hh"
172
173#include "endian.hh"
174#include "inline.hh"
175#include "narrow.hh"
176#include "unreachable.hh"
177#include "xrange.hh"
178
179#include <array>
180#include <bit>
181#include <cassert>
182#include <iostream>
183#include <type_traits>
184
185
186//
187// #define USE_COMPUTED_GOTO
188//
189// Computed goto's are not enabled by default:
190// - Computed goto's are a gcc extension, it's not part of the official c++
191// standard. So this will only work if you use gcc as your compiler (it
192// won't work with visual c++ for example)
193// - This is only beneficial on CPUs with branch prediction for indirect jumps
194// and a reasonable amount of cache. For example it is very beneficial for a
195// intel core2 cpu (10% faster), but not for a ARM920 (a few percent slower)
196// - Compiling src/cpu/CPUCore.cc with computed goto's enabled is very demanding
197// on the compiler. On older gcc versions it requires up to 1.5GB of memory.
198// But even on more recent gcc versions it still requires around 700MB.
199//
200// Probably the easiest way to enable this, is to pass the -DUSE_COMPUTED_GOTO
201// flag to the compiler. This is for example done in the super-opt flavour.
202// See build/flavour-super-opt.mk
203
204#ifndef _MSC_VER
205 // [[maybe_unused]] on a label is not (yet?) officially part of c++
206 // Gcc/clang do support it (as an extension), but visual studio complains
207 // about it. Hence the different implementation for both.
208 #define MAYBE_UNUSED_LABEL [[maybe_unused]]
209#else
210 #pragma warning(disable : 4102) // unreferenced label
211 #define MAYBE_UNUSED_LABEL
212#endif
213
214
215namespace openmsx {
216
217enum Reg8 : int { A, F, B, C, D, E, H, L, IXH, IXL, IYH, IYL, REG_I, REG_R, DUMMY };
218enum Reg16 : int { AF, BC, DE, HL, IX, IY, SP };
219
220// flag positions
221static constexpr byte S_FLAG = 0x80;
222static constexpr byte Z_FLAG = 0x40;
223static constexpr byte Y_FLAG = 0x20;
224static constexpr byte H_FLAG = 0x10;
225static constexpr byte X_FLAG = 0x08;
226static constexpr byte V_FLAG = 0x04;
227static constexpr byte P_FLAG = V_FLAG;
228static constexpr byte N_FLAG = 0x02;
229static constexpr byte C_FLAG = 0x01;
230
231// flag-register lookup tables
232struct Table {
233 std::array<byte, 256> ZS;
234 std::array<byte, 256> ZSXY;
235 std::array<byte, 256> ZSP;
236 std::array<byte, 256> ZSPXY;
237 std::array<byte, 256> ZSPH;
238};
239
240static constexpr byte ZS0 = Z_FLAG;
241static constexpr byte ZSXY0 = Z_FLAG;
242static constexpr byte ZSP0 = Z_FLAG | V_FLAG;
243static constexpr byte ZSPXY0 = Z_FLAG | V_FLAG;
244static constexpr byte ZS255 = S_FLAG;
245static constexpr byte ZSXY255 = S_FLAG | X_FLAG | Y_FLAG;
246
247static constexpr Table initTables()
248{
249 Table table = {};
250
251 for (auto i_ : xrange(256)) {
252 auto i = narrow_cast<byte>(i_);
253 byte zFlag = (i == 0) ? Z_FLAG : 0;
254 byte sFlag = i & S_FLAG;
255 byte xFlag = i & X_FLAG;
256 byte yFlag = i & Y_FLAG;
257 byte vFlag = V_FLAG;
258 for (int v = 128; v != 0; v >>= 1) {
259 if (i & v) vFlag ^= V_FLAG;
260 }
261 table.ZS [i] = zFlag | sFlag;
262 table.ZSXY [i] = zFlag | sFlag | xFlag | yFlag;
263 table.ZSP [i] = zFlag | sFlag | vFlag;
264 table.ZSPXY[i] = zFlag | sFlag | xFlag | yFlag | vFlag;
265 table.ZSPH [i] = zFlag | sFlag | vFlag | H_FLAG;
266 }
267 assert(table.ZS [ 0] == ZS0);
268 assert(table.ZSXY [ 0] == ZSXY0);
269 assert(table.ZSP [ 0] == ZSP0);
270 assert(table.ZSPXY[ 0] == ZSPXY0);
271 assert(table.ZS [255] == ZS255);
272 assert(table.ZSXY [255] == ZSXY255);
273
274 return table;
275}
276
277static constexpr Table table = initTables();
278
279// Global variable, because it should be shared between Z80 and R800.
280// It must not be shared between the CPUs of different MSX machines, but
281// the (logical) lifetime of this variable cannot overlap between execution
282// of two MSX machines.
283static word start_pc;
284
285// conditions
286struct CondC { bool operator()(byte f) const { return (f & C_FLAG) != 0; } };
287struct CondNC { bool operator()(byte f) const { return !(f & C_FLAG); } };
288struct CondZ { bool operator()(byte f) const { return (f & Z_FLAG) != 0; } };
289struct CondNZ { bool operator()(byte f) const { return !(f & Z_FLAG); } };
290struct CondM { bool operator()(byte f) const { return (f & S_FLAG) != 0; } };
291struct CondP { bool operator()(byte f) const { return !(f & S_FLAG); } };
292struct CondPE { bool operator()(byte f) const { return (f & V_FLAG) != 0; } };
293struct CondPO { bool operator()(byte f) const { return !(f & V_FLAG); } };
294struct CondTrue { bool operator()(byte /*f*/) const { return true; } };
295
296template<typename T> CPUCore<T>::CPUCore(
297 MSXMotherBoard& motherboard_, const std::string& name,
298 const BooleanSetting& traceSetting_,
299 TclCallback& diHaltCallback_, EmuTime::param time)
300 : CPURegs(T::IS_R800)
301 , T(time, motherboard_.getScheduler())
302 , motherboard(motherboard_)
303 , scheduler(motherboard.getScheduler())
304 , traceSetting(traceSetting_)
305 , diHaltCallback(diHaltCallback_)
306 , IRQStatus(motherboard.getDebugger(), name + ".pendingIRQ",
307 "Non-zero if there are pending IRQs (thus CPU would enter "
308 "interrupt routine in EI mode).",
309 0)
310 , IRQAccept(motherboard.getDebugger(), name + ".acceptIRQ",
311 "This probe is only useful to set a breakpoint on (the value "
312 "return by read is meaningless). The breakpoint gets triggered "
313 "right after the CPU accepted an IRQ.")
314 , freqLocked(
315 motherboard.getCommandController(), tmpStrCat(name, "_freq_locked"),
316 "real (locked) or custom (unlocked) CPU frequency",
317 true)
318 , freqValue(
319 motherboard.getCommandController(), tmpStrCat(name, "_freq"),
320 "custom CPU frequency (only valid when unlocked)",
321 T::CLOCK_FREQ, 1000000, 1000000000)
322 , freq(T::CLOCK_FREQ)
323 , tracingEnabled(traceSetting.getBoolean())
324 , isCMOS(motherboard.hasToshibaEngine()) // Toshiba MSX-ENGINEs embed a CMOS Z80
325{
326 static_assert(!std::is_polymorphic_v<CPUCore<T>>,
327 "keep CPUCore non-virtual to keep PC at offset 0");
328 doSetFreq();
329 doReset(time);
330}
331
332template<typename T> void CPUCore<T>::warp(EmuTime::param time)
333{
334 assert(T::getTimeFast() <= time);
335 T::setTime(time);
336}
337
338template<typename T> EmuTime::param CPUCore<T>::getCurrentTime() const
339{
340 return T::getTime();
341}
342
343template<typename T> void CPUCore<T>::doReset(EmuTime::param time)
344{
345 // AF and SP are 0xFFFF
346 // PC, R, IFF1, IFF2, HALT and IM are 0x0
347 // all others are random
348 setAF(0xFFFF);
349 setBC(0xFFFF);
350 setDE(0xFFFF);
351 setHL(0xFFFF);
352 setIX(0xFFFF);
353 setIY(0xFFFF);
354 setPC(0x0000);
355 setSP(0xFFFF);
356 setAF2(0xFFFF);
357 setBC2(0xFFFF);
358 setDE2(0xFFFF);
359 setHL2(0xFFFF);
360 setIFF1(false);
361 setIFF2(false);
362 setHALT(false);
363 setExtHALT(false);
364 setIM(0);
365 setI(0x00);
366 setR(0x00);
367 T::setMemPtr(0xFFFF);
368 clearPrevious();
369
370 // We expect this assert to be valid
371 // assert(T::getTimeFast() <= time); // time shouldn't go backwards
372 // But it's disabled for the following reason:
373 // 'motion' (IRC nickname) managed to create a replay file that
374 // contains a reset command that falls in the middle of a Z80
375 // instruction. Replayed commands go via the Scheduler, and are
376 // (typically) executed right after a complete CPU instruction. So
377 // the CPU is (slightly) ahead in time of the about to be executed
378 // reset command.
379 // Normally this situation should never occur: console commands,
380 // hotkeys, commands over cliComm, ... are all handled via the global
381 // event mechanism. Such global events are scheduled between CPU
382 // instructions, so also in a replay they should fall between CPU
383 // instructions.
384 // However if for some reason the timing of the emulation changed
385 // (improved emulation accuracy or a bug so that emulation isn't
386 // deterministic or the replay file was edited, ...), then the above
387 // reasoning no longer holds and the assert can trigger.
388 // We need to be robust against loading older replays (when emulation
389 // timing has changed). So in that respect disabling the assert is
390 // good. Though in the example above (motion's replay) it's not clear
391 // whether the assert is really triggered by mixing an old replay
392 // with a newer openMSX version. In any case so far we haven't been
393 // able to reproduce this assert by recording and replaying using a
394 // single openMSX version.
395 T::setTime(time);
396
397 assert(NMIStatus == 0); // other devices must reset their NMI source
398 assert(IRQStatus == 0); // other devices must reset their IRQ source
399}
400
401// I believe the following two methods are thread safe even without any
402// locking. The worst that can happen is that we occasionally needlessly
403// exit the CPU loop, but that's harmless
404// TODO thread issues are always tricky, can someone confirm this really
405// is thread safe
406template<typename T> void CPUCore<T>::exitCPULoopAsync()
407{
408 // can get called from non-main threads
409 exitLoop = true;
410}
411template<typename T> void CPUCore<T>::exitCPULoopSync()
412{
413 assert(Thread::isMainThread());
414 exitLoop = true;
415 T::disableLimit();
416}
417template<typename T> inline bool CPUCore<T>::needExitCPULoop()
418{
419 // always executed in main thread
420 if (exitLoop) [[unlikely]] {
421 // Note: The test-and-set is _not_ atomic! But that's fine.
422 // An atomic implementation is trivial (see below), but
423 // this version (at least on x86) avoids the more expensive
424 // instructions on the likely path.
425 exitLoop = false;
426 return true;
427 }
428 return false;
429
430 // Alternative implementation:
431 // atomically set to false and return the old value
432 //return exitLoop.exchange(false);
433}
434
435template<typename T> void CPUCore<T>::setSlowInstructions()
436{
437 slowInstructions = 2;
438 T::disableLimit();
439}
440
441template<typename T> void CPUCore<T>::raiseIRQ()
442{
443 assert(IRQStatus >= 0);
444 if (IRQStatus == 0) {
445 setSlowInstructions();
446 }
447 IRQStatus = IRQStatus + 1;
448}
449
450template<typename T> void CPUCore<T>::lowerIRQ()
451{
452 IRQStatus = IRQStatus - 1;
453 assert(IRQStatus >= 0);
454}
455
456template<typename T> void CPUCore<T>::raiseNMI()
457{
458 assert(NMIStatus >= 0);
459 if (NMIStatus == 0) {
460 nmiEdge = true;
461 setSlowInstructions();
462 }
463 NMIStatus++;
464}
465
466template<typename T> void CPUCore<T>::lowerNMI()
467{
468 NMIStatus--;
469 assert(NMIStatus >= 0);
470}
471
472template<typename T> bool CPUCore<T>::isM1Cycle(unsigned address) const
473{
474 // This method should only be called from within a MSXDevice::readMem()
475 // method. It can be used to check whether the current read action has
476 // the M1 pin active. The 'address' parameter that is give to readMem()
477 // should be passed (unchanged) to this method.
478 //
479 // This simple implementation works because the rest of the CPUCore
480 // code is careful to only update the PC register on M1 cycles. In
481 // practice that means that the PC is (only) updated at the very end of
482 // every instruction, even if is a multi-byte instruction. Or for
483 // prefix-instructions the PC is also updated after the prefix is
484 // fetched (because such instructions activate M1 twice).
485 return address == getPC();
486}
487
488template<typename T> void CPUCore<T>::wait(EmuTime::param time)
489{
490 assert(time >= getCurrentTime());
491 scheduler.schedule(time);
492 T::advanceTime(time);
493}
494
495template<typename T> EmuTime CPUCore<T>::waitCycles(EmuTime::param time, unsigned cycles)
496{
497 T::add(cycles);
498 EmuTime time2 = T::calcTime(time, cycles);
499 // note: time2 is not necessarily equal to T::getTime() because of the
500 // way how WRITE_PORT() is implemented.
501 scheduler.schedule(time2);
502 return time2;
503}
504
505template<typename T> void CPUCore<T>::setNextSyncPoint(EmuTime::param time)
506{
507 T::setLimit(time);
508}
509
510
511static constexpr char toHex(byte x)
512{
513 return narrow<char>((x < 10) ? (x + '0') : (x - 10 + 'A'));
514}
515static constexpr void toHex(byte x, std::span<char, 3> buf)
516{
517 buf[0] = toHex(x / 16);
518 buf[1] = toHex(x & 15);
519}
520
521template<typename T> void CPUCore<T>::disasmCommand(
522 Interpreter& interp, std::span<const TclObject> tokens, TclObject& result) const
523{
524 word address = (tokens.size() < 3) ? getPC() : word(tokens[2].getInt(interp));
525 std::array<byte, 4> outBuf;
526 std::string dasmOutput;
527 unsigned len = dasm(*interface, address, outBuf, dasmOutput,
528 T::getTimeFast());
529 dasmOutput.resize(19, ' ');
530 result.addListElement(dasmOutput);
531 std::array<char, 3> tmp; tmp[2] = 0;
532 for (auto i : xrange(len)) {
533 toHex(outBuf[i], tmp);
534 result.addListElement(tmp.data());
535 }
536}
537
538template<typename T> void CPUCore<T>::update(const Setting& setting) noexcept
539{
540 if (&setting == &freqLocked) {
541 doSetFreq();
542 } else if (&setting == &freqValue) {
543 doSetFreq();
544 } else if (&setting == &traceSetting) {
545 tracingEnabled = traceSetting.getBoolean();
546 }
547}
548
549template<typename T> void CPUCore<T>::setFreq(unsigned freq_)
550{
551 freq = freq_;
552 doSetFreq();
553}
554
555template<typename T> void CPUCore<T>::doSetFreq()
556{
557 if (freqLocked.getBoolean()) {
558 // locked, use value set via setFreq()
559 T::setFreq(freq);
560 } else {
561 // unlocked, use value set by user
562 T::setFreq(freqValue.getInt());
563 }
564}
565
566
567template<typename T> inline byte CPUCore<T>::READ_PORT(word port, unsigned cc)
568{
569 EmuTime time = T::getTimeFast(cc);
570 scheduler.schedule(time);
571 byte result = interface->readIO(port, time);
572 // note: no forced page-break after IO
573 return result;
574}
575
576template<typename T> inline void CPUCore<T>::WRITE_PORT(word port, byte value, unsigned cc)
577{
578 EmuTime time = T::getTimeFast(cc);
579 scheduler.schedule(time);
580 interface->writeIO(port, value, time);
581 // note: no forced page-break after IO
582}
583
584template<typename T> template<bool PRE_PB, bool POST_PB>
585NEVER_INLINE byte CPUCore<T>::RDMEMslow(unsigned address, unsigned cc)
586{
587 interface->tick(CacheLineCounters::NonCachedRead);
588 // not cached
589 unsigned high = address >> CacheLine::BITS;
590 if (readCacheLine[high] == nullptr) {
591 // try to cache now (not a valid entry, and not yet tried)
592 auto addrBase = narrow_cast<word>(address & CacheLine::HIGH);
593 if (const byte* line = interface->getReadCacheLine(addrBase)) {
594 // cached ok
595 T::template PRE_MEM<PRE_PB, POST_PB>(address);
596 T::template POST_MEM< POST_PB>(address);
597 readCacheLine[high] = line - addrBase;
598 return readCacheLine[high][address];
599 }
600 }
601 // uncacheable
602 readCacheLine[high] = std::bit_cast<const byte*>(uintptr_t(1));
603 T::template PRE_MEM<PRE_PB, POST_PB>(address);
604 EmuTime time = T::getTimeFast(cc);
605 scheduler.schedule(time);
606 byte result = interface->readMem(narrow_cast<word>(address), time);
607 T::template POST_MEM<POST_PB>(address);
608 return result;
609}
610template<typename T> template<bool PRE_PB, bool POST_PB>
611ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl2(unsigned address, unsigned cc)
612{
613 const byte* line = readCacheLine[address >> CacheLine::BITS];
614 if (uintptr_t(line) > 1) [[likely]] {
615 // cached, fast path
616 T::template PRE_MEM<PRE_PB, POST_PB>(address);
617 T::template POST_MEM< POST_PB>(address);
618 return line[address];
619 } else {
620 return RDMEMslow<PRE_PB, POST_PB>(address, cc); // not inlined
621 }
622}
623template<typename T> template<bool PRE_PB, bool POST_PB>
624ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl(unsigned address, unsigned cc)
625{
626 constexpr bool PRE = T::template Normalize<PRE_PB >::value;
627 constexpr bool POST = T::template Normalize<POST_PB>::value;
628 return RDMEM_impl2<PRE, POST>(address, cc);
629}
630template<typename T> template<unsigned PC_OFFSET> ALWAYS_INLINE byte CPUCore<T>::RDMEM_OPCODE(unsigned cc)
631{
632 // Real Z80 would update the PC register now. In this implementation
633 // we've chosen to instead update PC only once at the end of the
634 // instruction. (Of course we made sure this difference is not
635 // noticeable by the program).
636 //
637 // See the comments in isM1Cycle() for the motivation for this
638 // deviation. Apart from that functional aspect it also turns out to be
639 // faster to only update PC once per instruction instead of after each
640 // fetch.
641 unsigned address = narrow_cast<word>(getPC() + PC_OFFSET);
642 return RDMEM_impl<false, false>(address, cc);
643}
644template<typename T> ALWAYS_INLINE byte CPUCore<T>::RDMEM(unsigned address, unsigned cc)
645{
646 return RDMEM_impl<true, true>(address, cc);
647}
648
649template<typename T> template<bool PRE_PB, bool POST_PB>
650NEVER_INLINE word CPUCore<T>::RD_WORD_slow(unsigned address, unsigned cc)
651{
652 auto res = word(RDMEM_impl<PRE_PB, false>(address, cc));
653 res |= word(RDMEM_impl<false, POST_PB>(narrow_cast<word>(address + 1), cc + T::CC_RDMEM) << 8);
654 return res;
655}
656template<typename T> template<bool PRE_PB, bool POST_PB>
657ALWAYS_INLINE word CPUCore<T>::RD_WORD_impl2(unsigned address, unsigned cc)
658{
659 const byte* line = readCacheLine[address >> CacheLine::BITS];
660 if (((address & CacheLine::LOW) != CacheLine::LOW) && (uintptr_t(line) > 1)) [[likely]] {
661 // fast path: cached and two bytes in same cache line
662 T::template PRE_WORD<PRE_PB, POST_PB>(address);
663 T::template POST_WORD< POST_PB>(address);
664 return Endian::read_UA_L16(&line[address]);
665 } else {
666 // slow path, not inline
667 return RD_WORD_slow<PRE_PB, POST_PB>(address, cc);
668 }
669}
670template<typename T> template<bool PRE_PB, bool POST_PB>
671ALWAYS_INLINE word CPUCore<T>::RD_WORD_impl(unsigned address, unsigned cc)
672{
673 constexpr bool PRE = T::template Normalize<PRE_PB >::value;
674 constexpr bool POST = T::template Normalize<POST_PB>::value;
675 return RD_WORD_impl2<PRE, POST>(address, cc);
676}
677template<typename T> template<unsigned PC_OFFSET> ALWAYS_INLINE word CPUCore<T>::RD_WORD_PC(unsigned cc)
678{
679 unsigned addr = narrow_cast<word>(getPC() + PC_OFFSET);
680 return RD_WORD_impl<false, false>(addr, cc);
681}
682template<typename T> ALWAYS_INLINE word CPUCore<T>::RD_WORD(
683 unsigned address, unsigned cc)
684{
685 return RD_WORD_impl<true, true>(address, cc);
686}
687
688template<typename T> template<bool PRE_PB, bool POST_PB>
689NEVER_INLINE void CPUCore<T>::WRMEMslow(unsigned address, byte value, unsigned cc)
690{
691 interface->tick(CacheLineCounters::NonCachedWrite);
692 // not cached
693 unsigned high = address >> CacheLine::BITS;
694 if (writeCacheLine[high] == nullptr) {
695 // try to cache now
696 auto addrBase = narrow_cast<word>(address & CacheLine::HIGH);
697 if (byte* line = interface->getWriteCacheLine(addrBase)) {
698 // cached ok
699 T::template PRE_MEM<PRE_PB, POST_PB>(address);
700 T::template POST_MEM< POST_PB>(address);
701 writeCacheLine[high] = line - addrBase;
702 writeCacheLine[high][address] = value;
703 return;
704 }
705 }
706 // uncacheable
707 writeCacheLine[high] = std::bit_cast<byte*>(uintptr_t(1));
708 T::template PRE_MEM<PRE_PB, POST_PB>(address);
709 EmuTime time = T::getTimeFast(cc);
710 scheduler.schedule(time);
711 interface->writeMem(narrow_cast<word>(address), value, time);
712 T::template POST_MEM<POST_PB>(address);
713}
714template<typename T> template<bool PRE_PB, bool POST_PB>
716 unsigned address, byte value, unsigned cc)
717{
718 byte* line = writeCacheLine[address >> CacheLine::BITS];
719 if (uintptr_t(line) > 1) [[likely]] {
720 // cached, fast path
721 T::template PRE_MEM<PRE_PB, POST_PB>(address);
722 T::template POST_MEM< POST_PB>(address);
723 line[address] = value;
724 } else {
725 WRMEMslow<PRE_PB, POST_PB>(address, value, cc); // not inlined
726 }
727}
728template<typename T> template<bool PRE_PB, bool POST_PB>
730 unsigned address, byte value, unsigned cc)
731{
732 constexpr bool PRE = T::template Normalize<PRE_PB >::value;
733 constexpr bool POST = T::template Normalize<POST_PB>::value;
734 WRMEM_impl2<PRE, POST>(address, value, cc);
735}
736template<typename T> ALWAYS_INLINE void CPUCore<T>::WRMEM(
737 unsigned address, byte value, unsigned cc)
738{
739 WRMEM_impl<true, true>(address, value, cc);
740}
741
742template<typename T> NEVER_INLINE void CPUCore<T>::WR_WORD_slow(
743 unsigned address, word value, unsigned cc)
744{
745 WRMEM_impl<true, false>( address, byte(value & 255), cc);
746 WRMEM_impl<false, true>(narrow_cast<word>(address + 1), byte(value >> 8), cc + T::CC_WRMEM);
747}
748template<typename T> ALWAYS_INLINE void CPUCore<T>::WR_WORD(
749 unsigned address, word value, unsigned cc)
750{
751 byte* line = writeCacheLine[address >> CacheLine::BITS];
752 if (((address & CacheLine::LOW) != CacheLine::LOW) && (uintptr_t(line) > 1)) [[likely]] {
753 // fast path: cached and two bytes in same cache line
754 T::template PRE_WORD<true, true>(address);
755 T::template POST_WORD< true>(address);
756 Endian::write_UA_L16(&line[address], value);
757 } else {
758 // slow path, not inline
759 WR_WORD_slow(address, value, cc);
760 }
761}
762
763// same as WR_WORD, but writes high byte first
764template<typename T> template<bool PRE_PB, bool POST_PB>
766 unsigned address, word value, unsigned cc)
767{
768 WRMEM_impl<PRE_PB, false>(narrow_cast<word>(address + 1), byte(value >> 8), cc);
769 WRMEM_impl<false, POST_PB>( address, byte(value & 255), cc + T::CC_WRMEM);
770}
771template<typename T> template<bool PRE_PB, bool POST_PB>
773 unsigned address, word value, unsigned cc)
774{
775 byte* line = writeCacheLine[address >> CacheLine::BITS];
776 if (((address & CacheLine::LOW) != CacheLine::LOW) && (uintptr_t(line) > 1)) [[likely]] {
777 // fast path: cached and two bytes in same cache line
778 T::template PRE_WORD<PRE_PB, POST_PB>(address);
779 T::template POST_WORD< POST_PB>(address);
780 Endian::write_UA_L16(&line[address], value);
781 } else {
782 // slow path, not inline
783 WR_WORD_rev_slow<PRE_PB, POST_PB>(address, value, cc);
784 }
785}
786template<typename T> template<bool PRE_PB, bool POST_PB>
788 unsigned address, word value, unsigned cc)
789{
790 constexpr bool PRE = T::template Normalize<PRE_PB >::value;
791 constexpr bool POST = T::template Normalize<POST_PB>::value;
792 WR_WORD_rev2<PRE, POST>(address, value, cc);
793}
794
795
796// NMI interrupt
797template<typename T> inline void CPUCore<T>::nmi()
798{
799 incR(1);
800 setHALT(false);
801 setIFF1(false);
802 PUSH<T::EE_NMI_1>(getPC());
803 setPC(0x0066);
804 T::add(T::CC_NMI);
805}
806
807// IM0 interrupt
808template<typename T> inline void CPUCore<T>::irq0()
809{
810 // TODO current implementation only works for 1-byte instructions
811 // ok for MSX
812 assert(interface->readIRQVector() == 0xFF);
813 incR(1);
814 setHALT(false);
815 setIFF1(false);
816 setIFF2(false);
817 PUSH<T::EE_IRQ0_1>(getPC());
818 setPC(0x0038);
819 T::setMemPtr(getPC());
820 T::add(T::CC_IRQ0);
821}
822
823// IM1 interrupt
824template<typename T> inline void CPUCore<T>::irq1()
825{
826 incR(1);
827 setHALT(false);
828 setIFF1(false);
829 setIFF2(false);
830 PUSH<T::EE_IRQ1_1>(getPC());
831 setPC(0x0038);
832 T::setMemPtr(getPC());
833 T::add(T::CC_IRQ1);
834}
835
836// IM2 interrupt
837template<typename T> inline void CPUCore<T>::irq2()
838{
839 incR(1);
840 setHALT(false);
841 setIFF1(false);
842 setIFF2(false);
843 PUSH<T::EE_IRQ2_1>(getPC());
844 unsigned x = interface->readIRQVector() | (getI() << 8);
845 setPC(RD_WORD(x, T::CC_IRQ2_2));
846 T::setMemPtr(getPC());
847 T::add(T::CC_IRQ2);
848}
849
850template<typename T>
851void CPUCore<T>::executeInstructions()
852{
853 checkNoCurrentFlags();
854#ifdef USE_COMPUTED_GOTO
855 // Addresses of all main-opcode routines,
856 // Note that 40/49/53/5B/64/6D/7F is replaced by 00 (ld r,r == nop)
857 static std::array<void*, 256> opcodeTable = {
858 &&op00, &&op01, &&op02, &&op03, &&op04, &&op05, &&op06, &&op07,
859 &&op08, &&op09, &&op0A, &&op0B, &&op0C, &&op0D, &&op0E, &&op0F,
860 &&op10, &&op11, &&op12, &&op13, &&op14, &&op15, &&op16, &&op17,
861 &&op18, &&op19, &&op1A, &&op1B, &&op1C, &&op1D, &&op1E, &&op1F,
862 &&op20, &&op21, &&op22, &&op23, &&op24, &&op25, &&op26, &&op27,
863 &&op28, &&op29, &&op2A, &&op2B, &&op2C, &&op2D, &&op2E, &&op2F,
864 &&op30, &&op31, &&op32, &&op33, &&op34, &&op35, &&op36, &&op37,
865 &&op38, &&op39, &&op3A, &&op3B, &&op3C, &&op3D, &&op3E, &&op3F,
866 &&op00, &&op41, &&op42, &&op43, &&op44, &&op45, &&op46, &&op47,
867 &&op48, &&op00, &&op4A, &&op4B, &&op4C, &&op4D, &&op4E, &&op4F,
868 &&op50, &&op51, &&op00, &&op53, &&op54, &&op55, &&op56, &&op57,
869 &&op58, &&op59, &&op5A, &&op00, &&op5C, &&op5D, &&op5E, &&op5F,
870 &&op60, &&op61, &&op62, &&op63, &&op00, &&op65, &&op66, &&op67,
871 &&op68, &&op69, &&op6A, &&op6B, &&op6C, &&op00, &&op6E, &&op6F,
872 &&op70, &&op71, &&op72, &&op73, &&op74, &&op75, &&op76, &&op77,
873 &&op78, &&op79, &&op7A, &&op7B, &&op7C, &&op7D, &&op7E, &&op00,
874 &&op80, &&op81, &&op82, &&op83, &&op84, &&op85, &&op86, &&op87,
875 &&op88, &&op89, &&op8A, &&op8B, &&op8C, &&op8D, &&op8E, &&op8F,
876 &&op90, &&op91, &&op92, &&op93, &&op94, &&op95, &&op96, &&op97,
877 &&op98, &&op99, &&op9A, &&op9B, &&op9C, &&op9D, &&op9E, &&op9F,
878 &&opA0, &&opA1, &&opA2, &&opA3, &&opA4, &&opA5, &&opA6, &&opA7,
879 &&opA8, &&opA9, &&opAA, &&opAB, &&opAC, &&opAD, &&opAE, &&opAF,
880 &&opB0, &&opB1, &&opB2, &&opB3, &&opB4, &&opB5, &&opB6, &&opB7,
881 &&opB8, &&opB9, &&opBA, &&opBB, &&opBC, &&opBD, &&opBE, &&opBF,
882 &&opC0, &&opC1, &&opC2, &&opC3, &&opC4, &&opC5, &&opC6, &&opC7,
883 &&opC8, &&opC9, &&opCA, &&opCB, &&opCC, &&opCD, &&opCE, &&opCF,
884 &&opD0, &&opD1, &&opD2, &&opD3, &&opD4, &&opD5, &&opD6, &&opD7,
885 &&opD8, &&opD9, &&opDA, &&opDB, &&opDC, &&opDD, &&opDE, &&opDF,
886 &&opE0, &&opE1, &&opE2, &&opE3, &&opE4, &&opE5, &&opE6, &&opE7,
887 &&opE8, &&opE9, &&opEA, &&opEB, &&opEC, &&opED, &&opEE, &&opEF,
888 &&opF0, &&opF1, &&opF2, &&opF3, &&opF4, &&opF5, &&opF6, &&opF7,
889 &&opF8, &&opF9, &&opFA, &&opFB, &&opFC, &&opFD, &&opFE, &&opFF,
890 };
891
892// Check T::limitReached(). If it's OK to continue,
893// fetch and execute next instruction.
894#define NEXT \
895 setPC(getPC() + ii.length); \
896 T::add(ii.cycles); \
897 T::R800Refresh(*this); \
898 if (!T::limitReached()) [[likely]] { \
899 incR(1); \
900 unsigned address = getPC(); \
901 const byte* line = readCacheLine[address >> CacheLine::BITS]; \
902 if (uintptr_t(line) > 1) [[likely]] { \
903 T::template PRE_MEM<false, false>(address); \
904 T::template POST_MEM< false>(address); \
905 byte op = line[address]; \
906 goto *(opcodeTable[op]); \
907 } else { \
908 goto fetchSlow; \
909 } \
910 } \
911 return;
912
913// After some instructions we must always exit the CPU loop (ei, halt, retn)
914#define NEXT_STOP \
915 setPC(getPC() + ii.length); \
916 T::add(ii.cycles); \
917 T::R800Refresh(*this); \
918 assert(T::limitReached()); \
919 return;
920
921#define NEXT_EI \
922 setPC(getPC() + ii.length); \
923 T::add(ii.cycles); \
924 /* !! NO T::R800Refresh(*this); !! */ \
925 assert(T::limitReached()); \
926 return;
927
928// Define a label (instead of case in a switch statement)
929#define CASE(X) op##X:
930
931#else // USE_COMPUTED_GOTO
932
933#define NEXT \
934 setPC(getPC() + ii.length); \
935 T::add(ii.cycles); \
936 T::R800Refresh(*this); \
937 if (!T::limitReached()) [[likely]] { \
938 goto start; \
939 } \
940 return;
941
942#define NEXT_STOP \
943 setPC(getPC() + ii.length); \
944 T::add(ii.cycles); \
945 T::R800Refresh(*this); \
946 assert(T::limitReached()); \
947 return;
948
949#define NEXT_EI \
950 setPC(getPC() + ii.length); \
951 T::add(ii.cycles); \
952 /* !! NO T::R800Refresh(*this); !! */ \
953 assert(T::limitReached()); \
954 return;
955
956#define CASE(X) case 0x##X:
957
958#endif // USE_COMPUTED_GOTO
959
960#ifndef USE_COMPUTED_GOTO
961start:
962#endif
963 unsigned ixy; // for dd_cb/fd_cb
964 byte opcodeMain = RDMEM_OPCODE<0>(T::CC_MAIN);
965 incR(1);
966#ifdef USE_COMPUTED_GOTO
967 goto *(opcodeTable[opcodeMain]);
968
969fetchSlow: {
970 unsigned address = getPC();
971 byte opcodeSlow = RDMEMslow<false, false>(address, T::CC_MAIN);
972 goto *(opcodeTable[opcodeSlow]);
973}
974#endif
975
976#ifndef USE_COMPUTED_GOTO
977MAYBE_UNUSED_LABEL switchOpcode:
978 switch (opcodeMain) {
979CASE(40) // ld b,b
980CASE(49) // ld c,c
981CASE(52) // ld d,d
982CASE(5B) // ld e,e
983CASE(64) // ld h,h
984CASE(6D) // ld l,l
985CASE(7F) // ld a,a
986#endif
987CASE(00) { II ii = nop(); NEXT; }
988CASE(07) { II ii = rlca(); NEXT; }
989CASE(0F) { II ii = rrca(); NEXT; }
990CASE(17) { II ii = rla(); NEXT; }
991CASE(1F) { II ii = rra(); NEXT; }
992CASE(08) { II ii = ex_af_af(); NEXT; }
993CASE(27) { II ii = daa(); NEXT; }
994CASE(2F) { II ii = cpl(); NEXT; }
995CASE(37) { II ii = scf(); NEXT; }
996CASE(3F) { II ii = ccf(); NEXT; }
997CASE(20) { II ii = jr(CondNZ()); NEXT; }
998CASE(28) { II ii = jr(CondZ ()); NEXT; }
999CASE(30) { II ii = jr(CondNC()); NEXT; }
1000CASE(38) { II ii = jr(CondC ()); NEXT; }
1001CASE(18) { II ii = jr(CondTrue()); NEXT; }
1002CASE(10) { II ii = djnz(); NEXT; }
1003CASE(32) { II ii = ld_xbyte_a(); NEXT; }
1004CASE(3A) { II ii = ld_a_xbyte(); NEXT; }
1005CASE(22) { II ii = ld_xword_SS<HL,0>(); NEXT; }
1006CASE(2A) { II ii = ld_SS_xword<HL,0>(); NEXT; }
1007CASE(02) { II ii = ld_SS_a<BC>(); NEXT; }
1008CASE(12) { II ii = ld_SS_a<DE>(); NEXT; }
1009CASE(1A) { II ii = ld_a_SS<DE>(); NEXT; }
1010CASE(0A) { II ii = ld_a_SS<BC>(); NEXT; }
1011CASE(03) { II ii = inc_SS<BC,0>(); NEXT; }
1012CASE(13) { II ii = inc_SS<DE,0>(); NEXT; }
1013CASE(23) { II ii = inc_SS<HL,0>(); NEXT; }
1014CASE(33) { II ii = inc_SS<SP,0>(); NEXT; }
1015CASE(0B) { II ii = dec_SS<BC,0>(); NEXT; }
1016CASE(1B) { II ii = dec_SS<DE,0>(); NEXT; }
1017CASE(2B) { II ii = dec_SS<HL,0>(); NEXT; }
1018CASE(3B) { II ii = dec_SS<SP,0>(); NEXT; }
1019CASE(09) { II ii = add_SS_TT<HL,BC,0>(); NEXT; }
1020CASE(19) { II ii = add_SS_TT<HL,DE,0>(); NEXT; }
1021CASE(29) { II ii = add_SS_SS<HL ,0>(); NEXT; }
1022CASE(39) { II ii = add_SS_TT<HL,SP,0>(); NEXT; }
1023CASE(01) { II ii = ld_SS_word<BC,0>(); NEXT; }
1024CASE(11) { II ii = ld_SS_word<DE,0>(); NEXT; }
1025CASE(21) { II ii = ld_SS_word<HL,0>(); NEXT; }
1026CASE(31) { II ii = ld_SS_word<SP,0>(); NEXT; }
1027CASE(04) { II ii = inc_R<B,0>(); NEXT; }
1028CASE(0C) { II ii = inc_R<C,0>(); NEXT; }
1029CASE(14) { II ii = inc_R<D,0>(); NEXT; }
1030CASE(1C) { II ii = inc_R<E,0>(); NEXT; }
1031CASE(24) { II ii = inc_R<H,0>(); NEXT; }
1032CASE(2C) { II ii = inc_R<L,0>(); NEXT; }
1033CASE(3C) { II ii = inc_R<A,0>(); NEXT; }
1034CASE(34) { II ii = inc_xhl(); NEXT; }
1035CASE(05) { II ii = dec_R<B,0>(); NEXT; }
1036CASE(0D) { II ii = dec_R<C,0>(); NEXT; }
1037CASE(15) { II ii = dec_R<D,0>(); NEXT; }
1038CASE(1D) { II ii = dec_R<E,0>(); NEXT; }
1039CASE(25) { II ii = dec_R<H,0>(); NEXT; }
1040CASE(2D) { II ii = dec_R<L,0>(); NEXT; }
1041CASE(3D) { II ii = dec_R<A,0>(); NEXT; }
1042CASE(35) { II ii = dec_xhl(); NEXT; }
1043CASE(06) { II ii = ld_R_byte<B,0>(); NEXT; }
1044CASE(0E) { II ii = ld_R_byte<C,0>(); NEXT; }
1045CASE(16) { II ii = ld_R_byte<D,0>(); NEXT; }
1046CASE(1E) { II ii = ld_R_byte<E,0>(); NEXT; }
1047CASE(26) { II ii = ld_R_byte<H,0>(); NEXT; }
1048CASE(2E) { II ii = ld_R_byte<L,0>(); NEXT; }
1049CASE(3E) { II ii = ld_R_byte<A,0>(); NEXT; }
1050CASE(36) { II ii = ld_xhl_byte(); NEXT; }
1051
1052CASE(41) { II ii = ld_R_R<B,C,0>(); NEXT; }
1053CASE(42) { II ii = ld_R_R<B,D,0>(); NEXT; }
1054CASE(43) { II ii = ld_R_R<B,E,0>(); NEXT; }
1055CASE(44) { II ii = ld_R_R<B,H,0>(); NEXT; }
1056CASE(45) { II ii = ld_R_R<B,L,0>(); NEXT; }
1057CASE(47) { II ii = ld_R_R<B,A,0>(); NEXT; }
1058CASE(48) { II ii = ld_R_R<C,B,0>(); NEXT; }
1059CASE(4A) { II ii = ld_R_R<C,D,0>(); NEXT; }
1060CASE(4B) { II ii = ld_R_R<C,E,0>(); NEXT; }
1061CASE(4C) { II ii = ld_R_R<C,H,0>(); NEXT; }
1062CASE(4D) { II ii = ld_R_R<C,L,0>(); NEXT; }
1063CASE(4F) { II ii = ld_R_R<C,A,0>(); NEXT; }
1064CASE(50) { II ii = ld_R_R<D,B,0>(); NEXT; }
1065CASE(51) { II ii = ld_R_R<D,C,0>(); NEXT; }
1066CASE(53) { II ii = ld_R_R<D,E,0>(); NEXT; }
1067CASE(54) { II ii = ld_R_R<D,H,0>(); NEXT; }
1068CASE(55) { II ii = ld_R_R<D,L,0>(); NEXT; }
1069CASE(57) { II ii = ld_R_R<D,A,0>(); NEXT; }
1070CASE(58) { II ii = ld_R_R<E,B,0>(); NEXT; }
1071CASE(59) { II ii = ld_R_R<E,C,0>(); NEXT; }
1072CASE(5A) { II ii = ld_R_R<E,D,0>(); NEXT; }
1073CASE(5C) { II ii = ld_R_R<E,H,0>(); NEXT; }
1074CASE(5D) { II ii = ld_R_R<E,L,0>(); NEXT; }
1075CASE(5F) { II ii = ld_R_R<E,A,0>(); NEXT; }
1076CASE(60) { II ii = ld_R_R<H,B,0>(); NEXT; }
1077CASE(61) { II ii = ld_R_R<H,C,0>(); NEXT; }
1078CASE(62) { II ii = ld_R_R<H,D,0>(); NEXT; }
1079CASE(63) { II ii = ld_R_R<H,E,0>(); NEXT; }
1080CASE(65) { II ii = ld_R_R<H,L,0>(); NEXT; }
1081CASE(67) { II ii = ld_R_R<H,A,0>(); NEXT; }
1082CASE(68) { II ii = ld_R_R<L,B,0>(); NEXT; }
1083CASE(69) { II ii = ld_R_R<L,C,0>(); NEXT; }
1084CASE(6A) { II ii = ld_R_R<L,D,0>(); NEXT; }
1085CASE(6B) { II ii = ld_R_R<L,E,0>(); NEXT; }
1086CASE(6C) { II ii = ld_R_R<L,H,0>(); NEXT; }
1087CASE(6F) { II ii = ld_R_R<L,A,0>(); NEXT; }
1088CASE(78) { II ii = ld_R_R<A,B,0>(); NEXT; }
1089CASE(79) { II ii = ld_R_R<A,C,0>(); NEXT; }
1090CASE(7A) { II ii = ld_R_R<A,D,0>(); NEXT; }
1091CASE(7B) { II ii = ld_R_R<A,E,0>(); NEXT; }
1092CASE(7C) { II ii = ld_R_R<A,H,0>(); NEXT; }
1093CASE(7D) { II ii = ld_R_R<A,L,0>(); NEXT; }
1094CASE(70) { II ii = ld_xhl_R<B>(); NEXT; }
1095CASE(71) { II ii = ld_xhl_R<C>(); NEXT; }
1096CASE(72) { II ii = ld_xhl_R<D>(); NEXT; }
1097CASE(73) { II ii = ld_xhl_R<E>(); NEXT; }
1098CASE(74) { II ii = ld_xhl_R<H>(); NEXT; }
1099CASE(75) { II ii = ld_xhl_R<L>(); NEXT; }
1100CASE(77) { II ii = ld_xhl_R<A>(); NEXT; }
1101CASE(46) { II ii = ld_R_xhl<B>(); NEXT; }
1102CASE(4E) { II ii = ld_R_xhl<C>(); NEXT; }
1103CASE(56) { II ii = ld_R_xhl<D>(); NEXT; }
1104CASE(5E) { II ii = ld_R_xhl<E>(); NEXT; }
1105CASE(66) { II ii = ld_R_xhl<H>(); NEXT; }
1106CASE(6E) { II ii = ld_R_xhl<L>(); NEXT; }
1107CASE(7E) { II ii = ld_R_xhl<A>(); NEXT; }
1108CASE(76) { II ii = halt(); NEXT_STOP; }
1109
1110CASE(80) { II ii = add_a_R<B,0>(); NEXT; }
1111CASE(81) { II ii = add_a_R<C,0>(); NEXT; }
1112CASE(82) { II ii = add_a_R<D,0>(); NEXT; }
1113CASE(83) { II ii = add_a_R<E,0>(); NEXT; }
1114CASE(84) { II ii = add_a_R<H,0>(); NEXT; }
1115CASE(85) { II ii = add_a_R<L,0>(); NEXT; }
1116CASE(86) { II ii = add_a_xhl(); NEXT; }
1117CASE(87) { II ii = add_a_a(); NEXT; }
1118CASE(88) { II ii = adc_a_R<B,0>(); NEXT; }
1119CASE(89) { II ii = adc_a_R<C,0>(); NEXT; }
1120CASE(8A) { II ii = adc_a_R<D,0>(); NEXT; }
1121CASE(8B) { II ii = adc_a_R<E,0>(); NEXT; }
1122CASE(8C) { II ii = adc_a_R<H,0>(); NEXT; }
1123CASE(8D) { II ii = adc_a_R<L,0>(); NEXT; }
1124CASE(8E) { II ii = adc_a_xhl(); NEXT; }
1125CASE(8F) { II ii = adc_a_a(); NEXT; }
1126CASE(90) { II ii = sub_R<B,0>(); NEXT; }
1127CASE(91) { II ii = sub_R<C,0>(); NEXT; }
1128CASE(92) { II ii = sub_R<D,0>(); NEXT; }
1129CASE(93) { II ii = sub_R<E,0>(); NEXT; }
1130CASE(94) { II ii = sub_R<H,0>(); NEXT; }
1131CASE(95) { II ii = sub_R<L,0>(); NEXT; }
1132CASE(96) { II ii = sub_xhl(); NEXT; }
1133CASE(97) { II ii = sub_a(); NEXT; }
1134CASE(98) { II ii = sbc_a_R<B,0>(); NEXT; }
1135CASE(99) { II ii = sbc_a_R<C,0>(); NEXT; }
1136CASE(9A) { II ii = sbc_a_R<D,0>(); NEXT; }
1137CASE(9B) { II ii = sbc_a_R<E,0>(); NEXT; }
1138CASE(9C) { II ii = sbc_a_R<H,0>(); NEXT; }
1139CASE(9D) { II ii = sbc_a_R<L,0>(); NEXT; }
1140CASE(9E) { II ii = sbc_a_xhl(); NEXT; }
1141CASE(9F) { II ii = sbc_a_a(); NEXT; }
1142CASE(A0) { II ii = and_R<B,0>(); NEXT; }
1143CASE(A1) { II ii = and_R<C,0>(); NEXT; }
1144CASE(A2) { II ii = and_R<D,0>(); NEXT; }
1145CASE(A3) { II ii = and_R<E,0>(); NEXT; }
1146CASE(A4) { II ii = and_R<H,0>(); NEXT; }
1147CASE(A5) { II ii = and_R<L,0>(); NEXT; }
1148CASE(A6) { II ii = and_xhl(); NEXT; }
1149CASE(A7) { II ii = and_a(); NEXT; }
1150CASE(A8) { II ii = xor_R<B,0>(); NEXT; }
1151CASE(A9) { II ii = xor_R<C,0>(); NEXT; }
1152CASE(AA) { II ii = xor_R<D,0>(); NEXT; }
1153CASE(AB) { II ii = xor_R<E,0>(); NEXT; }
1154CASE(AC) { II ii = xor_R<H,0>(); NEXT; }
1155CASE(AD) { II ii = xor_R<L,0>(); NEXT; }
1156CASE(AE) { II ii = xor_xhl(); NEXT; }
1157CASE(AF) { II ii = xor_a(); NEXT; }
1158CASE(B0) { II ii = or_R<B,0>(); NEXT; }
1159CASE(B1) { II ii = or_R<C,0>(); NEXT; }
1160CASE(B2) { II ii = or_R<D,0>(); NEXT; }
1161CASE(B3) { II ii = or_R<E,0>(); NEXT; }
1162CASE(B4) { II ii = or_R<H,0>(); NEXT; }
1163CASE(B5) { II ii = or_R<L,0>(); NEXT; }
1164CASE(B6) { II ii = or_xhl(); NEXT; }
1165CASE(B7) { II ii = or_a(); NEXT; }
1166CASE(B8) { II ii = cp_R<B,0>(); NEXT; }
1167CASE(B9) { II ii = cp_R<C,0>(); NEXT; }
1168CASE(BA) { II ii = cp_R<D,0>(); NEXT; }
1169CASE(BB) { II ii = cp_R<E,0>(); NEXT; }
1170CASE(BC) { II ii = cp_R<H,0>(); NEXT; }
1171CASE(BD) { II ii = cp_R<L,0>(); NEXT; }
1172CASE(BE) { II ii = cp_xhl(); NEXT; }
1173CASE(BF) { II ii = cp_a(); NEXT; }
1174
1175CASE(D3) { II ii = out_byte_a(); NEXT; }
1176CASE(DB) { II ii = in_a_byte(); NEXT; }
1177CASE(D9) { II ii = exx(); NEXT; }
1178CASE(E3) { II ii = ex_xsp_SS<HL,0>(); NEXT; }
1179CASE(EB) { II ii = ex_de_hl(); NEXT; }
1180CASE(E9) { II ii = jp_SS<HL,0>(); NEXT; }
1181CASE(F9) { II ii = ld_sp_SS<HL,0>(); NEXT; }
1182CASE(F3) { II ii = di(); NEXT; }
1183CASE(FB) { II ii = ei(); NEXT_EI; }
1184CASE(C6) { II ii = add_a_byte(); NEXT; }
1185CASE(CE) { II ii = adc_a_byte(); NEXT; }
1186CASE(D6) { II ii = sub_byte(); NEXT; }
1187CASE(DE) { II ii = sbc_a_byte(); NEXT; }
1188CASE(E6) { II ii = and_byte(); NEXT; }
1189CASE(EE) { II ii = xor_byte(); NEXT; }
1190CASE(F6) { II ii = or_byte(); NEXT; }
1191CASE(FE) { II ii = cp_byte(); NEXT; }
1192CASE(C0) { II ii = ret(CondNZ()); NEXT; }
1193CASE(C8) { II ii = ret(CondZ ()); NEXT; }
1194CASE(D0) { II ii = ret(CondNC()); NEXT; }
1195CASE(D8) { II ii = ret(CondC ()); NEXT; }
1196CASE(E0) { II ii = ret(CondPO()); NEXT; }
1197CASE(E8) { II ii = ret(CondPE()); NEXT; }
1198CASE(F0) { II ii = ret(CondP ()); NEXT; }
1199CASE(F8) { II ii = ret(CondM ()); NEXT; }
1200CASE(C9) { II ii = ret(); NEXT; }
1201CASE(C2) { II ii = jp(CondNZ()); NEXT; }
1202CASE(CA) { II ii = jp(CondZ ()); NEXT; }
1203CASE(D2) { II ii = jp(CondNC()); NEXT; }
1204CASE(DA) { II ii = jp(CondC ()); NEXT; }
1205CASE(E2) { II ii = jp(CondPO()); NEXT; }
1206CASE(EA) { II ii = jp(CondPE()); NEXT; }
1207CASE(F2) { II ii = jp(CondP ()); NEXT; }
1208CASE(FA) { II ii = jp(CondM ()); NEXT; }
1209CASE(C3) { II ii = jp(CondTrue()); NEXT; }
1210CASE(C4) { II ii = call(CondNZ()); NEXT; }
1211CASE(CC) { II ii = call(CondZ ()); NEXT; }
1212CASE(D4) { II ii = call(CondNC()); NEXT; }
1213CASE(DC) { II ii = call(CondC ()); NEXT; }
1214CASE(E4) { II ii = call(CondPO()); NEXT; }
1215CASE(EC) { II ii = call(CondPE()); NEXT; }
1216CASE(F4) { II ii = call(CondP ()); NEXT; }
1217CASE(FC) { II ii = call(CondM ()); NEXT; }
1218CASE(CD) { II ii = call(CondTrue()); NEXT; }
1219CASE(C1) { II ii = pop_SS <BC,0>(); NEXT; }
1220CASE(D1) { II ii = pop_SS <DE,0>(); NEXT; }
1221CASE(E1) { II ii = pop_SS <HL,0>(); NEXT; }
1222CASE(F1) { II ii = pop_SS <AF,0>(); NEXT; }
1223CASE(C5) { II ii = push_SS<BC,0>(); NEXT; }
1224CASE(D5) { II ii = push_SS<DE,0>(); NEXT; }
1225CASE(E5) { II ii = push_SS<HL,0>(); NEXT; }
1226CASE(F5) { II ii = push_SS<AF,0>(); NEXT; }
1227CASE(C7) { II ii = rst<0x00>(); NEXT; }
1228CASE(CF) { II ii = rst<0x08>(); NEXT; }
1229CASE(D7) { II ii = rst<0x10>(); NEXT; }
1230CASE(DF) { II ii = rst<0x18>(); NEXT; }
1231CASE(E7) { II ii = rst<0x20>(); NEXT; }
1232CASE(EF) { II ii = rst<0x28>(); NEXT; }
1233CASE(F7) { II ii = rst<0x30>(); NEXT; }
1234CASE(FF) { II ii = rst<0x38>(); NEXT; }
1235CASE(CB) {
1236 setPC(getPC() + 1); // M1 cycle at this point
1237 byte cb_opcode = RDMEM_OPCODE<0>(T::CC_PREFIX);
1238 incR(1);
1239 switch (cb_opcode) {
1240 case 0x00: { II ii = rlc_R<B>(); NEXT; }
1241 case 0x01: { II ii = rlc_R<C>(); NEXT; }
1242 case 0x02: { II ii = rlc_R<D>(); NEXT; }
1243 case 0x03: { II ii = rlc_R<E>(); NEXT; }
1244 case 0x04: { II ii = rlc_R<H>(); NEXT; }
1245 case 0x05: { II ii = rlc_R<L>(); NEXT; }
1246 case 0x07: { II ii = rlc_R<A>(); NEXT; }
1247 case 0x06: { II ii = rlc_xhl(); NEXT; }
1248 case 0x08: { II ii = rrc_R<B>(); NEXT; }
1249 case 0x09: { II ii = rrc_R<C>(); NEXT; }
1250 case 0x0a: { II ii = rrc_R<D>(); NEXT; }
1251 case 0x0b: { II ii = rrc_R<E>(); NEXT; }
1252 case 0x0c: { II ii = rrc_R<H>(); NEXT; }
1253 case 0x0d: { II ii = rrc_R<L>(); NEXT; }
1254 case 0x0f: { II ii = rrc_R<A>(); NEXT; }
1255 case 0x0e: { II ii = rrc_xhl(); NEXT; }
1256 case 0x10: { II ii = rl_R<B>(); NEXT; }
1257 case 0x11: { II ii = rl_R<C>(); NEXT; }
1258 case 0x12: { II ii = rl_R<D>(); NEXT; }
1259 case 0x13: { II ii = rl_R<E>(); NEXT; }
1260 case 0x14: { II ii = rl_R<H>(); NEXT; }
1261 case 0x15: { II ii = rl_R<L>(); NEXT; }
1262 case 0x17: { II ii = rl_R<A>(); NEXT; }
1263 case 0x16: { II ii = rl_xhl(); NEXT; }
1264 case 0x18: { II ii = rr_R<B>(); NEXT; }
1265 case 0x19: { II ii = rr_R<C>(); NEXT; }
1266 case 0x1a: { II ii = rr_R<D>(); NEXT; }
1267 case 0x1b: { II ii = rr_R<E>(); NEXT; }
1268 case 0x1c: { II ii = rr_R<H>(); NEXT; }
1269 case 0x1d: { II ii = rr_R<L>(); NEXT; }
1270 case 0x1f: { II ii = rr_R<A>(); NEXT; }
1271 case 0x1e: { II ii = rr_xhl(); NEXT; }
1272 case 0x20: { II ii = sla_R<B>(); NEXT; }
1273 case 0x21: { II ii = sla_R<C>(); NEXT; }
1274 case 0x22: { II ii = sla_R<D>(); NEXT; }
1275 case 0x23: { II ii = sla_R<E>(); NEXT; }
1276 case 0x24: { II ii = sla_R<H>(); NEXT; }
1277 case 0x25: { II ii = sla_R<L>(); NEXT; }
1278 case 0x27: { II ii = sla_R<A>(); NEXT; }
1279 case 0x26: { II ii = sla_xhl(); NEXT; }
1280 case 0x28: { II ii = sra_R<B>(); NEXT; }
1281 case 0x29: { II ii = sra_R<C>(); NEXT; }
1282 case 0x2a: { II ii = sra_R<D>(); NEXT; }
1283 case 0x2b: { II ii = sra_R<E>(); NEXT; }
1284 case 0x2c: { II ii = sra_R<H>(); NEXT; }
1285 case 0x2d: { II ii = sra_R<L>(); NEXT; }
1286 case 0x2f: { II ii = sra_R<A>(); NEXT; }
1287 case 0x2e: { II ii = sra_xhl(); NEXT; }
1288 case 0x30: { II ii = T::IS_R800 ? sla_R<B>() : sll_R<B>(); NEXT; }
1289 case 0x31: { II ii = T::IS_R800 ? sla_R<C>() : sll_R<C>(); NEXT; }
1290 case 0x32: { II ii = T::IS_R800 ? sla_R<D>() : sll_R<D>(); NEXT; }
1291 case 0x33: { II ii = T::IS_R800 ? sla_R<E>() : sll_R<E>(); NEXT; }
1292 case 0x34: { II ii = T::IS_R800 ? sla_R<H>() : sll_R<H>(); NEXT; }
1293 case 0x35: { II ii = T::IS_R800 ? sla_R<L>() : sll_R<L>(); NEXT; }
1294 case 0x37: { II ii = T::IS_R800 ? sla_R<A>() : sll_R<A>(); NEXT; }
1295 case 0x36: { II ii = T::IS_R800 ? sla_xhl() : sll_xhl(); NEXT; }
1296 case 0x38: { II ii = srl_R<B>(); NEXT; }
1297 case 0x39: { II ii = srl_R<C>(); NEXT; }
1298 case 0x3a: { II ii = srl_R<D>(); NEXT; }
1299 case 0x3b: { II ii = srl_R<E>(); NEXT; }
1300 case 0x3c: { II ii = srl_R<H>(); NEXT; }
1301 case 0x3d: { II ii = srl_R<L>(); NEXT; }
1302 case 0x3f: { II ii = srl_R<A>(); NEXT; }
1303 case 0x3e: { II ii = srl_xhl(); NEXT; }
1304
1305 case 0x40: { II ii = bit_N_R<0,B>(); NEXT; }
1306 case 0x41: { II ii = bit_N_R<0,C>(); NEXT; }
1307 case 0x42: { II ii = bit_N_R<0,D>(); NEXT; }
1308 case 0x43: { II ii = bit_N_R<0,E>(); NEXT; }
1309 case 0x44: { II ii = bit_N_R<0,H>(); NEXT; }
1310 case 0x45: { II ii = bit_N_R<0,L>(); NEXT; }
1311 case 0x47: { II ii = bit_N_R<0,A>(); NEXT; }
1312 case 0x48: { II ii = bit_N_R<1,B>(); NEXT; }
1313 case 0x49: { II ii = bit_N_R<1,C>(); NEXT; }
1314 case 0x4a: { II ii = bit_N_R<1,D>(); NEXT; }
1315 case 0x4b: { II ii = bit_N_R<1,E>(); NEXT; }
1316 case 0x4c: { II ii = bit_N_R<1,H>(); NEXT; }
1317 case 0x4d: { II ii = bit_N_R<1,L>(); NEXT; }
1318 case 0x4f: { II ii = bit_N_R<1,A>(); NEXT; }
1319 case 0x50: { II ii = bit_N_R<2,B>(); NEXT; }
1320 case 0x51: { II ii = bit_N_R<2,C>(); NEXT; }
1321 case 0x52: { II ii = bit_N_R<2,D>(); NEXT; }
1322 case 0x53: { II ii = bit_N_R<2,E>(); NEXT; }
1323 case 0x54: { II ii = bit_N_R<2,H>(); NEXT; }
1324 case 0x55: { II ii = bit_N_R<2,L>(); NEXT; }
1325 case 0x57: { II ii = bit_N_R<2,A>(); NEXT; }
1326 case 0x58: { II ii = bit_N_R<3,B>(); NEXT; }
1327 case 0x59: { II ii = bit_N_R<3,C>(); NEXT; }
1328 case 0x5a: { II ii = bit_N_R<3,D>(); NEXT; }
1329 case 0x5b: { II ii = bit_N_R<3,E>(); NEXT; }
1330 case 0x5c: { II ii = bit_N_R<3,H>(); NEXT; }
1331 case 0x5d: { II ii = bit_N_R<3,L>(); NEXT; }
1332 case 0x5f: { II ii = bit_N_R<3,A>(); NEXT; }
1333 case 0x60: { II ii = bit_N_R<4,B>(); NEXT; }
1334 case 0x61: { II ii = bit_N_R<4,C>(); NEXT; }
1335 case 0x62: { II ii = bit_N_R<4,D>(); NEXT; }
1336 case 0x63: { II ii = bit_N_R<4,E>(); NEXT; }
1337 case 0x64: { II ii = bit_N_R<4,H>(); NEXT; }
1338 case 0x65: { II ii = bit_N_R<4,L>(); NEXT; }
1339 case 0x67: { II ii = bit_N_R<4,A>(); NEXT; }
1340 case 0x68: { II ii = bit_N_R<5,B>(); NEXT; }
1341 case 0x69: { II ii = bit_N_R<5,C>(); NEXT; }
1342 case 0x6a: { II ii = bit_N_R<5,D>(); NEXT; }
1343 case 0x6b: { II ii = bit_N_R<5,E>(); NEXT; }
1344 case 0x6c: { II ii = bit_N_R<5,H>(); NEXT; }
1345 case 0x6d: { II ii = bit_N_R<5,L>(); NEXT; }
1346 case 0x6f: { II ii = bit_N_R<5,A>(); NEXT; }
1347 case 0x70: { II ii = bit_N_R<6,B>(); NEXT; }
1348 case 0x71: { II ii = bit_N_R<6,C>(); NEXT; }
1349 case 0x72: { II ii = bit_N_R<6,D>(); NEXT; }
1350 case 0x73: { II ii = bit_N_R<6,E>(); NEXT; }
1351 case 0x74: { II ii = bit_N_R<6,H>(); NEXT; }
1352 case 0x75: { II ii = bit_N_R<6,L>(); NEXT; }
1353 case 0x77: { II ii = bit_N_R<6,A>(); NEXT; }
1354 case 0x78: { II ii = bit_N_R<7,B>(); NEXT; }
1355 case 0x79: { II ii = bit_N_R<7,C>(); NEXT; }
1356 case 0x7a: { II ii = bit_N_R<7,D>(); NEXT; }
1357 case 0x7b: { II ii = bit_N_R<7,E>(); NEXT; }
1358 case 0x7c: { II ii = bit_N_R<7,H>(); NEXT; }
1359 case 0x7d: { II ii = bit_N_R<7,L>(); NEXT; }
1360 case 0x7f: { II ii = bit_N_R<7,A>(); NEXT; }
1361 case 0x46: { II ii = bit_N_xhl<0>(); NEXT; }
1362 case 0x4e: { II ii = bit_N_xhl<1>(); NEXT; }
1363 case 0x56: { II ii = bit_N_xhl<2>(); NEXT; }
1364 case 0x5e: { II ii = bit_N_xhl<3>(); NEXT; }
1365 case 0x66: { II ii = bit_N_xhl<4>(); NEXT; }
1366 case 0x6e: { II ii = bit_N_xhl<5>(); NEXT; }
1367 case 0x76: { II ii = bit_N_xhl<6>(); NEXT; }
1368 case 0x7e: { II ii = bit_N_xhl<7>(); NEXT; }
1369
1370 case 0x80: { II ii = res_N_R<0,B>(); NEXT; }
1371 case 0x81: { II ii = res_N_R<0,C>(); NEXT; }
1372 case 0x82: { II ii = res_N_R<0,D>(); NEXT; }
1373 case 0x83: { II ii = res_N_R<0,E>(); NEXT; }
1374 case 0x84: { II ii = res_N_R<0,H>(); NEXT; }
1375 case 0x85: { II ii = res_N_R<0,L>(); NEXT; }
1376 case 0x87: { II ii = res_N_R<0,A>(); NEXT; }
1377 case 0x88: { II ii = res_N_R<1,B>(); NEXT; }
1378 case 0x89: { II ii = res_N_R<1,C>(); NEXT; }
1379 case 0x8a: { II ii = res_N_R<1,D>(); NEXT; }
1380 case 0x8b: { II ii = res_N_R<1,E>(); NEXT; }
1381 case 0x8c: { II ii = res_N_R<1,H>(); NEXT; }
1382 case 0x8d: { II ii = res_N_R<1,L>(); NEXT; }
1383 case 0x8f: { II ii = res_N_R<1,A>(); NEXT; }
1384 case 0x90: { II ii = res_N_R<2,B>(); NEXT; }
1385 case 0x91: { II ii = res_N_R<2,C>(); NEXT; }
1386 case 0x92: { II ii = res_N_R<2,D>(); NEXT; }
1387 case 0x93: { II ii = res_N_R<2,E>(); NEXT; }
1388 case 0x94: { II ii = res_N_R<2,H>(); NEXT; }
1389 case 0x95: { II ii = res_N_R<2,L>(); NEXT; }
1390 case 0x97: { II ii = res_N_R<2,A>(); NEXT; }
1391 case 0x98: { II ii = res_N_R<3,B>(); NEXT; }
1392 case 0x99: { II ii = res_N_R<3,C>(); NEXT; }
1393 case 0x9a: { II ii = res_N_R<3,D>(); NEXT; }
1394 case 0x9b: { II ii = res_N_R<3,E>(); NEXT; }
1395 case 0x9c: { II ii = res_N_R<3,H>(); NEXT; }
1396 case 0x9d: { II ii = res_N_R<3,L>(); NEXT; }
1397 case 0x9f: { II ii = res_N_R<3,A>(); NEXT; }
1398 case 0xa0: { II ii = res_N_R<4,B>(); NEXT; }
1399 case 0xa1: { II ii = res_N_R<4,C>(); NEXT; }
1400 case 0xa2: { II ii = res_N_R<4,D>(); NEXT; }
1401 case 0xa3: { II ii = res_N_R<4,E>(); NEXT; }
1402 case 0xa4: { II ii = res_N_R<4,H>(); NEXT; }
1403 case 0xa5: { II ii = res_N_R<4,L>(); NEXT; }
1404 case 0xa7: { II ii = res_N_R<4,A>(); NEXT; }
1405 case 0xa8: { II ii = res_N_R<5,B>(); NEXT; }
1406 case 0xa9: { II ii = res_N_R<5,C>(); NEXT; }
1407 case 0xaa: { II ii = res_N_R<5,D>(); NEXT; }
1408 case 0xab: { II ii = res_N_R<5,E>(); NEXT; }
1409 case 0xac: { II ii = res_N_R<5,H>(); NEXT; }
1410 case 0xad: { II ii = res_N_R<5,L>(); NEXT; }
1411 case 0xaf: { II ii = res_N_R<5,A>(); NEXT; }
1412 case 0xb0: { II ii = res_N_R<6,B>(); NEXT; }
1413 case 0xb1: { II ii = res_N_R<6,C>(); NEXT; }
1414 case 0xb2: { II ii = res_N_R<6,D>(); NEXT; }
1415 case 0xb3: { II ii = res_N_R<6,E>(); NEXT; }
1416 case 0xb4: { II ii = res_N_R<6,H>(); NEXT; }
1417 case 0xb5: { II ii = res_N_R<6,L>(); NEXT; }
1418 case 0xb7: { II ii = res_N_R<6,A>(); NEXT; }
1419 case 0xb8: { II ii = res_N_R<7,B>(); NEXT; }
1420 case 0xb9: { II ii = res_N_R<7,C>(); NEXT; }
1421 case 0xba: { II ii = res_N_R<7,D>(); NEXT; }
1422 case 0xbb: { II ii = res_N_R<7,E>(); NEXT; }
1423 case 0xbc: { II ii = res_N_R<7,H>(); NEXT; }
1424 case 0xbd: { II ii = res_N_R<7,L>(); NEXT; }
1425 case 0xbf: { II ii = res_N_R<7,A>(); NEXT; }
1426 case 0x86: { II ii = res_N_xhl<0>(); NEXT; }
1427 case 0x8e: { II ii = res_N_xhl<1>(); NEXT; }
1428 case 0x96: { II ii = res_N_xhl<2>(); NEXT; }
1429 case 0x9e: { II ii = res_N_xhl<3>(); NEXT; }
1430 case 0xa6: { II ii = res_N_xhl<4>(); NEXT; }
1431 case 0xae: { II ii = res_N_xhl<5>(); NEXT; }
1432 case 0xb6: { II ii = res_N_xhl<6>(); NEXT; }
1433 case 0xbe: { II ii = res_N_xhl<7>(); NEXT; }
1434
1435 case 0xc0: { II ii = set_N_R<0,B>(); NEXT; }
1436 case 0xc1: { II ii = set_N_R<0,C>(); NEXT; }
1437 case 0xc2: { II ii = set_N_R<0,D>(); NEXT; }
1438 case 0xc3: { II ii = set_N_R<0,E>(); NEXT; }
1439 case 0xc4: { II ii = set_N_R<0,H>(); NEXT; }
1440 case 0xc5: { II ii = set_N_R<0,L>(); NEXT; }
1441 case 0xc7: { II ii = set_N_R<0,A>(); NEXT; }
1442 case 0xc8: { II ii = set_N_R<1,B>(); NEXT; }
1443 case 0xc9: { II ii = set_N_R<1,C>(); NEXT; }
1444 case 0xca: { II ii = set_N_R<1,D>(); NEXT; }
1445 case 0xcb: { II ii = set_N_R<1,E>(); NEXT; }
1446 case 0xcc: { II ii = set_N_R<1,H>(); NEXT; }
1447 case 0xcd: { II ii = set_N_R<1,L>(); NEXT; }
1448 case 0xcf: { II ii = set_N_R<1,A>(); NEXT; }
1449 case 0xd0: { II ii = set_N_R<2,B>(); NEXT; }
1450 case 0xd1: { II ii = set_N_R<2,C>(); NEXT; }
1451 case 0xd2: { II ii = set_N_R<2,D>(); NEXT; }
1452 case 0xd3: { II ii = set_N_R<2,E>(); NEXT; }
1453 case 0xd4: { II ii = set_N_R<2,H>(); NEXT; }
1454 case 0xd5: { II ii = set_N_R<2,L>(); NEXT; }
1455 case 0xd7: { II ii = set_N_R<2,A>(); NEXT; }
1456 case 0xd8: { II ii = set_N_R<3,B>(); NEXT; }
1457 case 0xd9: { II ii = set_N_R<3,C>(); NEXT; }
1458 case 0xda: { II ii = set_N_R<3,D>(); NEXT; }
1459 case 0xdb: { II ii = set_N_R<3,E>(); NEXT; }
1460 case 0xdc: { II ii = set_N_R<3,H>(); NEXT; }
1461 case 0xdd: { II ii = set_N_R<3,L>(); NEXT; }
1462 case 0xdf: { II ii = set_N_R<3,A>(); NEXT; }
1463 case 0xe0: { II ii = set_N_R<4,B>(); NEXT; }
1464 case 0xe1: { II ii = set_N_R<4,C>(); NEXT; }
1465 case 0xe2: { II ii = set_N_R<4,D>(); NEXT; }
1466 case 0xe3: { II ii = set_N_R<4,E>(); NEXT; }
1467 case 0xe4: { II ii = set_N_R<4,H>(); NEXT; }
1468 case 0xe5: { II ii = set_N_R<4,L>(); NEXT; }
1469 case 0xe7: { II ii = set_N_R<4,A>(); NEXT; }
1470 case 0xe8: { II ii = set_N_R<5,B>(); NEXT; }
1471 case 0xe9: { II ii = set_N_R<5,C>(); NEXT; }
1472 case 0xea: { II ii = set_N_R<5,D>(); NEXT; }
1473 case 0xeb: { II ii = set_N_R<5,E>(); NEXT; }
1474 case 0xec: { II ii = set_N_R<5,H>(); NEXT; }
1475 case 0xed: { II ii = set_N_R<5,L>(); NEXT; }
1476 case 0xef: { II ii = set_N_R<5,A>(); NEXT; }
1477 case 0xf0: { II ii = set_N_R<6,B>(); NEXT; }
1478 case 0xf1: { II ii = set_N_R<6,C>(); NEXT; }
1479 case 0xf2: { II ii = set_N_R<6,D>(); NEXT; }
1480 case 0xf3: { II ii = set_N_R<6,E>(); NEXT; }
1481 case 0xf4: { II ii = set_N_R<6,H>(); NEXT; }
1482 case 0xf5: { II ii = set_N_R<6,L>(); NEXT; }
1483 case 0xf7: { II ii = set_N_R<6,A>(); NEXT; }
1484 case 0xf8: { II ii = set_N_R<7,B>(); NEXT; }
1485 case 0xf9: { II ii = set_N_R<7,C>(); NEXT; }
1486 case 0xfa: { II ii = set_N_R<7,D>(); NEXT; }
1487 case 0xfb: { II ii = set_N_R<7,E>(); NEXT; }
1488 case 0xfc: { II ii = set_N_R<7,H>(); NEXT; }
1489 case 0xfd: { II ii = set_N_R<7,L>(); NEXT; }
1490 case 0xff: { II ii = set_N_R<7,A>(); NEXT; }
1491 case 0xc6: { II ii = set_N_xhl<0>(); NEXT; }
1492 case 0xce: { II ii = set_N_xhl<1>(); NEXT; }
1493 case 0xd6: { II ii = set_N_xhl<2>(); NEXT; }
1494 case 0xde: { II ii = set_N_xhl<3>(); NEXT; }
1495 case 0xe6: { II ii = set_N_xhl<4>(); NEXT; }
1496 case 0xee: { II ii = set_N_xhl<5>(); NEXT; }
1497 case 0xf6: { II ii = set_N_xhl<6>(); NEXT; }
1498 case 0xfe: { II ii = set_N_xhl<7>(); NEXT; }
1499 default: UNREACHABLE;
1500 }
1501}
1502CASE(ED) {
1503 setPC(getPC() + 1); // M1 cycle at this point
1504 byte ed_opcode = RDMEM_OPCODE<0>(T::CC_PREFIX);
1505 incR(1);
1506 switch (ed_opcode) {
1507 case 0x00: case 0x01: case 0x02: case 0x03:
1508 case 0x04: case 0x05: case 0x06: case 0x07:
1509 case 0x08: case 0x09: case 0x0a: case 0x0b:
1510 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1511 case 0x10: case 0x11: case 0x12: case 0x13:
1512 case 0x14: case 0x15: case 0x16: case 0x17:
1513 case 0x18: case 0x19: case 0x1a: case 0x1b:
1514 case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1515 case 0x20: case 0x21: case 0x22: case 0x23:
1516 case 0x24: case 0x25: case 0x26: case 0x27:
1517 case 0x28: case 0x29: case 0x2a: case 0x2b:
1518 case 0x2c: case 0x2d: case 0x2e: case 0x2f:
1519 case 0x30: case 0x31: case 0x32: case 0x33:
1520 case 0x34: case 0x35: case 0x36: case 0x37:
1521 case 0x38: case 0x39: case 0x3a: case 0x3b:
1522 case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1523
1524 case 0x77: case 0x7f:
1525
1526 case 0x80: case 0x81: case 0x82: case 0x83:
1527 case 0x84: case 0x85: case 0x86: case 0x87:
1528 case 0x88: case 0x89: case 0x8a: case 0x8b:
1529 case 0x8c: case 0x8d: case 0x8e: case 0x8f:
1530 case 0x90: case 0x91: case 0x92: case 0x93:
1531 case 0x94: case 0x95: case 0x96: case 0x97:
1532 case 0x98: case 0x99: case 0x9a: case 0x9b:
1533 case 0x9c: case 0x9d: case 0x9e: case 0x9f:
1534 case 0xa4: case 0xa5: case 0xa6: case 0xa7:
1535 case 0xac: case 0xad: case 0xae: case 0xaf:
1536 case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1537 case 0xbc: case 0xbd: case 0xbe: case 0xbf:
1538
1539 case 0xc0: case 0xc2:
1540 case 0xc4: case 0xc5: case 0xc6: case 0xc7:
1541 case 0xc8: case 0xca: case 0xcb:
1542 case 0xcc: case 0xcd: case 0xce: case 0xcf:
1543 case 0xd0: case 0xd2: case 0xd3:
1544 case 0xd4: case 0xd5: case 0xd6: case 0xd7:
1545 case 0xd8: case 0xda: case 0xdb:
1546 case 0xdc: case 0xdd: case 0xde: case 0xdf:
1547 case 0xe0: case 0xe1: case 0xe2: case 0xe3:
1548 case 0xe4: case 0xe5: case 0xe6: case 0xe7:
1549 case 0xe8: case 0xe9: case 0xea: case 0xeb:
1550 case 0xec: case 0xed: case 0xee: case 0xef:
1551 case 0xf0: case 0xf1: case 0xf2:
1552 case 0xf4: case 0xf5: case 0xf6: case 0xf7:
1553 case 0xf8: case 0xf9: case 0xfa: case 0xfb:
1554 case 0xfc: case 0xfd: case 0xfe: case 0xff:
1555 { II ii = nop(); NEXT; }
1556
1557 case 0x40: { II ii = in_R_c<B>(); NEXT; }
1558 case 0x48: { II ii = in_R_c<C>(); NEXT; }
1559 case 0x50: { II ii = in_R_c<D>(); NEXT; }
1560 case 0x58: { II ii = in_R_c<E>(); NEXT; }
1561 case 0x60: { II ii = in_R_c<H>(); NEXT; }
1562 case 0x68: { II ii = in_R_c<L>(); NEXT; }
1563 case 0x70: { II ii = in_R_c<DUMMY>(); NEXT; }
1564 case 0x78: { II ii = in_R_c<A>(); NEXT; }
1565
1566 case 0x41: { II ii = out_c_R<B>(); NEXT; }
1567 case 0x49: { II ii = out_c_R<C>(); NEXT; }
1568 case 0x51: { II ii = out_c_R<D>(); NEXT; }
1569 case 0x59: { II ii = out_c_R<E>(); NEXT; }
1570 case 0x61: { II ii = out_c_R<H>(); NEXT; }
1571 case 0x69: { II ii = out_c_R<L>(); NEXT; }
1572 case 0x71: { II ii = out_c_0(); NEXT; }
1573 case 0x79: { II ii = out_c_R<A>(); NEXT; }
1574
1575 case 0x42: { II ii = sbc_hl_SS<BC>(); NEXT; }
1576 case 0x52: { II ii = sbc_hl_SS<DE>(); NEXT; }
1577 case 0x62: { II ii = sbc_hl_hl (); NEXT; }
1578 case 0x72: { II ii = sbc_hl_SS<SP>(); NEXT; }
1579
1580 case 0x4a: { II ii = adc_hl_SS<BC>(); NEXT; }
1581 case 0x5a: { II ii = adc_hl_SS<DE>(); NEXT; }
1582 case 0x6a: { II ii = adc_hl_hl (); NEXT; }
1583 case 0x7a: { II ii = adc_hl_SS<SP>(); NEXT; }
1584
1585 case 0x43: { II ii = ld_xword_SS_ED<BC>(); NEXT; }
1586 case 0x53: { II ii = ld_xword_SS_ED<DE>(); NEXT; }
1587 case 0x63: { II ii = ld_xword_SS_ED<HL>(); NEXT; }
1588 case 0x73: { II ii = ld_xword_SS_ED<SP>(); NEXT; }
1589
1590 case 0x4b: { II ii = ld_SS_xword_ED<BC>(); NEXT; }
1591 case 0x5b: { II ii = ld_SS_xword_ED<DE>(); NEXT; }
1592 case 0x6b: { II ii = ld_SS_xword_ED<HL>(); NEXT; }
1593 case 0x7b: { II ii = ld_SS_xword_ED<SP>(); NEXT; }
1594
1595 case 0x47: { II ii = ld_i_a(); NEXT; }
1596 case 0x4f: { II ii = ld_r_a(); NEXT; }
1597 case 0x57: { II ii = ld_a_IR<REG_I>(); if (T::IS_R800) { NEXT; } else { NEXT_STOP; }}
1598 case 0x5f: { II ii = ld_a_IR<REG_R>(); if (T::IS_R800) { NEXT; } else { NEXT_STOP; }}
1599
1600 case 0x67: { II ii = rrd(); NEXT; }
1601 case 0x6f: { II ii = rld(); NEXT; }
1602
1603 case 0x45: case 0x4d: case 0x55: case 0x5d:
1604 case 0x65: case 0x6d: case 0x75: case 0x7d:
1605 { II ii = retn(); NEXT_STOP; }
1606 case 0x46: case 0x4e: case 0x66: case 0x6e:
1607 { II ii = im_N<0>(); NEXT; }
1608 case 0x56: case 0x76:
1609 { II ii = im_N<1>(); NEXT; }
1610 case 0x5e: case 0x7e:
1611 { II ii = im_N<2>(); NEXT; }
1612 case 0x44: case 0x4c: case 0x54: case 0x5c:
1613 case 0x64: case 0x6c: case 0x74: case 0x7c:
1614 { II ii = neg(); NEXT; }
1615
1616 case 0xa0: { II ii = ldi(); NEXT; }
1617 case 0xa1: { II ii = cpi(); NEXT; }
1618 case 0xa2: { II ii = ini(); NEXT; }
1619 case 0xa3: { II ii = outi(); NEXT; }
1620 case 0xa8: { II ii = ldd(); NEXT; }
1621 case 0xa9: { II ii = cpd(); NEXT; }
1622 case 0xaa: { II ii = ind(); NEXT; }
1623 case 0xab: { II ii = outd(); NEXT; }
1624 case 0xb0: { II ii = ldir(); NEXT; }
1625 case 0xb1: { II ii = cpir(); NEXT; }
1626 case 0xb2: { II ii = inir(); NEXT; }
1627 case 0xb3: { II ii = otir(); NEXT; }
1628 case 0xb8: { II ii = lddr(); NEXT; }
1629 case 0xb9: { II ii = cpdr(); NEXT; }
1630 case 0xba: { II ii = indr(); NEXT; }
1631 case 0xbb: { II ii = otdr(); NEXT; }
1632
1633 case 0xc1: { II ii = T::IS_R800 ? mulub_a_R<B>() : nop(); NEXT; }
1634 case 0xc9: { II ii = T::IS_R800 ? mulub_a_R<C>() : nop(); NEXT; }
1635 case 0xd1: { II ii = T::IS_R800 ? mulub_a_R<D>() : nop(); NEXT; }
1636 case 0xd9: { II ii = T::IS_R800 ? mulub_a_R<E>() : nop(); NEXT; }
1637 case 0xc3: { II ii = T::IS_R800 ? muluw_hl_SS<BC>() : nop(); NEXT; }
1638 case 0xf3: { II ii = T::IS_R800 ? muluw_hl_SS<SP>() : nop(); NEXT; }
1639 default: UNREACHABLE;
1640 }
1641}
1642MAYBE_UNUSED_LABEL opDD_2:
1643CASE(DD) {
1644 setPC(getPC() + 1); // M1 cycle at this point
1645 byte opcodeDD = RDMEM_OPCODE<0>(T::CC_DD + T::CC_MAIN);
1646 incR(1);
1647 switch (opcodeDD) {
1648 case 0x00: // nop();
1649 case 0x01: // ld_bc_word();
1650 case 0x02: // ld_xbc_a();
1651 case 0x03: // inc_bc();
1652 case 0x04: // inc_b();
1653 case 0x05: // dec_b();
1654 case 0x06: // ld_b_byte();
1655 case 0x07: // rlca();
1656 case 0x08: // ex_af_af();
1657 case 0x0a: // ld_a_xbc();
1658 case 0x0b: // dec_bc();
1659 case 0x0c: // inc_c();
1660 case 0x0d: // dec_c();
1661 case 0x0e: // ld_c_byte();
1662 case 0x0f: // rrca();
1663 case 0x10: // djnz();
1664 case 0x11: // ld_de_word();
1665 case 0x12: // ld_xde_a();
1666 case 0x13: // inc_de();
1667 case 0x14: // inc_d();
1668 case 0x15: // dec_d();
1669 case 0x16: // ld_d_byte();
1670 case 0x17: // rla();
1671 case 0x18: // jr();
1672 case 0x1a: // ld_a_xde();
1673 case 0x1b: // dec_de();
1674 case 0x1c: // inc_e();
1675 case 0x1d: // dec_e();
1676 case 0x1e: // ld_e_byte();
1677 case 0x1f: // rra();
1678 case 0x20: // jr_nz();
1679 case 0x27: // daa();
1680 case 0x28: // jr_z();
1681 case 0x2f: // cpl();
1682 case 0x30: // jr_nc();
1683 case 0x31: // ld_sp_word();
1684 case 0x32: // ld_xbyte_a();
1685 case 0x33: // inc_sp();
1686 case 0x37: // scf();
1687 case 0x38: // jr_c();
1688 case 0x3a: // ld_a_xbyte();
1689 case 0x3b: // dec_sp();
1690 case 0x3c: // inc_a();
1691 case 0x3d: // dec_a();
1692 case 0x3e: // ld_a_byte();
1693 case 0x3f: // ccf();
1694
1695 case 0x40: // ld_b_b();
1696 case 0x41: // ld_b_c();
1697 case 0x42: // ld_b_d();
1698 case 0x43: // ld_b_e();
1699 case 0x47: // ld_b_a();
1700 case 0x48: // ld_c_b();
1701 case 0x49: // ld_c_c();
1702 case 0x4a: // ld_c_d();
1703 case 0x4b: // ld_c_e();
1704 case 0x4f: // ld_c_a();
1705 case 0x50: // ld_d_b();
1706 case 0x51: // ld_d_c();
1707 case 0x52: // ld_d_d();
1708 case 0x53: // ld_d_e();
1709 case 0x57: // ld_d_a();
1710 case 0x58: // ld_e_b();
1711 case 0x59: // ld_e_c();
1712 case 0x5a: // ld_e_d();
1713 case 0x5b: // ld_e_e();
1714 case 0x5f: // ld_e_a();
1715 case 0x64: // ld_ixh_ixh(); == nop
1716 case 0x6d: // ld_ixl_ixl(); == nop
1717 case 0x76: // halt();
1718 case 0x78: // ld_a_b();
1719 case 0x79: // ld_a_c();
1720 case 0x7a: // ld_a_d();
1721 case 0x7b: // ld_a_e();
1722 case 0x7f: // ld_a_a();
1723
1724 case 0x80: // add_a_b();
1725 case 0x81: // add_a_c();
1726 case 0x82: // add_a_d();
1727 case 0x83: // add_a_e();
1728 case 0x87: // add_a_a();
1729 case 0x88: // adc_a_b();
1730 case 0x89: // adc_a_c();
1731 case 0x8a: // adc_a_d();
1732 case 0x8b: // adc_a_e();
1733 case 0x8f: // adc_a_a();
1734 case 0x90: // sub_b();
1735 case 0x91: // sub_c();
1736 case 0x92: // sub_d();
1737 case 0x93: // sub_e();
1738 case 0x97: // sub_a();
1739 case 0x98: // sbc_a_b();
1740 case 0x99: // sbc_a_c();
1741 case 0x9a: // sbc_a_d();
1742 case 0x9b: // sbc_a_e();
1743 case 0x9f: // sbc_a_a();
1744 case 0xa0: // and_b();
1745 case 0xa1: // and_c();
1746 case 0xa2: // and_d();
1747 case 0xa3: // and_e();
1748 case 0xa7: // and_a();
1749 case 0xa8: // xor_b();
1750 case 0xa9: // xor_c();
1751 case 0xaa: // xor_d();
1752 case 0xab: // xor_e();
1753 case 0xaf: // xor_a();
1754 case 0xb0: // or_b();
1755 case 0xb1: // or_c();
1756 case 0xb2: // or_d();
1757 case 0xb3: // or_e();
1758 case 0xb7: // or_a();
1759 case 0xb8: // cp_b();
1760 case 0xb9: // cp_c();
1761 case 0xba: // cp_d();
1762 case 0xbb: // cp_e();
1763 case 0xbf: // cp_a();
1764
1765 case 0xc0: // ret_nz();
1766 case 0xc1: // pop_bc();
1767 case 0xc2: // jp_nz();
1768 case 0xc3: // jp();
1769 case 0xc4: // call_nz();
1770 case 0xc5: // push_bc();
1771 case 0xc6: // add_a_byte();
1772 case 0xc7: // rst_00();
1773 case 0xc8: // ret_z();
1774 case 0xc9: // ret();
1775 case 0xca: // jp_z();
1776 case 0xcc: // call_z();
1777 case 0xcd: // call();
1778 case 0xce: // adc_a_byte();
1779 case 0xcf: // rst_08();
1780 case 0xd0: // ret_nc();
1781 case 0xd1: // pop_de();
1782 case 0xd2: // jp_nc();
1783 case 0xd3: // out_byte_a();
1784 case 0xd4: // call_nc();
1785 case 0xd5: // push_de();
1786 case 0xd6: // sub_byte();
1787 case 0xd7: // rst_10();
1788 case 0xd8: // ret_c();
1789 case 0xd9: // exx();
1790 case 0xda: // jp_c();
1791 case 0xdb: // in_a_byte();
1792 case 0xdc: // call_c();
1793 case 0xde: // sbc_a_byte();
1794 case 0xdf: // rst_18();
1795 case 0xe0: // ret_po();
1796 case 0xe2: // jp_po();
1797 case 0xe4: // call_po();
1798 case 0xe6: // and_byte();
1799 case 0xe7: // rst_20();
1800 case 0xe8: // ret_pe();
1801 case 0xea: // jp_pe();
1802 case 0xeb: // ex_de_hl();
1803 case 0xec: // call_pe();
1804 case 0xed: // ed();
1805 case 0xee: // xor_byte();
1806 case 0xef: // rst_28();
1807 case 0xf0: // ret_p();
1808 case 0xf1: // pop_af();
1809 case 0xf2: // jp_p();
1810 case 0xf3: // di();
1811 case 0xf4: // call_p();
1812 case 0xf5: // push_af();
1813 case 0xf6: // or_byte();
1814 case 0xf7: // rst_30();
1815 case 0xf8: // ret_m();
1816 case 0xfa: // jp_m();
1817 case 0xfb: // ei();
1818 case 0xfc: // call_m();
1819 case 0xfe: // cp_byte();
1820 case 0xff: // rst_38();
1821 if constexpr (T::IS_R800) {
1822 II ii = nop<T::CC_DD>(); NEXT;
1823 } else {
1824 T::add(T::CC_DD);
1825 #ifdef USE_COMPUTED_GOTO
1826 goto *(opcodeTable[opcodeDD]);
1827 #else
1828 opcodeMain = opcodeDD;
1829 goto switchOpcode;
1830 #endif
1831 }
1832
1833 case 0x09: { II ii = add_SS_TT<IX,BC,T::CC_DD>(); NEXT; }
1834 case 0x19: { II ii = add_SS_TT<IX,DE,T::CC_DD>(); NEXT; }
1835 case 0x29: { II ii = add_SS_SS<IX ,T::CC_DD>(); NEXT; }
1836 case 0x39: { II ii = add_SS_TT<IX,SP,T::CC_DD>(); NEXT; }
1837 case 0x21: { II ii = ld_SS_word<IX,T::CC_DD>(); NEXT; }
1838 case 0x22: { II ii = ld_xword_SS<IX,T::CC_DD>(); NEXT; }
1839 case 0x2a: { II ii = ld_SS_xword<IX,T::CC_DD>(); NEXT; }
1840 case 0x23: { II ii = inc_SS<IX,T::CC_DD>(); NEXT; }
1841 case 0x2b: { II ii = dec_SS<IX,T::CC_DD>(); NEXT; }
1842 case 0x24: { II ii = inc_R<IXH,T::CC_DD>(); NEXT; }
1843 case 0x2c: { II ii = inc_R<IXL,T::CC_DD>(); NEXT; }
1844 case 0x25: { II ii = dec_R<IXH,T::CC_DD>(); NEXT; }
1845 case 0x2d: { II ii = dec_R<IXL,T::CC_DD>(); NEXT; }
1846 case 0x26: { II ii = ld_R_byte<IXH,T::CC_DD>(); NEXT; }
1847 case 0x2e: { II ii = ld_R_byte<IXL,T::CC_DD>(); NEXT; }
1848 case 0x34: { II ii = inc_xix<IX>(); NEXT; }
1849 case 0x35: { II ii = dec_xix<IX>(); NEXT; }
1850 case 0x36: { II ii = ld_xix_byte<IX>(); NEXT; }
1851
1852 case 0x44: { II ii = ld_R_R<B,IXH,T::CC_DD>(); NEXT; }
1853 case 0x45: { II ii = ld_R_R<B,IXL,T::CC_DD>(); NEXT; }
1854 case 0x4c: { II ii = ld_R_R<C,IXH,T::CC_DD>(); NEXT; }
1855 case 0x4d: { II ii = ld_R_R<C,IXL,T::CC_DD>(); NEXT; }
1856 case 0x54: { II ii = ld_R_R<D,IXH,T::CC_DD>(); NEXT; }
1857 case 0x55: { II ii = ld_R_R<D,IXL,T::CC_DD>(); NEXT; }
1858 case 0x5c: { II ii = ld_R_R<E,IXH,T::CC_DD>(); NEXT; }
1859 case 0x5d: { II ii = ld_R_R<E,IXL,T::CC_DD>(); NEXT; }
1860 case 0x7c: { II ii = ld_R_R<A,IXH,T::CC_DD>(); NEXT; }
1861 case 0x7d: { II ii = ld_R_R<A,IXL,T::CC_DD>(); NEXT; }
1862 case 0x60: { II ii = ld_R_R<IXH,B,T::CC_DD>(); NEXT; }
1863 case 0x61: { II ii = ld_R_R<IXH,C,T::CC_DD>(); NEXT; }
1864 case 0x62: { II ii = ld_R_R<IXH,D,T::CC_DD>(); NEXT; }
1865 case 0x63: { II ii = ld_R_R<IXH,E,T::CC_DD>(); NEXT; }
1866 case 0x65: { II ii = ld_R_R<IXH,IXL,T::CC_DD>(); NEXT; }
1867 case 0x67: { II ii = ld_R_R<IXH,A,T::CC_DD>(); NEXT; }
1868 case 0x68: { II ii = ld_R_R<IXL,B,T::CC_DD>(); NEXT; }
1869 case 0x69: { II ii = ld_R_R<IXL,C,T::CC_DD>(); NEXT; }
1870 case 0x6a: { II ii = ld_R_R<IXL,D,T::CC_DD>(); NEXT; }
1871 case 0x6b: { II ii = ld_R_R<IXL,E,T::CC_DD>(); NEXT; }
1872 case 0x6c: { II ii = ld_R_R<IXL,IXH,T::CC_DD>(); NEXT; }
1873 case 0x6f: { II ii = ld_R_R<IXL,A,T::CC_DD>(); NEXT; }
1874 case 0x70: { II ii = ld_xix_R<IX,B>(); NEXT; }
1875 case 0x71: { II ii = ld_xix_R<IX,C>(); NEXT; }
1876 case 0x72: { II ii = ld_xix_R<IX,D>(); NEXT; }
1877 case 0x73: { II ii = ld_xix_R<IX,E>(); NEXT; }
1878 case 0x74: { II ii = ld_xix_R<IX,H>(); NEXT; }
1879 case 0x75: { II ii = ld_xix_R<IX,L>(); NEXT; }
1880 case 0x77: { II ii = ld_xix_R<IX,A>(); NEXT; }
1881 case 0x46: { II ii = ld_R_xix<B,IX>(); NEXT; }
1882 case 0x4e: { II ii = ld_R_xix<C,IX>(); NEXT; }
1883 case 0x56: { II ii = ld_R_xix<D,IX>(); NEXT; }
1884 case 0x5e: { II ii = ld_R_xix<E,IX>(); NEXT; }
1885 case 0x66: { II ii = ld_R_xix<H,IX>(); NEXT; }
1886 case 0x6e: { II ii = ld_R_xix<L,IX>(); NEXT; }
1887 case 0x7e: { II ii = ld_R_xix<A,IX>(); NEXT; }
1888
1889 case 0x84: { II ii = add_a_R<IXH,T::CC_DD>(); NEXT; }
1890 case 0x85: { II ii = add_a_R<IXL,T::CC_DD>(); NEXT; }
1891 case 0x86: { II ii = add_a_xix<IX>(); NEXT; }
1892 case 0x8c: { II ii = adc_a_R<IXH,T::CC_DD>(); NEXT; }
1893 case 0x8d: { II ii = adc_a_R<IXL,T::CC_DD>(); NEXT; }
1894 case 0x8e: { II ii = adc_a_xix<IX>(); NEXT; }
1895 case 0x94: { II ii = sub_R<IXH,T::CC_DD>(); NEXT; }
1896 case 0x95: { II ii = sub_R<IXL,T::CC_DD>(); NEXT; }
1897 case 0x96: { II ii = sub_xix<IX>(); NEXT; }
1898 case 0x9c: { II ii = sbc_a_R<IXH,T::CC_DD>(); NEXT; }
1899 case 0x9d: { II ii = sbc_a_R<IXL,T::CC_DD>(); NEXT; }
1900 case 0x9e: { II ii = sbc_a_xix<IX>(); NEXT; }
1901 case 0xa4: { II ii = and_R<IXH,T::CC_DD>(); NEXT; }
1902 case 0xa5: { II ii = and_R<IXL,T::CC_DD>(); NEXT; }
1903 case 0xa6: { II ii = and_xix<IX>(); NEXT; }
1904 case 0xac: { II ii = xor_R<IXH,T::CC_DD>(); NEXT; }
1905 case 0xad: { II ii = xor_R<IXL,T::CC_DD>(); NEXT; }
1906 case 0xae: { II ii = xor_xix<IX>(); NEXT; }
1907 case 0xb4: { II ii = or_R<IXH,T::CC_DD>(); NEXT; }
1908 case 0xb5: { II ii = or_R<IXL,T::CC_DD>(); NEXT; }
1909 case 0xb6: { II ii = or_xix<IX>(); NEXT; }
1910 case 0xbc: { II ii = cp_R<IXH,T::CC_DD>(); NEXT; }
1911 case 0xbd: { II ii = cp_R<IXL,T::CC_DD>(); NEXT; }
1912 case 0xbe: { II ii = cp_xix<IX>(); NEXT; }
1913
1914 case 0xe1: { II ii = pop_SS <IX,T::CC_DD>(); NEXT; }
1915 case 0xe5: { II ii = push_SS<IX,T::CC_DD>(); NEXT; }
1916 case 0xe3: { II ii = ex_xsp_SS<IX,T::CC_DD>(); NEXT; }
1917 case 0xe9: { II ii = jp_SS<IX,T::CC_DD>(); NEXT; }
1918 case 0xf9: { II ii = ld_sp_SS<IX,T::CC_DD>(); NEXT; }
1919 case 0xcb: ixy = getIX(); goto xx_cb;
1920 case 0xdd:
1921 if constexpr (T::IS_R800) {
1922 II ii = nop<T::CC_DD>(); NEXT;
1923 } else {
1924 T::add(T::CC_DD); goto opDD_2;
1925 }
1926 case 0xfd:
1927 if constexpr (T::IS_R800) {
1928 II ii = nop<T::CC_DD>(); NEXT;
1929 } else {
1930 T::add(T::CC_DD); goto opFD_2;
1931 }
1932 default: UNREACHABLE;
1933 }
1934}
1935MAYBE_UNUSED_LABEL opFD_2:
1936CASE(FD) {
1937 setPC(getPC() + 1); // M1 cycle at this point
1938 byte opcodeFD = RDMEM_OPCODE<0>(T::CC_DD + T::CC_MAIN);
1939 incR(1);
1940 switch (opcodeFD) {
1941 case 0x00: // nop();
1942 case 0x01: // ld_bc_word();
1943 case 0x02: // ld_xbc_a();
1944 case 0x03: // inc_bc();
1945 case 0x04: // inc_b();
1946 case 0x05: // dec_b();
1947 case 0x06: // ld_b_byte();
1948 case 0x07: // rlca();
1949 case 0x08: // ex_af_af();
1950 case 0x0a: // ld_a_xbc();
1951 case 0x0b: // dec_bc();
1952 case 0x0c: // inc_c();
1953 case 0x0d: // dec_c();
1954 case 0x0e: // ld_c_byte();
1955 case 0x0f: // rrca();
1956 case 0x10: // djnz();
1957 case 0x11: // ld_de_word();
1958 case 0x12: // ld_xde_a();
1959 case 0x13: // inc_de();
1960 case 0x14: // inc_d();
1961 case 0x15: // dec_d();
1962 case 0x16: // ld_d_byte();
1963 case 0x17: // rla();
1964 case 0x18: // jr();
1965 case 0x1a: // ld_a_xde();
1966 case 0x1b: // dec_de();
1967 case 0x1c: // inc_e();
1968 case 0x1d: // dec_e();
1969 case 0x1e: // ld_e_byte();
1970 case 0x1f: // rra();
1971 case 0x20: // jr_nz();
1972 case 0x27: // daa();
1973 case 0x28: // jr_z();
1974 case 0x2f: // cpl();
1975 case 0x30: // jr_nc();
1976 case 0x31: // ld_sp_word();
1977 case 0x32: // ld_xbyte_a();
1978 case 0x33: // inc_sp();
1979 case 0x37: // scf();
1980 case 0x38: // jr_c();
1981 case 0x3a: // ld_a_xbyte();
1982 case 0x3b: // dec_sp();
1983 case 0x3c: // inc_a();
1984 case 0x3d: // dec_a();
1985 case 0x3e: // ld_a_byte();
1986 case 0x3f: // ccf();
1987
1988 case 0x40: // ld_b_b();
1989 case 0x41: // ld_b_c();
1990 case 0x42: // ld_b_d();
1991 case 0x43: // ld_b_e();
1992 case 0x47: // ld_b_a();
1993 case 0x48: // ld_c_b();
1994 case 0x49: // ld_c_c();
1995 case 0x4a: // ld_c_d();
1996 case 0x4b: // ld_c_e();
1997 case 0x4f: // ld_c_a();
1998 case 0x50: // ld_d_b();
1999 case 0x51: // ld_d_c();
2000 case 0x52: // ld_d_d();
2001 case 0x53: // ld_d_e();
2002 case 0x57: // ld_d_a();
2003 case 0x58: // ld_e_b();
2004 case 0x59: // ld_e_c();
2005 case 0x5a: // ld_e_d();
2006 case 0x5b: // ld_e_e();
2007 case 0x5f: // ld_e_a();
2008 case 0x64: // ld_ixh_ixh(); == nop
2009 case 0x6d: // ld_ixl_ixl(); == nop
2010 case 0x76: // halt();
2011 case 0x78: // ld_a_b();
2012 case 0x79: // ld_a_c();
2013 case 0x7a: // ld_a_d();
2014 case 0x7b: // ld_a_e();
2015 case 0x7f: // ld_a_a();
2016
2017 case 0x80: // add_a_b();
2018 case 0x81: // add_a_c();
2019 case 0x82: // add_a_d();
2020 case 0x83: // add_a_e();
2021 case 0x87: // add_a_a();
2022 case 0x88: // adc_a_b();
2023 case 0x89: // adc_a_c();
2024 case 0x8a: // adc_a_d();
2025 case 0x8b: // adc_a_e();
2026 case 0x8f: // adc_a_a();
2027 case 0x90: // sub_b();
2028 case 0x91: // sub_c();
2029 case 0x92: // sub_d();
2030 case 0x93: // sub_e();
2031 case 0x97: // sub_a();
2032 case 0x98: // sbc_a_b();
2033 case 0x99: // sbc_a_c();
2034 case 0x9a: // sbc_a_d();
2035 case 0x9b: // sbc_a_e();
2036 case 0x9f: // sbc_a_a();
2037 case 0xa0: // and_b();
2038 case 0xa1: // and_c();
2039 case 0xa2: // and_d();
2040 case 0xa3: // and_e();
2041 case 0xa7: // and_a();
2042 case 0xa8: // xor_b();
2043 case 0xa9: // xor_c();
2044 case 0xaa: // xor_d();
2045 case 0xab: // xor_e();
2046 case 0xaf: // xor_a();
2047 case 0xb0: // or_b();
2048 case 0xb1: // or_c();
2049 case 0xb2: // or_d();
2050 case 0xb3: // or_e();
2051 case 0xb7: // or_a();
2052 case 0xb8: // cp_b();
2053 case 0xb9: // cp_c();
2054 case 0xba: // cp_d();
2055 case 0xbb: // cp_e();
2056 case 0xbf: // cp_a();
2057
2058 case 0xc0: // ret_nz();
2059 case 0xc1: // pop_bc();
2060 case 0xc2: // jp_nz();
2061 case 0xc3: // jp();
2062 case 0xc4: // call_nz();
2063 case 0xc5: // push_bc();
2064 case 0xc6: // add_a_byte();
2065 case 0xc7: // rst_00();
2066 case 0xc8: // ret_z();
2067 case 0xc9: // ret();
2068 case 0xca: // jp_z();
2069 case 0xcc: // call_z();
2070 case 0xcd: // call();
2071 case 0xce: // adc_a_byte();
2072 case 0xcf: // rst_08();
2073 case 0xd0: // ret_nc();
2074 case 0xd1: // pop_de();
2075 case 0xd2: // jp_nc();
2076 case 0xd3: // out_byte_a();
2077 case 0xd4: // call_nc();
2078 case 0xd5: // push_de();
2079 case 0xd6: // sub_byte();
2080 case 0xd7: // rst_10();
2081 case 0xd8: // ret_c();
2082 case 0xd9: // exx();
2083 case 0xda: // jp_c();
2084 case 0xdb: // in_a_byte();
2085 case 0xdc: // call_c();
2086 case 0xde: // sbc_a_byte();
2087 case 0xdf: // rst_18();
2088 case 0xe0: // ret_po();
2089 case 0xe2: // jp_po();
2090 case 0xe4: // call_po();
2091 case 0xe6: // and_byte();
2092 case 0xe7: // rst_20();
2093 case 0xe8: // ret_pe();
2094 case 0xea: // jp_pe();
2095 case 0xeb: // ex_de_hl();
2096 case 0xec: // call_pe();
2097 case 0xed: // ed();
2098 case 0xee: // xor_byte();
2099 case 0xef: // rst_28();
2100 case 0xf0: // ret_p();
2101 case 0xf1: // pop_af();
2102 case 0xf2: // jp_p();
2103 case 0xf3: // di();
2104 case 0xf4: // call_p();
2105 case 0xf5: // push_af();
2106 case 0xf6: // or_byte();
2107 case 0xf7: // rst_30();
2108 case 0xf8: // ret_m();
2109 case 0xfa: // jp_m();
2110 case 0xfb: // ei();
2111 case 0xfc: // call_m();
2112 case 0xfe: // cp_byte();
2113 case 0xff: // rst_38();
2114 if constexpr (T::IS_R800) {
2115 II ii = nop<T::CC_DD>(); NEXT;
2116 } else {
2117 T::add(T::CC_DD);
2118 #ifdef USE_COMPUTED_GOTO
2119 goto *(opcodeTable[opcodeFD]);
2120 #else
2121 opcodeMain = opcodeFD;
2122 goto switchOpcode;
2123 #endif
2124 }
2125
2126 case 0x09: { II ii = add_SS_TT<IY,BC,T::CC_DD>(); NEXT; }
2127 case 0x19: { II ii = add_SS_TT<IY,DE,T::CC_DD>(); NEXT; }
2128 case 0x29: { II ii = add_SS_SS<IY ,T::CC_DD>(); NEXT; }
2129 case 0x39: { II ii = add_SS_TT<IY,SP,T::CC_DD>(); NEXT; }
2130 case 0x21: { II ii = ld_SS_word<IY,T::CC_DD>(); NEXT; }
2131 case 0x22: { II ii = ld_xword_SS<IY,T::CC_DD>(); NEXT; }
2132 case 0x2a: { II ii = ld_SS_xword<IY,T::CC_DD>(); NEXT; }
2133 case 0x23: { II ii = inc_SS<IY,T::CC_DD>(); NEXT; }
2134 case 0x2b: { II ii = dec_SS<IY,T::CC_DD>(); NEXT; }
2135 case 0x24: { II ii = inc_R<IYH,T::CC_DD>(); NEXT; }
2136 case 0x2c: { II ii = inc_R<IYL,T::CC_DD>(); NEXT; }
2137 case 0x25: { II ii = dec_R<IYH,T::CC_DD>(); NEXT; }
2138 case 0x2d: { II ii = dec_R<IYL,T::CC_DD>(); NEXT; }
2139 case 0x26: { II ii = ld_R_byte<IYH,T::CC_DD>(); NEXT; }
2140 case 0x2e: { II ii = ld_R_byte<IYL,T::CC_DD>(); NEXT; }
2141 case 0x34: { II ii = inc_xix<IY>(); NEXT; }
2142 case 0x35: { II ii = dec_xix<IY>(); NEXT; }
2143 case 0x36: { II ii = ld_xix_byte<IY>(); NEXT; }
2144
2145 case 0x44: { II ii = ld_R_R<B,IYH,T::CC_DD>(); NEXT; }
2146 case 0x45: { II ii = ld_R_R<B,IYL,T::CC_DD>(); NEXT; }
2147 case 0x4c: { II ii = ld_R_R<C,IYH,T::CC_DD>(); NEXT; }
2148 case 0x4d: { II ii = ld_R_R<C,IYL,T::CC_DD>(); NEXT; }
2149 case 0x54: { II ii = ld_R_R<D,IYH,T::CC_DD>(); NEXT; }
2150 case 0x55: { II ii = ld_R_R<D,IYL,T::CC_DD>(); NEXT; }
2151 case 0x5c: { II ii = ld_R_R<E,IYH,T::CC_DD>(); NEXT; }
2152 case 0x5d: { II ii = ld_R_R<E,IYL,T::CC_DD>(); NEXT; }
2153 case 0x7c: { II ii = ld_R_R<A,IYH,T::CC_DD>(); NEXT; }
2154 case 0x7d: { II ii = ld_R_R<A,IYL,T::CC_DD>(); NEXT; }
2155 case 0x60: { II ii = ld_R_R<IYH,B,T::CC_DD>(); NEXT; }
2156 case 0x61: { II ii = ld_R_R<IYH,C,T::CC_DD>(); NEXT; }
2157 case 0x62: { II ii = ld_R_R<IYH,D,T::CC_DD>(); NEXT; }
2158 case 0x63: { II ii = ld_R_R<IYH,E,T::CC_DD>(); NEXT; }
2159 case 0x65: { II ii = ld_R_R<IYH,IYL,T::CC_DD>(); NEXT; }
2160 case 0x67: { II ii = ld_R_R<IYH,A,T::CC_DD>(); NEXT; }
2161 case 0x68: { II ii = ld_R_R<IYL,B,T::CC_DD>(); NEXT; }
2162 case 0x69: { II ii = ld_R_R<IYL,C,T::CC_DD>(); NEXT; }
2163 case 0x6a: { II ii = ld_R_R<IYL,D,T::CC_DD>(); NEXT; }
2164 case 0x6b: { II ii = ld_R_R<IYL,E,T::CC_DD>(); NEXT; }
2165 case 0x6c: { II ii = ld_R_R<IYL,IYH,T::CC_DD>(); NEXT; }
2166 case 0x6f: { II ii = ld_R_R<IYL,A,T::CC_DD>(); NEXT; }
2167 case 0x70: { II ii = ld_xix_R<IY,B>(); NEXT; }
2168 case 0x71: { II ii = ld_xix_R<IY,C>(); NEXT; }
2169 case 0x72: { II ii = ld_xix_R<IY,D>(); NEXT; }
2170 case 0x73: { II ii = ld_xix_R<IY,E>(); NEXT; }
2171 case 0x74: { II ii = ld_xix_R<IY,H>(); NEXT; }
2172 case 0x75: { II ii = ld_xix_R<IY,L>(); NEXT; }
2173 case 0x77: { II ii = ld_xix_R<IY,A>(); NEXT; }
2174 case 0x46: { II ii = ld_R_xix<B,IY>(); NEXT; }
2175 case 0x4e: { II ii = ld_R_xix<C,IY>(); NEXT; }
2176 case 0x56: { II ii = ld_R_xix<D,IY>(); NEXT; }
2177 case 0x5e: { II ii = ld_R_xix<E,IY>(); NEXT; }
2178 case 0x66: { II ii = ld_R_xix<H,IY>(); NEXT; }
2179 case 0x6e: { II ii = ld_R_xix<L,IY>(); NEXT; }
2180 case 0x7e: { II ii = ld_R_xix<A,IY>(); NEXT; }
2181
2182 case 0x84: { II ii = add_a_R<IYH,T::CC_DD>(); NEXT; }
2183 case 0x85: { II ii = add_a_R<IYL,T::CC_DD>(); NEXT; }
2184 case 0x86: { II ii = add_a_xix<IY>(); NEXT; }
2185 case 0x8c: { II ii = adc_a_R<IYH,T::CC_DD>(); NEXT; }
2186 case 0x8d: { II ii = adc_a_R<IYL,T::CC_DD>(); NEXT; }
2187 case 0x8e: { II ii = adc_a_xix<IY>(); NEXT; }
2188 case 0x94: { II ii = sub_R<IYH,T::CC_DD>(); NEXT; }
2189 case 0x95: { II ii = sub_R<IYL,T::CC_DD>(); NEXT; }
2190 case 0x96: { II ii = sub_xix<IY>(); NEXT; }
2191 case 0x9c: { II ii = sbc_a_R<IYH,T::CC_DD>(); NEXT; }
2192 case 0x9d: { II ii = sbc_a_R<IYL,T::CC_DD>(); NEXT; }
2193 case 0x9e: { II ii = sbc_a_xix<IY>(); NEXT; }
2194 case 0xa4: { II ii = and_R<IYH,T::CC_DD>(); NEXT; }
2195 case 0xa5: { II ii = and_R<IYL,T::CC_DD>(); NEXT; }
2196 case 0xa6: { II ii = and_xix<IY>(); NEXT; }
2197 case 0xac: { II ii = xor_R<IYH,T::CC_DD>(); NEXT; }
2198 case 0xad: { II ii = xor_R<IYL,T::CC_DD>(); NEXT; }
2199 case 0xae: { II ii = xor_xix<IY>(); NEXT; }
2200 case 0xb4: { II ii = or_R<IYH,T::CC_DD>(); NEXT; }
2201 case 0xb5: { II ii = or_R<IYL,T::CC_DD>(); NEXT; }
2202 case 0xb6: { II ii = or_xix<IY>(); NEXT; }
2203 case 0xbc: { II ii = cp_R<IYH,T::CC_DD>(); NEXT; }
2204 case 0xbd: { II ii = cp_R<IYL,T::CC_DD>(); NEXT; }
2205 case 0xbe: { II ii = cp_xix<IY>(); NEXT; }
2206
2207 case 0xe1: { II ii = pop_SS <IY,T::CC_DD>(); NEXT; }
2208 case 0xe5: { II ii = push_SS<IY,T::CC_DD>(); NEXT; }
2209 case 0xe3: { II ii = ex_xsp_SS<IY,T::CC_DD>(); NEXT; }
2210 case 0xe9: { II ii = jp_SS<IY,T::CC_DD>(); NEXT; }
2211 case 0xf9: { II ii = ld_sp_SS<IY,T::CC_DD>(); NEXT; }
2212 case 0xcb: ixy = getIY(); goto xx_cb;
2213 case 0xdd:
2214 if constexpr (T::IS_R800) {
2215 II ii = nop<T::CC_DD>(); NEXT;
2216 } else {
2217 T::add(T::CC_DD); goto opDD_2;
2218 }
2219 case 0xfd:
2220 if constexpr (T::IS_R800) {
2221 II ii = nop<T::CC_DD>(); NEXT;
2222 } else {
2223 T::add(T::CC_DD); goto opFD_2;
2224 }
2225 default: UNREACHABLE;
2226 }
2227}
2228#ifndef USE_COMPUTED_GOTO
2229 default: UNREACHABLE;
2230}
2231#endif
2232
2233xx_cb: {
2234 unsigned tmp = RD_WORD_PC<1>(T::CC_DD + T::CC_DD_CB);
2235 auto ofst = narrow_cast<int8_t>(tmp & 0xFF);
2236 unsigned addr = narrow_cast<word>(ixy + ofst);
2237 auto xxcb_opcode = narrow_cast<byte>(tmp >> 8);
2238 switch (xxcb_opcode) {
2239 case 0x00: { II ii = rlc_xix_R<B>(addr); NEXT; }
2240 case 0x01: { II ii = rlc_xix_R<C>(addr); NEXT; }
2241 case 0x02: { II ii = rlc_xix_R<D>(addr); NEXT; }
2242 case 0x03: { II ii = rlc_xix_R<E>(addr); NEXT; }
2243 case 0x04: { II ii = rlc_xix_R<H>(addr); NEXT; }
2244 case 0x05: { II ii = rlc_xix_R<L>(addr); NEXT; }
2245 case 0x06: { II ii = rlc_xix_R<DUMMY>(addr); NEXT; }
2246 case 0x07: { II ii = rlc_xix_R<A>(addr); NEXT; }
2247 case 0x08: { II ii = rrc_xix_R<B>(addr); NEXT; }
2248 case 0x09: { II ii = rrc_xix_R<C>(addr); NEXT; }
2249 case 0x0a: { II ii = rrc_xix_R<D>(addr); NEXT; }
2250 case 0x0b: { II ii = rrc_xix_R<E>(addr); NEXT; }
2251 case 0x0c: { II ii = rrc_xix_R<H>(addr); NEXT; }
2252 case 0x0d: { II ii = rrc_xix_R<L>(addr); NEXT; }
2253 case 0x0e: { II ii = rrc_xix_R<DUMMY>(addr); NEXT; }
2254 case 0x0f: { II ii = rrc_xix_R<A>(addr); NEXT; }
2255 case 0x10: { II ii = rl_xix_R<B>(addr); NEXT; }
2256 case 0x11: { II ii = rl_xix_R<C>(addr); NEXT; }
2257 case 0x12: { II ii = rl_xix_R<D>(addr); NEXT; }
2258 case 0x13: { II ii = rl_xix_R<E>(addr); NEXT; }
2259 case 0x14: { II ii = rl_xix_R<H>(addr); NEXT; }
2260 case 0x15: { II ii = rl_xix_R<L>(addr); NEXT; }
2261 case 0x16: { II ii = rl_xix_R<DUMMY>(addr); NEXT; }
2262 case 0x17: { II ii = rl_xix_R<A>(addr); NEXT; }
2263 case 0x18: { II ii = rr_xix_R<B>(addr); NEXT; }
2264 case 0x19: { II ii = rr_xix_R<C>(addr); NEXT; }
2265 case 0x1a: { II ii = rr_xix_R<D>(addr); NEXT; }
2266 case 0x1b: { II ii = rr_xix_R<E>(addr); NEXT; }
2267 case 0x1c: { II ii = rr_xix_R<H>(addr); NEXT; }
2268 case 0x1d: { II ii = rr_xix_R<L>(addr); NEXT; }
2269 case 0x1e: { II ii = rr_xix_R<DUMMY>(addr); NEXT; }
2270 case 0x1f: { II ii = rr_xix_R<A>(addr); NEXT; }
2271 case 0x20: { II ii = sla_xix_R<B>(addr); NEXT; }
2272 case 0x21: { II ii = sla_xix_R<C>(addr); NEXT; }
2273 case 0x22: { II ii = sla_xix_R<D>(addr); NEXT; }
2274 case 0x23: { II ii = sla_xix_R<E>(addr); NEXT; }
2275 case 0x24: { II ii = sla_xix_R<H>(addr); NEXT; }
2276 case 0x25: { II ii = sla_xix_R<L>(addr); NEXT; }
2277 case 0x26: { II ii = sla_xix_R<DUMMY>(addr); NEXT; }
2278 case 0x27: { II ii = sla_xix_R<A>(addr); NEXT; }
2279 case 0x28: { II ii = sra_xix_R<B>(addr); NEXT; }
2280 case 0x29: { II ii = sra_xix_R<C>(addr); NEXT; }
2281 case 0x2a: { II ii = sra_xix_R<D>(addr); NEXT; }
2282 case 0x2b: { II ii = sra_xix_R<E>(addr); NEXT; }
2283 case 0x2c: { II ii = sra_xix_R<H>(addr); NEXT; }
2284 case 0x2d: { II ii = sra_xix_R<L>(addr); NEXT; }
2285 case 0x2e: { II ii = sra_xix_R<DUMMY>(addr); NEXT; }
2286 case 0x2f: { II ii = sra_xix_R<A>(addr); NEXT; }
2287 case 0x30: { II ii = T::IS_R800 ? sll2() : sll_xix_R<B>(addr); NEXT; }
2288 case 0x31: { II ii = T::IS_R800 ? sll2() : sll_xix_R<C>(addr); NEXT; }
2289 case 0x32: { II ii = T::IS_R800 ? sll2() : sll_xix_R<D>(addr); NEXT; }
2290 case 0x33: { II ii = T::IS_R800 ? sll2() : sll_xix_R<E>(addr); NEXT; }
2291 case 0x34: { II ii = T::IS_R800 ? sll2() : sll_xix_R<H>(addr); NEXT; }
2292 case 0x35: { II ii = T::IS_R800 ? sll2() : sll_xix_R<L>(addr); NEXT; }
2293 case 0x36: { II ii = T::IS_R800 ? sll2() : sll_xix_R<DUMMY>(addr); NEXT; }
2294 case 0x37: { II ii = T::IS_R800 ? sll2() : sll_xix_R<A>(addr); NEXT; }
2295 case 0x38: { II ii = srl_xix_R<B>(addr); NEXT; }
2296 case 0x39: { II ii = srl_xix_R<C>(addr); NEXT; }
2297 case 0x3a: { II ii = srl_xix_R<D>(addr); NEXT; }
2298 case 0x3b: { II ii = srl_xix_R<E>(addr); NEXT; }
2299 case 0x3c: { II ii = srl_xix_R<H>(addr); NEXT; }
2300 case 0x3d: { II ii = srl_xix_R<L>(addr); NEXT; }
2301 case 0x3e: { II ii = srl_xix_R<DUMMY>(addr); NEXT; }
2302 case 0x3f: { II ii = srl_xix_R<A>(addr); NEXT; }
2303
2304 case 0x40: case 0x41: case 0x42: case 0x43:
2305 case 0x44: case 0x45: case 0x46: case 0x47:
2306 { II ii = bit_N_xix<0>(addr); NEXT; }
2307 case 0x48: case 0x49: case 0x4a: case 0x4b:
2308 case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2309 { II ii = bit_N_xix<1>(addr); NEXT; }
2310 case 0x50: case 0x51: case 0x52: case 0x53:
2311 case 0x54: case 0x55: case 0x56: case 0x57:
2312 { II ii = bit_N_xix<2>(addr); NEXT; }
2313 case 0x58: case 0x59: case 0x5a: case 0x5b:
2314 case 0x5c: case 0x5d: case 0x5e: case 0x5f:
2315 { II ii = bit_N_xix<3>(addr); NEXT; }
2316 case 0x60: case 0x61: case 0x62: case 0x63:
2317 case 0x64: case 0x65: case 0x66: case 0x67:
2318 { II ii = bit_N_xix<4>(addr); NEXT; }
2319 case 0x68: case 0x69: case 0x6a: case 0x6b:
2320 case 0x6c: case 0x6d: case 0x6e: case 0x6f:
2321 { II ii = bit_N_xix<5>(addr); NEXT; }
2322 case 0x70: case 0x71: case 0x72: case 0x73:
2323 case 0x74: case 0x75: case 0x76: case 0x77:
2324 { II ii = bit_N_xix<6>(addr); NEXT; }
2325 case 0x78: case 0x79: case 0x7a: case 0x7b:
2326 case 0x7c: case 0x7d: case 0x7e: case 0x7f:
2327 { II ii = bit_N_xix<7>(addr); NEXT; }
2328
2329 case 0x80: { II ii = res_N_xix_R<0,B>(addr); NEXT; }
2330 case 0x81: { II ii = res_N_xix_R<0,C>(addr); NEXT; }
2331 case 0x82: { II ii = res_N_xix_R<0,D>(addr); NEXT; }
2332 case 0x83: { II ii = res_N_xix_R<0,E>(addr); NEXT; }
2333 case 0x84: { II ii = res_N_xix_R<0,H>(addr); NEXT; }
2334 case 0x85: { II ii = res_N_xix_R<0,L>(addr); NEXT; }
2335 case 0x87: { II ii = res_N_xix_R<0,A>(addr); NEXT; }
2336 case 0x88: { II ii = res_N_xix_R<1,B>(addr); NEXT; }
2337 case 0x89: { II ii = res_N_xix_R<1,C>(addr); NEXT; }
2338 case 0x8a: { II ii = res_N_xix_R<1,D>(addr); NEXT; }
2339 case 0x8b: { II ii = res_N_xix_R<1,E>(addr); NEXT; }
2340 case 0x8c: { II ii = res_N_xix_R<1,H>(addr); NEXT; }
2341 case 0x8d: { II ii = res_N_xix_R<1,L>(addr); NEXT; }
2342 case 0x8f: { II ii = res_N_xix_R<1,A>(addr); NEXT; }
2343 case 0x90: { II ii = res_N_xix_R<2,B>(addr); NEXT; }
2344 case 0x91: { II ii = res_N_xix_R<2,C>(addr); NEXT; }
2345 case 0x92: { II ii = res_N_xix_R<2,D>(addr); NEXT; }
2346 case 0x93: { II ii = res_N_xix_R<2,E>(addr); NEXT; }
2347 case 0x94: { II ii = res_N_xix_R<2,H>(addr); NEXT; }
2348 case 0x95: { II ii = res_N_xix_R<2,L>(addr); NEXT; }
2349 case 0x97: { II ii = res_N_xix_R<2,A>(addr); NEXT; }
2350 case 0x98: { II ii = res_N_xix_R<3,B>(addr); NEXT; }
2351 case 0x99: { II ii = res_N_xix_R<3,C>(addr); NEXT; }
2352 case 0x9a: { II ii = res_N_xix_R<3,D>(addr); NEXT; }
2353 case 0x9b: { II ii = res_N_xix_R<3,E>(addr); NEXT; }
2354 case 0x9c: { II ii = res_N_xix_R<3,H>(addr); NEXT; }
2355 case 0x9d: { II ii = res_N_xix_R<3,L>(addr); NEXT; }
2356 case 0x9f: { II ii = res_N_xix_R<3,A>(addr); NEXT; }
2357 case 0xa0: { II ii = res_N_xix_R<4,B>(addr); NEXT; }
2358 case 0xa1: { II ii = res_N_xix_R<4,C>(addr); NEXT; }
2359 case 0xa2: { II ii = res_N_xix_R<4,D>(addr); NEXT; }
2360 case 0xa3: { II ii = res_N_xix_R<4,E>(addr); NEXT; }
2361 case 0xa4: { II ii = res_N_xix_R<4,H>(addr); NEXT; }
2362 case 0xa5: { II ii = res_N_xix_R<4,L>(addr); NEXT; }
2363 case 0xa7: { II ii = res_N_xix_R<4,A>(addr); NEXT; }
2364 case 0xa8: { II ii = res_N_xix_R<5,B>(addr); NEXT; }
2365 case 0xa9: { II ii = res_N_xix_R<5,C>(addr); NEXT; }
2366 case 0xaa: { II ii = res_N_xix_R<5,D>(addr); NEXT; }
2367 case 0xab: { II ii = res_N_xix_R<5,E>(addr); NEXT; }
2368 case 0xac: { II ii = res_N_xix_R<5,H>(addr); NEXT; }
2369 case 0xad: { II ii = res_N_xix_R<5,L>(addr); NEXT; }
2370 case 0xaf: { II ii = res_N_xix_R<5,A>(addr); NEXT; }
2371 case 0xb0: { II ii = res_N_xix_R<6,B>(addr); NEXT; }
2372 case 0xb1: { II ii = res_N_xix_R<6,C>(addr); NEXT; }
2373 case 0xb2: { II ii = res_N_xix_R<6,D>(addr); NEXT; }
2374 case 0xb3: { II ii = res_N_xix_R<6,E>(addr); NEXT; }
2375 case 0xb4: { II ii = res_N_xix_R<6,H>(addr); NEXT; }
2376 case 0xb5: { II ii = res_N_xix_R<6,L>(addr); NEXT; }
2377 case 0xb7: { II ii = res_N_xix_R<6,A>(addr); NEXT; }
2378 case 0xb8: { II ii = res_N_xix_R<7,B>(addr); NEXT; }
2379 case 0xb9: { II ii = res_N_xix_R<7,C>(addr); NEXT; }
2380 case 0xba: { II ii = res_N_xix_R<7,D>(addr); NEXT; }
2381 case 0xbb: { II ii = res_N_xix_R<7,E>(addr); NEXT; }
2382 case 0xbc: { II ii = res_N_xix_R<7,H>(addr); NEXT; }
2383 case 0xbd: { II ii = res_N_xix_R<7,L>(addr); NEXT; }
2384 case 0xbf: { II ii = res_N_xix_R<7,A>(addr); NEXT; }
2385 case 0x86: { II ii = res_N_xix_R<0,DUMMY>(addr); NEXT; }
2386 case 0x8e: { II ii = res_N_xix_R<1,DUMMY>(addr); NEXT; }
2387 case 0x96: { II ii = res_N_xix_R<2,DUMMY>(addr); NEXT; }
2388 case 0x9e: { II ii = res_N_xix_R<3,DUMMY>(addr); NEXT; }
2389 case 0xa6: { II ii = res_N_xix_R<4,DUMMY>(addr); NEXT; }
2390 case 0xae: { II ii = res_N_xix_R<5,DUMMY>(addr); NEXT; }
2391 case 0xb6: { II ii = res_N_xix_R<6,DUMMY>(addr); NEXT; }
2392 case 0xbe: { II ii = res_N_xix_R<7,DUMMY>(addr); NEXT; }
2393
2394 case 0xc0: { II ii = set_N_xix_R<0,B>(addr); NEXT; }
2395 case 0xc1: { II ii = set_N_xix_R<0,C>(addr); NEXT; }
2396 case 0xc2: { II ii = set_N_xix_R<0,D>(addr); NEXT; }
2397 case 0xc3: { II ii = set_N_xix_R<0,E>(addr); NEXT; }
2398 case 0xc4: { II ii = set_N_xix_R<0,H>(addr); NEXT; }
2399 case 0xc5: { II ii = set_N_xix_R<0,L>(addr); NEXT; }
2400 case 0xc7: { II ii = set_N_xix_R<0,A>(addr); NEXT; }
2401 case 0xc8: { II ii = set_N_xix_R<1,B>(addr); NEXT; }
2402 case 0xc9: { II ii = set_N_xix_R<1,C>(addr); NEXT; }
2403 case 0xca: { II ii = set_N_xix_R<1,D>(addr); NEXT; }
2404 case 0xcb: { II ii = set_N_xix_R<1,E>(addr); NEXT; }
2405 case 0xcc: { II ii = set_N_xix_R<1,H>(addr); NEXT; }
2406 case 0xcd: { II ii = set_N_xix_R<1,L>(addr); NEXT; }
2407 case 0xcf: { II ii = set_N_xix_R<1,A>(addr); NEXT; }
2408 case 0xd0: { II ii = set_N_xix_R<2,B>(addr); NEXT; }
2409 case 0xd1: { II ii = set_N_xix_R<2,C>(addr); NEXT; }
2410 case 0xd2: { II ii = set_N_xix_R<2,D>(addr); NEXT; }
2411 case 0xd3: { II ii = set_N_xix_R<2,E>(addr); NEXT; }
2412 case 0xd4: { II ii = set_N_xix_R<2,H>(addr); NEXT; }
2413 case 0xd5: { II ii = set_N_xix_R<2,L>(addr); NEXT; }
2414 case 0xd7: { II ii = set_N_xix_R<2,A>(addr); NEXT; }
2415 case 0xd8: { II ii = set_N_xix_R<3,B>(addr); NEXT; }
2416 case 0xd9: { II ii = set_N_xix_R<3,C>(addr); NEXT; }
2417 case 0xda: { II ii = set_N_xix_R<3,D>(addr); NEXT; }
2418 case 0xdb: { II ii = set_N_xix_R<3,E>(addr); NEXT; }
2419 case 0xdc: { II ii = set_N_xix_R<3,H>(addr); NEXT; }
2420 case 0xdd: { II ii = set_N_xix_R<3,L>(addr); NEXT; }
2421 case 0xdf: { II ii = set_N_xix_R<3,A>(addr); NEXT; }
2422 case 0xe0: { II ii = set_N_xix_R<4,B>(addr); NEXT; }
2423 case 0xe1: { II ii = set_N_xix_R<4,C>(addr); NEXT; }
2424 case 0xe2: { II ii = set_N_xix_R<4,D>(addr); NEXT; }
2425 case 0xe3: { II ii = set_N_xix_R<4,E>(addr); NEXT; }
2426 case 0xe4: { II ii = set_N_xix_R<4,H>(addr); NEXT; }
2427 case 0xe5: { II ii = set_N_xix_R<4,L>(addr); NEXT; }
2428 case 0xe7: { II ii = set_N_xix_R<4,A>(addr); NEXT; }
2429 case 0xe8: { II ii = set_N_xix_R<5,B>(addr); NEXT; }
2430 case 0xe9: { II ii = set_N_xix_R<5,C>(addr); NEXT; }
2431 case 0xea: { II ii = set_N_xix_R<5,D>(addr); NEXT; }
2432 case 0xeb: { II ii = set_N_xix_R<5,E>(addr); NEXT; }
2433 case 0xec: { II ii = set_N_xix_R<5,H>(addr); NEXT; }
2434 case 0xed: { II ii = set_N_xix_R<5,L>(addr); NEXT; }
2435 case 0xef: { II ii = set_N_xix_R<5,A>(addr); NEXT; }
2436 case 0xf0: { II ii = set_N_xix_R<6,B>(addr); NEXT; }
2437 case 0xf1: { II ii = set_N_xix_R<6,C>(addr); NEXT; }
2438 case 0xf2: { II ii = set_N_xix_R<6,D>(addr); NEXT; }
2439 case 0xf3: { II ii = set_N_xix_R<6,E>(addr); NEXT; }
2440 case 0xf4: { II ii = set_N_xix_R<6,H>(addr); NEXT; }
2441 case 0xf5: { II ii = set_N_xix_R<6,L>(addr); NEXT; }
2442 case 0xf7: { II ii = set_N_xix_R<6,A>(addr); NEXT; }
2443 case 0xf8: { II ii = set_N_xix_R<7,B>(addr); NEXT; }
2444 case 0xf9: { II ii = set_N_xix_R<7,C>(addr); NEXT; }
2445 case 0xfa: { II ii = set_N_xix_R<7,D>(addr); NEXT; }
2446 case 0xfb: { II ii = set_N_xix_R<7,E>(addr); NEXT; }
2447 case 0xfc: { II ii = set_N_xix_R<7,H>(addr); NEXT; }
2448 case 0xfd: { II ii = set_N_xix_R<7,L>(addr); NEXT; }
2449 case 0xff: { II ii = set_N_xix_R<7,A>(addr); NEXT; }
2450 case 0xc6: { II ii = set_N_xix_R<0,DUMMY>(addr); NEXT; }
2451 case 0xce: { II ii = set_N_xix_R<1,DUMMY>(addr); NEXT; }
2452 case 0xd6: { II ii = set_N_xix_R<2,DUMMY>(addr); NEXT; }
2453 case 0xde: { II ii = set_N_xix_R<3,DUMMY>(addr); NEXT; }
2454 case 0xe6: { II ii = set_N_xix_R<4,DUMMY>(addr); NEXT; }
2455 case 0xee: { II ii = set_N_xix_R<5,DUMMY>(addr); NEXT; }
2456 case 0xf6: { II ii = set_N_xix_R<6,DUMMY>(addr); NEXT; }
2457 case 0xfe: { II ii = set_N_xix_R<7,DUMMY>(addr); NEXT; }
2458 default: UNREACHABLE;
2459 }
2460 }
2461}
2462
2463template<typename T> inline void CPUCore<T>::cpuTracePre()
2464{
2465 start_pc = getPC();
2466}
2467template<typename T> inline void CPUCore<T>::cpuTracePost()
2468{
2469 if (tracingEnabled) [[unlikely]] {
2470 cpuTracePost_slow();
2471 }
2472}
2473template<typename T> void CPUCore<T>::cpuTracePost_slow()
2474{
2475 std::array<byte, 4> opBuf;
2476 std::string dasmOutput;
2477 dasm(*interface, start_pc, opBuf, dasmOutput, T::getTimeFast());
2478 dasmOutput.resize(19, ' '); // alternative: print fixed-size field
2479 std::cout << strCat(hex_string<4>(start_pc),
2480 " : ", dasmOutput,
2481 " AF=", hex_string<4>(getAF()),
2482 " BC=", hex_string<4>(getBC()),
2483 " DE=", hex_string<4>(getDE()),
2484 " HL=", hex_string<4>(getHL()),
2485 " IX=", hex_string<4>(getIX()),
2486 " IY=", hex_string<4>(getIY()),
2487 " SP=", hex_string<4>(getSP()),
2488 '\n')
2489 << std::flush;
2490}
2491
2492template<typename T> ExecIRQ CPUCore<T>::getExecIRQ() const
2493{
2494 if (nmiEdge) [[unlikely]] return ExecIRQ::NMI;
2495 if (IRQStatus && getIFF1() && !prevWasEI()) [[unlikely]] return ExecIRQ::IRQ;
2496 return ExecIRQ::NONE;
2497}
2498
2499template<typename T> void CPUCore<T>::executeSlow(ExecIRQ execIRQ)
2500{
2501 if (execIRQ == ExecIRQ::NMI) [[unlikely]] {
2502 nmiEdge = false;
2503 nmi(); // NMI occurred
2504 } else if (execIRQ == ExecIRQ::IRQ) [[unlikely]] {
2505 // normal interrupt
2506 if (prevWasLDAI()) [[unlikely]] {
2507 // HACK!!!
2508 // The 'ld a,i' or 'ld a,r' instruction copies the IFF2
2509 // bit to the V flag. Though when the Z80 accepts an
2510 // IRQ directly after this instruction, the V flag is 0
2511 // (instead of the expected value 1). This can probably
2512 // be explained if you look at the pipeline of the Z80.
2513 // But for speed reasons we implement it here as a
2514 // fix-up (a hack) in the IRQ routine. This behaviour
2515 // is actually a bug in the Z80.
2516 // Thanks to n_n for reporting this behaviour. I think
2517 // this was discovered by GuyveR800. Also thanks to
2518 // n_n for writing a test program that demonstrates
2519 // this quirk.
2520 // I also wrote a test program that demonstrates this
2521 // behaviour is the same whether 'ld a,i' is preceded
2522 // by a 'ei' instruction or not (so it's not caused by
2523 // the 'delayed IRQ acceptance of ei').
2524 assert(getF() & V_FLAG);
2525 setF(getF() & ~V_FLAG);
2526 }
2527 IRQAccept.signal();
2528 switch (getIM()) {
2529 case 0: irq0();
2530 break;
2531 case 1: irq1();
2532 break;
2533 case 2: irq2();
2534 break;
2535 default:
2537 }
2538 } else if (getHALT()) [[unlikely]] {
2539 // in halt mode
2540 incR(narrow_cast<byte>(T::advanceHalt(T::HALT_STATES, scheduler.getNext())));
2541 setSlowInstructions();
2542 } else {
2543 cpuTracePre();
2544 assert(T::limitReached()); // we want only one instruction
2545 executeInstructions();
2546 endInstruction();
2547
2548 if constexpr (T::IS_R800) {
2549 if (/*unlikely*/(prev2WasCall()) && /*likely*/(!prevWasPopRet())) [[unlikely]] {
2550 // On R800 a CALL or RST instruction not _immediately_
2551 // followed by a (single-byte) POP or RET instruction
2552 // causes an extra cycle in that following instruction.
2553 // No idea why yet. See doc/internal/r800-call.txt
2554 // for more information.
2555 //
2556 // TODO this implementation adds the extra cycle at
2557 // the end of the instruction POP/RET. It is not known
2558 // where in the instruction the real R800 adds this cycle.
2559 T::add(1);
2560 }
2561 }
2562 cpuTracePost();
2563 }
2564}
2565
2566template<typename T> void CPUCore<T>::execute(bool fastForward)
2567{
2568 // In fast-forward mode, breakpoints, watchpoints or debug conditions
2569 // won't trigger. It is possible we already are in break mode, but
2570 // break is ignored in fast-forward mode.
2571 assert(fastForward || !interface->isBreaked());
2572 if (fastForward) {
2573 interface->setFastForward(true);
2574 }
2575 execute2(fastForward);
2576 interface->setFastForward(false);
2577}
2578
2579template<typename T> void CPUCore<T>::execute2(bool fastForward)
2580{
2581 // note: Don't use getTimeFast() here, because 'once in a while' we
2582 // need to CPUClock::sync() to avoid overflow.
2583 // Should be done at least once per second (approx). So only
2584 // once in this method is enough.
2585 scheduler.schedule(T::getTime());
2586 setSlowInstructions();
2587
2588 // Note: we call scheduler _after_ executing the instruction and before
2589 // deciding between executeFast() and executeSlow() (because a
2590 // SyncPoint could set an IRQ and then we must choose executeSlow())
2591 if (fastForward ||
2592 (!interface->anyBreakPoints() && !tracingEnabled)) {
2593 // fast path, no breakpoints, no tracing
2594 do {
2595 if (slowInstructions) {
2596 --slowInstructions;
2597 executeSlow(getExecIRQ());
2598 scheduler.schedule(T::getTimeFast());
2599 } else {
2600 while (slowInstructions == 0) {
2601 T::enableLimit(); // does CPUClock::sync()
2602 if (!T::limitReached()) [[likely]] {
2603 // multiple instructions
2604 executeInstructions();
2605 // note: pipeline only shifted one
2606 // step for multiple instructions
2607 endInstruction();
2608 }
2609 scheduler.schedule(T::getTimeFast());
2610 if (needExitCPULoop()) return;
2611 }
2612 }
2613 } while (!needExitCPULoop());
2614 } else {
2615 do {
2616 if (slowInstructions == 0) {
2617 cpuTracePre();
2618 assert(T::limitReached()); // only one instruction
2619 executeInstructions();
2620 endInstruction();
2621 cpuTracePost();
2622 } else {
2623 --slowInstructions;
2624 executeSlow(getExecIRQ());
2625 }
2626 // Don't use getTimeFast() here, we need a call to
2627 // CPUClock::sync() 'once in a while'. (During a
2628 // reverse fast-forward this wasn't always the case).
2629 scheduler.schedule(T::getTime());
2630
2631 // Only check for breakpoints when we're not about to jump to an IRQ handler.
2632 //
2633 // This fixes the following problem reported by Grauw:
2634 //
2635 // I found a breakpoints bug: sometimes a breakpoint gets hit twice even
2636 // though the code is executed once. This manifests itself in my profiler
2637 // as an imbalance between section begin- and end-calls.
2638 //
2639 // Turns out this occurs when an interrupt occurs exactly on the line of
2640 // the breakpoint, then the breakpoint gets hit before immediately going
2641 // to the ISR, as well as when returning from the ISR.
2642 //
2643 // The IRQ is handled by the Z80 at the end of an instruction. So it
2644 // should change the PC before the next instruction is fetched and the
2645 // breakpoints should be evaluated during instruction fetch.
2646 //
2647 // I think Grauw's analysis is correct. Though for performance reasons we
2648 // don't emulate the Z80 like that: we don't check for IRQs at the end of
2649 // every instruction. In the openMSX emulation model, we can only enter an
2650 // ISR:
2651 // - (One instruction after) switching from DI to EI mode.
2652 // - After emulating device code. This can be:
2653 // * When the Z80 communicated with the device (IO or memory mapped IO).
2654 // * The device had set a synchronization point.
2655 // In all cases disableLimit() gets called which will cause
2656 // limitReached() to return true (and possibly slowInstructions to be > 0).
2657 // So after most emulated Z80 instructions there can't be a pending IRQ, so
2658 // checking for it is wasteful. Also synchronization points are handled
2659 // between emulated Z80 instructions, that means me must check for pending
2660 // IRQs at the start (instead of end) of an instruction.
2661 //
2662 auto execIRQ = getExecIRQ();
2663 if ((execIRQ == ExecIRQ::NONE) &&
2664 interface->checkBreakPoints(getPC())) {
2665 assert(interface->isBreaked());
2666 break;
2667 }
2668 } while (!needExitCPULoop());
2669 }
2670}
2671
2672template<typename T> template<Reg8 R8> ALWAYS_INLINE byte CPUCore<T>::get8() const {
2673 if constexpr (R8 == A) { return getA(); }
2674 else if constexpr (R8 == F) { return getF(); }
2675 else if constexpr (R8 == B) { return getB(); }
2676 else if constexpr (R8 == C) { return getC(); }
2677 else if constexpr (R8 == D) { return getD(); }
2678 else if constexpr (R8 == E) { return getE(); }
2679 else if constexpr (R8 == H) { return getH(); }
2680 else if constexpr (R8 == L) { return getL(); }
2681 else if constexpr (R8 == IXH) { return getIXh(); }
2682 else if constexpr (R8 == IXL) { return getIXl(); }
2683 else if constexpr (R8 == IYH) { return getIYh(); }
2684 else if constexpr (R8 == IYL) { return getIYl(); }
2685 else if constexpr (R8 == REG_I) { return getI(); }
2686 else if constexpr (R8 == REG_R) { return getR(); }
2687 else if constexpr (R8 == DUMMY) { return 0; }
2688 else { UNREACHABLE; }
2689}
2690template<typename T> template<Reg16 R16> ALWAYS_INLINE word CPUCore<T>::get16() const {
2691 if constexpr (R16 == AF) { return getAF(); }
2692 else if constexpr (R16 == BC) { return getBC(); }
2693 else if constexpr (R16 == DE) { return getDE(); }
2694 else if constexpr (R16 == HL) { return getHL(); }
2695 else if constexpr (R16 == IX) { return getIX(); }
2696 else if constexpr (R16 == IY) { return getIY(); }
2697 else if constexpr (R16 == SP) { return getSP(); }
2698 else { UNREACHABLE; }
2699}
2700template<typename T> template<Reg8 R8> ALWAYS_INLINE void CPUCore<T>::set8(byte x) {
2701 if constexpr (R8 == A) { setA(x); }
2702 else if constexpr (R8 == F) { setF(x); }
2703 else if constexpr (R8 == B) { setB(x); }
2704 else if constexpr (R8 == C) { setC(x); }
2705 else if constexpr (R8 == D) { setD(x); }
2706 else if constexpr (R8 == E) { setE(x); }
2707 else if constexpr (R8 == H) { setH(x); }
2708 else if constexpr (R8 == L) { setL(x); }
2709 else if constexpr (R8 == IXH) { setIXh(x); }
2710 else if constexpr (R8 == IXL) { setIXl(x); }
2711 else if constexpr (R8 == IYH) { setIYh(x); }
2712 else if constexpr (R8 == IYL) { setIYl(x); }
2713 else if constexpr (R8 == REG_I) { setI(x); }
2714 else if constexpr (R8 == REG_R) { setR(x); }
2715 else if constexpr (R8 == DUMMY) { /* nothing */ }
2716 else { UNREACHABLE; }
2717}
2718template<typename T> template<Reg16 R16> ALWAYS_INLINE void CPUCore<T>::set16(word x) {
2719 if constexpr (R16 == AF) { setAF(x); }
2720 else if constexpr (R16 == BC) { setBC(x); }
2721 else if constexpr (R16 == DE) { setDE(x); }
2722 else if constexpr (R16 == HL) { setHL(x); }
2723 else if constexpr (R16 == IX) { setIX(x); }
2724 else if constexpr (R16 == IY) { setIY(x); }
2725 else if constexpr (R16 == SP) { setSP(x); }
2726 else { UNREACHABLE; }
2727}
2728
2729// LD r,r
2730template<typename T> template<Reg8 DST, Reg8 SRC, int EE> II CPUCore<T>::ld_R_R() {
2731 set8<DST>(get8<SRC>()); return {1, T::CC_LD_R_R + EE};
2732}
2733
2734// LD SP,ss
2735template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ld_sp_SS() {
2736 setSP(get16<REG>()); return {1, T::CC_LD_SP_HL + EE};
2737}
2738
2739// LD (ss),a
2740template<typename T> template<Reg16 REG> II CPUCore<T>::ld_SS_a() {
2741 T::setMemPtr((getA() << 8) | ((get16<REG>() + 1) & 0xFF));
2742 WRMEM(get16<REG>(), getA(), T::CC_LD_SS_A_1);
2743 return {1, T::CC_LD_SS_A};
2744}
2745
2746// LD (HL),r
2747template<typename T> template<Reg8 SRC> II CPUCore<T>::ld_xhl_R() {
2748 WRMEM(getHL(), get8<SRC>(), T::CC_LD_HL_R_1);
2749 return {1, T::CC_LD_HL_R};
2750}
2751
2752// LD (IXY+e),r
2753template<typename T> template<Reg16 IXY, Reg8 SRC> II CPUCore<T>::ld_xix_R() {
2754 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_LD_XIX_R_1);
2755 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
2756 T::setMemPtr(addr);
2757 WRMEM(addr, get8<SRC>(), T::CC_DD + T::CC_LD_XIX_R_2);
2758 return {2, T::CC_DD + T::CC_LD_XIX_R};
2759}
2760
2761// LD (HL),n
2762template<typename T> II CPUCore<T>::ld_xhl_byte() {
2763 byte val = RDMEM_OPCODE<1>(T::CC_LD_HL_N_1);
2764 WRMEM(getHL(), val, T::CC_LD_HL_N_2);
2765 return {2, T::CC_LD_HL_N};
2766}
2767
2768// LD (IXY+e),n
2769template<typename T> template<Reg16 IXY> II CPUCore<T>::ld_xix_byte() {
2770 unsigned tmp = RD_WORD_PC<1>(T::CC_DD + T::CC_LD_XIX_N_1);
2771 auto ofst = narrow_cast<int8_t>(tmp & 0xFF);
2772 auto val = narrow_cast<byte>(tmp >> 8);
2773 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
2774 T::setMemPtr(addr);
2775 WRMEM(addr, val, T::CC_DD + T::CC_LD_XIX_N_2);
2776 return {3, T::CC_DD + T::CC_LD_XIX_N};
2777}
2778
2779// LD (nn),A
2780template<typename T> II CPUCore<T>::ld_xbyte_a() {
2781 unsigned x = RD_WORD_PC<1>(T::CC_LD_NN_A_1);
2782 T::setMemPtr((getA() << 8) | ((x + 1) & 0xFF));
2783 WRMEM(x, getA(), T::CC_LD_NN_A_2);
2784 return {3, T::CC_LD_NN_A};
2785}
2786
2787// LD (nn),ss
2788template<typename T> template<int EE> inline II CPUCore<T>::WR_NN_Y(word reg) {
2789 unsigned addr = RD_WORD_PC<1>(T::CC_LD_XX_HL_1 + EE);
2790 T::setMemPtr(addr + 1);
2791 WR_WORD(addr, reg, T::CC_LD_XX_HL_2 + EE);
2792 return {3, T::CC_LD_XX_HL + EE};
2793}
2794template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ld_xword_SS() {
2795 return WR_NN_Y<EE >(get16<REG>());
2796}
2797template<typename T> template<Reg16 REG> II CPUCore<T>::ld_xword_SS_ED() {
2798 return WR_NN_Y<T::EE_ED>(get16<REG>());
2799}
2800
2801// LD A,(ss)
2802template<typename T> template<Reg16 REG> II CPUCore<T>::ld_a_SS() {
2803 T::setMemPtr(get16<REG>() + 1);
2804 setA(RDMEM(get16<REG>(), T::CC_LD_A_SS_1));
2805 return {1, T::CC_LD_A_SS};
2806}
2807
2808// LD A,(nn)
2809template<typename T> II CPUCore<T>::ld_a_xbyte() {
2810 unsigned addr = RD_WORD_PC<1>(T::CC_LD_A_NN_1);
2811 T::setMemPtr(addr + 1);
2812 setA(RDMEM(addr, T::CC_LD_A_NN_2));
2813 return {3, T::CC_LD_A_NN};
2814}
2815
2816// LD r,n
2817template<typename T> template<Reg8 DST, int EE> II CPUCore<T>::ld_R_byte() {
2818 set8<DST>(RDMEM_OPCODE<1>(T::CC_LD_R_N_1 + EE)); return {2, T::CC_LD_R_N + EE};
2819}
2820
2821// LD r,(hl)
2822template<typename T> template<Reg8 DST> II CPUCore<T>::ld_R_xhl() {
2823 set8<DST>(RDMEM(getHL(), T::CC_LD_R_HL_1)); return {1, T::CC_LD_R_HL};
2824}
2825
2826// LD r,(IXY+e)
2827template<typename T> template<Reg8 DST, Reg16 IXY> II CPUCore<T>::ld_R_xix() {
2828 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_LD_R_XIX_1);
2829 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
2830 T::setMemPtr(addr);
2831 set8<DST>(RDMEM(addr, T::CC_DD + T::CC_LD_R_XIX_2));
2832 return {2, T::CC_DD + T::CC_LD_R_XIX};
2833}
2834
2835// LD ss,(nn)
2836template<typename T> template<int EE> inline word CPUCore<T>::RD_P_XX() {
2837 unsigned addr = RD_WORD_PC<1>(T::CC_LD_HL_XX_1 + EE);
2838 T::setMemPtr(addr + 1);
2839 return RD_WORD(addr, T::CC_LD_HL_XX_2 + EE);
2840}
2841template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ld_SS_xword() {
2842 set16<REG>(RD_P_XX<EE>()); return {3, T::CC_LD_HL_XX + EE};
2843}
2844template<typename T> template<Reg16 REG> II CPUCore<T>::ld_SS_xword_ED() {
2845 set16<REG>(RD_P_XX<T::EE_ED>()); return {3, T::CC_LD_HL_XX + T::EE_ED};
2846}
2847
2848// LD ss,nn
2849template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ld_SS_word() {
2850 set16<REG>(RD_WORD_PC<1>(T::CC_LD_SS_NN_1 + EE)); return {3, T::CC_LD_SS_NN + EE};
2851}
2852
2853
2854// ADC A,r
2855template<typename T> inline void CPUCore<T>::ADC(byte reg) {
2856 unsigned res = getA() + reg + ((getF() & C_FLAG) ? 1 : 0);
2857 byte f = ((res & 0x100) ? C_FLAG : 0) |
2858 ((getA() ^ res ^ reg) & H_FLAG) |
2859 (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2860 0; // N_FLAG
2861 if constexpr (T::IS_R800) {
2862 f |= table.ZS[res & 0xFF];
2863 f |= byte(getF() & (X_FLAG | Y_FLAG));
2864 } else {
2865 f |= table.ZSXY[res & 0xFF];
2866 }
2867 setF(f);
2868 setA(narrow_cast<byte>(res));
2869}
2870template<typename T> inline II CPUCore<T>::adc_a_a() {
2871 unsigned res = 2 * getA() + ((getF() & C_FLAG) ? 1 : 0);
2872 byte f = ((res & 0x100) ? C_FLAG : 0) |
2873 (res & H_FLAG) |
2874 (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2875 0; // N_FLAG
2876 if constexpr (T::IS_R800) {
2877 f |= table.ZS[res & 0xFF];
2878 f |= byte(getF() & (X_FLAG | Y_FLAG));
2879 } else {
2880 f |= table.ZSXY[res & 0xFF];
2881 }
2882 setF(f);
2883 setA(narrow_cast<byte>(res));
2884 return {1, T::CC_CP_R};
2885}
2886template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::adc_a_R() {
2887 ADC(get8<SRC>()); return {1, T::CC_CP_R + EE};
2888}
2889template<typename T> II CPUCore<T>::adc_a_byte() {
2890 ADC(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2891}
2892template<typename T> II CPUCore<T>::adc_a_xhl() {
2893 ADC(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2894}
2895template<typename T> template<Reg16 IXY> II CPUCore<T>::adc_a_xix() {
2896 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2897 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
2898 T::setMemPtr(addr);
2899 ADC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2900 return {2, T::CC_DD + T::CC_CP_XIX};
2901}
2902
2903// ADD A,r
2904template<typename T> inline void CPUCore<T>::ADD(byte reg) {
2905 unsigned res = getA() + reg;
2906 byte f = ((res & 0x100) ? C_FLAG : 0) |
2907 ((getA() ^ res ^ reg) & H_FLAG) |
2908 (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2909 0; // N_FLAG
2910 if constexpr (T::IS_R800) {
2911 f |= table.ZS[res & 0xFF];
2912 f |= byte(getF() & (X_FLAG | Y_FLAG));
2913 } else {
2914 f |= table.ZSXY[res & 0xFF];
2915 }
2916 setF(f);
2917 setA(narrow_cast<byte>(res));
2918}
2919template<typename T> inline II CPUCore<T>::add_a_a() {
2920 unsigned res = 2 * getA();
2921 byte f = ((res & 0x100) ? C_FLAG : 0) |
2922 (res & H_FLAG) |
2923 (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2924 0; // N_FLAG
2925 if constexpr (T::IS_R800) {
2926 f |= table.ZS[res & 0xFF];
2927 f |= byte(getF() & (X_FLAG | Y_FLAG));
2928 } else {
2929 f |= table.ZSXY[res & 0xFF];
2930 }
2931 setF(f);
2932 setA(narrow_cast<byte>(res));
2933 return {1, T::CC_CP_R};
2934}
2935template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::add_a_R() {
2936 ADD(get8<SRC>()); return {1, T::CC_CP_R + EE};
2937}
2938template<typename T> II CPUCore<T>::add_a_byte() {
2939 ADD(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2940}
2941template<typename T> II CPUCore<T>::add_a_xhl() {
2942 ADD(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2943}
2944template<typename T> template<Reg16 IXY> II CPUCore<T>::add_a_xix() {
2945 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2946 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
2947 T::setMemPtr(addr);
2948 ADD(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2949 return {2, T::CC_DD + T::CC_CP_XIX};
2950}
2951
2952// AND r
2953template<typename T> inline void CPUCore<T>::AND(byte reg) {
2954 setA(getA() & reg);
2955 byte f = 0;
2956 if constexpr (T::IS_R800) {
2957 f |= table.ZSPH[getA()];
2958 f |= byte(getF() & (X_FLAG | Y_FLAG));
2959 } else {
2960 f |= table.ZSPXY[getA()];
2961 f |= H_FLAG;
2962 }
2963 setF(f);
2964}
2965template<typename T> II CPUCore<T>::and_a() {
2966 byte f = 0;
2967 if constexpr (T::IS_R800) {
2968 f |= table.ZSPH[getA()];
2969 f |= byte(getF() & (X_FLAG | Y_FLAG));
2970 } else {
2971 f |= table.ZSPXY[getA()];
2972 f |= H_FLAG;
2973 }
2974 setF(f);
2975 return {1, T::CC_CP_R};
2976}
2977template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::and_R() {
2978 AND(get8<SRC>()); return {1, T::CC_CP_R + EE};
2979}
2980template<typename T> II CPUCore<T>::and_byte() {
2981 AND(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2982}
2983template<typename T> II CPUCore<T>::and_xhl() {
2984 AND(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2985}
2986template<typename T> template<Reg16 IXY> II CPUCore<T>::and_xix() {
2987 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2988 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
2989 T::setMemPtr(addr);
2990 AND(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2991 return {2, T::CC_DD + T::CC_CP_XIX};
2992}
2993
2994// CP r
2995template<typename T> inline void CPUCore<T>::CP(byte reg) {
2996 unsigned q = getA() - reg;
2997 byte f = table.ZS[q & 0xFF] |
2998 ((q & 0x100) ? C_FLAG : 0) |
2999 N_FLAG |
3000 ((getA() ^ byte(q) ^ reg) & H_FLAG) |
3001 (((reg ^ getA()) & (getA() ^ byte(q)) & 0x80) >> 5); // V_FLAG
3002 if constexpr (T::IS_R800) {
3003 f |= byte(getF() & (X_FLAG | Y_FLAG));
3004 } else {
3005 f |= byte(reg & (X_FLAG | Y_FLAG)); // XY from operand, not from result
3006 }
3007 setF(f);
3008}
3009template<typename T> II CPUCore<T>::cp_a() {
3010 byte f = ZS0 | N_FLAG;
3011 if constexpr (T::IS_R800) {
3012 f |= byte(getF() & (X_FLAG | Y_FLAG));
3013 } else {
3014 f |= byte(getA() & (X_FLAG | Y_FLAG)); // XY from operand, not from result
3015 }
3016 setF(f);
3017 return {1, T::CC_CP_R};
3018}
3019template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::cp_R() {
3020 CP(get8<SRC>()); return {1, T::CC_CP_R + EE};
3021}
3022template<typename T> II CPUCore<T>::cp_byte() {
3023 CP(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3024}
3025template<typename T> II CPUCore<T>::cp_xhl() {
3026 CP(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3027}
3028template<typename T> template<Reg16 IXY> II CPUCore<T>::cp_xix() {
3029 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3030 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
3031 T::setMemPtr(addr);
3032 CP(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3033 return {2, T::CC_DD + T::CC_CP_XIX};
3034}
3035
3036// OR r
3037template<typename T> inline void CPUCore<T>::OR(byte reg) {
3038 setA(getA() | reg);
3039 byte f = 0;
3040 if constexpr (T::IS_R800) {
3041 f |= table.ZSP[getA()];
3042 f |= byte(getF() & (X_FLAG | Y_FLAG));
3043 } else {
3044 f |= table.ZSPXY[getA()];
3045 }
3046 setF(f);
3047}
3048template<typename T> II CPUCore<T>::or_a() {
3049 byte f = 0;
3050 if constexpr (T::IS_R800) {
3051 f |= table.ZSP[getA()];
3052 f |= byte(getF() & (X_FLAG | Y_FLAG));
3053 } else {
3054 f |= table.ZSPXY[getA()];
3055 }
3056 setF(f);
3057 return {1, T::CC_CP_R};
3058}
3059template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::or_R() {
3060 OR(get8<SRC>()); return {1, T::CC_CP_R + EE};
3061}
3062template<typename T> II CPUCore<T>::or_byte() {
3063 OR(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3064}
3065template<typename T> II CPUCore<T>::or_xhl() {
3066 OR(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3067}
3068template<typename T> template<Reg16 IXY> II CPUCore<T>::or_xix() {
3069 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3070 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
3071 T::setMemPtr(addr);
3072 OR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3073 return {2, T::CC_DD + T::CC_CP_XIX};
3074}
3075
3076// SBC A,r
3077template<typename T> inline void CPUCore<T>::SBC(byte reg) {
3078 unsigned res = getA() - reg - ((getF() & C_FLAG) ? 1 : 0);
3079 byte f = ((res & 0x100) ? C_FLAG : 0) |
3080 N_FLAG |
3081 ((getA() ^ res ^ reg) & H_FLAG) |
3082 (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3083 if constexpr (T::IS_R800) {
3084 f |= table.ZS[res & 0xFF];
3085 f |= byte(getF() & (X_FLAG | Y_FLAG));
3086 } else {
3087 f |= table.ZSXY[res & 0xFF];
3088 }
3089 setF(f);
3090 setA(narrow_cast<byte>(res));
3091}
3092template<typename T> II CPUCore<T>::sbc_a_a() {
3093 if constexpr (T::IS_R800) {
3094 word t = (getF() & C_FLAG)
3095 ? (255 * 256 | ZS255 | C_FLAG | H_FLAG | N_FLAG)
3096 : ( 0 * 256 | ZS0 | N_FLAG);
3097 setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3098 } else {
3099 setAF((getF() & C_FLAG) ?
3100 (255 * 256 | ZSXY255 | C_FLAG | H_FLAG | N_FLAG) :
3101 ( 0 * 256 | ZSXY0 | N_FLAG));
3102 }
3103 return {1, T::CC_CP_R};
3104}
3105template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::sbc_a_R() {
3106 SBC(get8<SRC>()); return {1, T::CC_CP_R + EE};
3107}
3108template<typename T> II CPUCore<T>::sbc_a_byte() {
3109 SBC(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3110}
3111template<typename T> II CPUCore<T>::sbc_a_xhl() {
3112 SBC(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3113}
3114template<typename T> template<Reg16 IXY> II CPUCore<T>::sbc_a_xix() {
3115 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3116 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
3117 T::setMemPtr(addr);
3118 SBC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3119 return {2, T::CC_DD + T::CC_CP_XIX};
3120}
3121
3122// SUB r
3123template<typename T> inline void CPUCore<T>::SUB(byte reg) {
3124 unsigned res = getA() - reg;
3125 byte f = ((res & 0x100) ? C_FLAG : 0) |
3126 N_FLAG |
3127 ((getA() ^ res ^ reg) & H_FLAG) |
3128 (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3129 if constexpr (T::IS_R800) {
3130 f |= table.ZS[res & 0xFF];
3131 f |= byte(getF() & (X_FLAG | Y_FLAG));
3132 } else {
3133 f |= table.ZSXY[res & 0xFF];
3134 }
3135 setF(f);
3136 setA(narrow_cast<byte>(res));
3137}
3138template<typename T> II CPUCore<T>::sub_a() {
3139 if constexpr (T::IS_R800) {
3140 word t = 0 * 256 | ZS0 | N_FLAG;
3141 setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3142 } else {
3143 setAF(0 * 256 | ZSXY0 | N_FLAG);
3144 }
3145 return {1, T::CC_CP_R};
3146}
3147template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::sub_R() {
3148 SUB(get8<SRC>()); return {1, T::CC_CP_R + EE};
3149}
3150template<typename T> II CPUCore<T>::sub_byte() {
3151 SUB(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3152}
3153template<typename T> II CPUCore<T>::sub_xhl() {
3154 SUB(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3155}
3156template<typename T> template<Reg16 IXY> II CPUCore<T>::sub_xix() {
3157 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3158 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
3159 T::setMemPtr(addr);
3160 SUB(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3161 return {2, T::CC_DD + T::CC_CP_XIX};
3162}
3163
3164// XOR r
3165template<typename T> inline void CPUCore<T>::XOR(byte reg) {
3166 setA(getA() ^ reg);
3167 byte f = 0;
3168 if constexpr (T::IS_R800) {
3169 f |= table.ZSP[getA()];
3170 f |= byte(getF() & (X_FLAG | Y_FLAG));
3171 } else {
3172 f |= table.ZSPXY[getA()];
3173 }
3174 setF(f);
3175}
3176template<typename T> II CPUCore<T>::xor_a() {
3177 if constexpr (T::IS_R800) {
3178 word t = 0 * 256 + ZSP0;
3179 setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3180 } else {
3181 setAF(0 * 256 + ZSPXY0);
3182 }
3183 return {1, T::CC_CP_R};
3184}
3185template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::xor_R() {
3186 XOR(get8<SRC>()); return {1, T::CC_CP_R + EE};
3187}
3188template<typename T> II CPUCore<T>::xor_byte() {
3189 XOR(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3190}
3191template<typename T> II CPUCore<T>::xor_xhl() {
3192 XOR(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3193}
3194template<typename T> template<Reg16 IXY> II CPUCore<T>::xor_xix() {
3195 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3196 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
3197 T::setMemPtr(addr);
3198 XOR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3199 return {2, T::CC_DD + T::CC_CP_XIX};
3200}
3201
3202
3203// DEC r
3204template<typename T> inline byte CPUCore<T>::DEC(byte reg) {
3205 byte res = reg - 1;
3206 byte f = ((reg & ~res & 0x80) >> 5) | // V_FLAG
3207 (((res & 0x0F) + 1) & H_FLAG) |
3208 N_FLAG;
3209 if constexpr (T::IS_R800) {
3210 f |= byte(getF() & (C_FLAG | X_FLAG | Y_FLAG));
3211 f |= table.ZS[res];
3212 } else {
3213 f |= byte(getF() & C_FLAG);
3214 f |= table.ZSXY[res];
3215 }
3216 setF(f);
3217 return res;
3218}
3219template<typename T> template<Reg8 REG, int EE> II CPUCore<T>::dec_R() {
3220 set8<REG>(DEC(get8<REG>())); return {1, T::CC_INC_R + EE};
3221}
3222template<typename T> template<int EE> inline void CPUCore<T>::DEC_X(unsigned x) {
3223 byte val = DEC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3224 WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3225}
3226template<typename T> II CPUCore<T>::dec_xhl() {
3227 DEC_X<0>(getHL());
3228 return {1, T::CC_INC_XHL};
3229}
3230template<typename T> template<Reg16 IXY> II CPUCore<T>::dec_xix() {
3231 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_INC_XIX_1);
3232 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
3233 T::setMemPtr(addr);
3234 DEC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3235 return {2, T::CC_INC_XHL + T::CC_DD + T::EE_INC_XIX};
3236}
3237
3238// INC r
3239template<typename T> inline byte CPUCore<T>::INC(byte reg) {
3240 reg++;
3241 byte f = ((reg & -reg & 0x80) >> 5) | // V_FLAG
3242 (((reg & 0x0F) - 1) & H_FLAG) |
3243 0; // N_FLAG
3244 if constexpr (T::IS_R800) {
3245 f |= byte(getF() & (C_FLAG | X_FLAG | Y_FLAG));
3246 f |= table.ZS[reg];
3247 } else {
3248 f |= byte(getF() & C_FLAG);
3249 f |= table.ZSXY[reg];
3250 }
3251 setF(f);
3252 return reg;
3253}
3254template<typename T> template<Reg8 REG, int EE> II CPUCore<T>::inc_R() {
3255 set8<REG>(INC(get8<REG>())); return {1, T::CC_INC_R + EE};
3256}
3257template<typename T> template<int EE> inline void CPUCore<T>::INC_X(unsigned x) {
3258 byte val = INC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3259 WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3260}
3261template<typename T> II CPUCore<T>::inc_xhl() {
3262 INC_X<0>(getHL());
3263 return {1, T::CC_INC_XHL};
3264}
3265template<typename T> template<Reg16 IXY> II CPUCore<T>::inc_xix() {
3266 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_INC_XIX_1);
3267 unsigned addr = narrow_cast<word>(get16<IXY>() + ofst);
3268 T::setMemPtr(addr);
3269 INC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3270 return {2, T::CC_INC_XHL + T::CC_DD + T::EE_INC_XIX};
3271}
3272
3273
3274// ADC HL,ss
3275template<typename T> template<Reg16 REG> inline II CPUCore<T>::adc_hl_SS() {
3276 unsigned reg = get16<REG>();
3277 T::setMemPtr(getHL() + 1);
3278 unsigned res = getHL() + reg + ((getF() & C_FLAG) ? 1 : 0);
3279 byte f = byte(res >> 16) | // C_FLAG
3280 0; // N_FLAG
3281 if constexpr (T::IS_R800) {
3282 f |= byte(getF() & (X_FLAG | Y_FLAG));
3283 }
3284 if (res & 0xFFFF) {
3285 f |= byte(((getHL() ^ res ^ reg) >> 8) & H_FLAG);
3286 f |= 0; // Z_FLAG
3287 f |= byte(((getHL() ^ res) & (reg ^ res) & 0x8000) >> 13); // V_FLAG
3288 if constexpr (T::IS_R800) {
3289 f |= (res >> 8) & S_FLAG;
3290 } else {
3291 f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3292 }
3293 } else {
3294 f |= byte(((getHL() ^ reg) >> 8) & H_FLAG);
3295 f |= Z_FLAG;
3296 f |= byte((getHL() & reg & 0x8000) >> 13); // V_FLAG
3297 f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3298 }
3299 setF(f);
3300 setHL(narrow_cast<word>(res));
3301 return {1, T::CC_ADC_HL_SS};
3302}
3303template<typename T> II CPUCore<T>::adc_hl_hl() {
3304 T::setMemPtr(getHL() + 1);
3305 unsigned res = 2 * getHL() + ((getF() & C_FLAG) ? 1 : 0);
3306 byte f = byte(res >> 16) | // C_FLAG
3307 0; // N_FLAG
3308 if constexpr (T::IS_R800) {
3309 f |= byte(getF() & (X_FLAG | Y_FLAG));
3310 }
3311 if (res & 0xFFFF) {
3312 f |= 0; // Z_FLAG
3313 f |= byte(((getHL() ^ res) & 0x8000) >> 13); // V_FLAG
3314 if constexpr (T::IS_R800) {
3315 f |= byte((res >> 8) & (H_FLAG | S_FLAG));
3316 } else {
3317 f |= byte((res >> 8) & (H_FLAG | S_FLAG | X_FLAG | Y_FLAG));
3318 }
3319 } else {
3320 f |= Z_FLAG;
3321 f |= byte((getHL() & 0x8000) >> 13); // V_FLAG
3322 f |= 0; // H_FLAG S_FLAG (X_FLAG Y_FLAG)
3323 }
3324 setF(f);
3325 setHL(narrow_cast<word>(res));
3326 return {1, T::CC_ADC_HL_SS};
3327}
3328
3329// ADD HL/IX/IY,ss
3330template<typename T> template<Reg16 REG1, Reg16 REG2, int EE> II CPUCore<T>::add_SS_TT() {
3331 unsigned reg1 = get16<REG1>();
3332 unsigned reg2 = get16<REG2>();
3333 T::setMemPtr(reg1 + 1);
3334 unsigned res = reg1 + reg2;
3335 byte f = byte(((reg1 ^ res ^ reg2) >> 8) & H_FLAG) |
3336 byte(res >> 16) | // C_FLAG
3337 0; // N_FLAG
3338 if constexpr (T::IS_R800) {
3339 f |= byte(getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG));
3340 } else {
3341 f |= byte(getF() & (S_FLAG | Z_FLAG | V_FLAG));
3342 f |= byte((res >> 8) & (X_FLAG | Y_FLAG));
3343 }
3344 setF(f);
3345 set16<REG1>(narrow_cast<word>(res));
3346 return {1, T::CC_ADD_HL_SS + EE};
3347}
3348template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::add_SS_SS() {
3349 unsigned reg = get16<REG>();
3350 T::setMemPtr(reg + 1);
3351 unsigned res = 2 * reg;
3352 byte f = byte(res >> 16) | // C_FLAG
3353 0; // N_FLAG
3354 if constexpr (T::IS_R800) {
3355 f |= byte(getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG));
3356 f |= byte((res >> 8) & H_FLAG);
3357 } else {
3358 f |= byte(getF() & (S_FLAG | Z_FLAG | V_FLAG));
3359 f |= byte((res >> 8) & (H_FLAG | X_FLAG | Y_FLAG));
3360 }
3361 setF(f);
3362 set16<REG>(narrow_cast<word>(res));
3363 return {1, T::CC_ADD_HL_SS + EE};
3364}
3365
3366// SBC HL,ss
3367template<typename T> template<Reg16 REG> inline II CPUCore<T>::sbc_hl_SS() {
3368 unsigned reg = get16<REG>();
3369 T::setMemPtr(getHL() + 1);
3370 unsigned res = getHL() - reg - ((getF() & C_FLAG) ? 1 : 0);
3371 byte f = ((res & 0x10000) ? C_FLAG : 0) |
3372 N_FLAG;
3373 if constexpr (T::IS_R800) {
3374 f |= byte(getF() & (X_FLAG | Y_FLAG));
3375 }
3376 if (res & 0xFFFF) {
3377 f |= byte(((getHL() ^ res ^ reg) >> 8) & H_FLAG);
3378 f |= 0; // Z_FLAG
3379 f |= byte(((reg ^ getHL()) & (getHL() ^ res) & 0x8000) >> 13); // V_FLAG
3380 if constexpr (T::IS_R800) {
3381 f |= byte((res >> 8) & S_FLAG);
3382 } else {
3383 f |= byte((res >> 8) & (S_FLAG | X_FLAG | Y_FLAG));
3384 }
3385 } else {
3386 f |= byte(((getHL() ^ reg) >> 8) & H_FLAG);
3387 f |= Z_FLAG;
3388 f |= byte(((reg ^ getHL()) & getHL() & 0x8000) >> 13); // V_FLAG
3389 f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3390 }
3391 setF(f);
3392 setHL(narrow_cast<word>(res));
3393 return {1, T::CC_ADC_HL_SS};
3394}
3395template<typename T> II CPUCore<T>::sbc_hl_hl() {
3396 T::setMemPtr(getHL() + 1);
3397 byte f = T::IS_R800 ? (getF() & (X_FLAG | Y_FLAG)) : 0;
3398 if (getF() & C_FLAG) {
3399 f |= C_FLAG | H_FLAG | S_FLAG | N_FLAG;
3400 if constexpr (!T::IS_R800) {
3401 f |= X_FLAG | Y_FLAG;
3402 }
3403 setHL(0xFFFF);
3404 } else {
3405 f |= Z_FLAG | N_FLAG;
3406 setHL(0);
3407 }
3408 setF(f);
3409 return {1, T::CC_ADC_HL_SS};
3410}
3411
3412// DEC ss
3413template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::dec_SS() {
3414 set16<REG>(narrow_cast<word>(get16<REG>() - 1)); return {1, T::CC_INC_SS + EE};
3415}
3416
3417// INC ss
3418template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::inc_SS() {
3419 set16<REG>(narrow_cast<word>(get16<REG>() + 1)); return {1, T::CC_INC_SS + EE};
3420}
3421
3422
3423// BIT n,r
3424template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::bit_N_R() {
3425 byte reg = get8<REG>();
3426 byte f = 0; // N_FLAG
3427 if constexpr (T::IS_R800) {
3428 // this is very different from Z80 (not only XY flags)
3429 f |= byte(getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG));
3430 f |= H_FLAG;
3431 f |= (reg & (1 << N)) ? 0 : Z_FLAG;
3432 } else {
3433 f |= table.ZSPH[reg & (1 << N)];
3434 f |= byte(getF() & C_FLAG);
3435 f |= byte(reg & (X_FLAG | Y_FLAG));
3436 }
3437 setF(f);
3438 return {1, T::CC_BIT_R};
3439}
3440template<typename T> template<unsigned N> inline II CPUCore<T>::bit_N_xhl() {
3441 byte m = RDMEM(getHL(), T::CC_BIT_XHL_1) & (1 << N);
3442 byte f = 0; // N_FLAG
3443 if constexpr (T::IS_R800) {
3444 f |= byte(getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG));
3445 f |= H_FLAG;
3446 f |= m ? 0 : Z_FLAG;
3447 } else {
3448 f |= table.ZSPH[m];
3449 f |= byte(getF() & C_FLAG);
3450 f |= byte((T::getMemPtr() >> 8) & (X_FLAG | Y_FLAG));
3451 }
3452 setF(f);
3453 return {1, T::CC_BIT_XHL};
3454}
3455template<typename T> template<unsigned N> inline II CPUCore<T>::bit_N_xix(unsigned addr) {
3456 T::setMemPtr(addr);
3457 byte m = RDMEM(addr, T::CC_DD + T::CC_BIT_XIX_1) & (1 << N);
3458 byte f = 0; // N_FLAG
3459 if constexpr (T::IS_R800) {
3460 f |= byte(getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG));
3461 f |= H_FLAG;
3462 f |= m ? 0 : Z_FLAG;
3463 } else {
3464 f |= table.ZSPH[m];
3465 f |= byte(getF() & C_FLAG);
3466 f |= byte((addr >> 8) & (X_FLAG | Y_FLAG));
3467 }
3468 setF(f);
3469 return {3, T::CC_DD + T::CC_BIT_XIX};
3470}
3471
3472// RES n,r
3473static constexpr byte RES(unsigned b, byte reg) {
3474 return reg & byte(~(1 << b));
3475}
3476template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::res_N_R() {
3477 set8<REG>(RES(N, get8<REG>())); return {1, T::CC_SET_R};
3478}
3479template<typename T> template<int EE> inline byte CPUCore<T>::RES_X(unsigned bit, unsigned addr) {
3480 byte res = RES(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3481 WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3482 return res;
3483}
3484template<typename T> template<unsigned N> II CPUCore<T>::res_N_xhl() {
3485 RES_X<0>(N, getHL()); return {1, T::CC_SET_XHL};
3486}
3487template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::res_N_xix_R(unsigned a) {
3488 T::setMemPtr(a);
3489 set8<REG>(RES_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3490 return {3, T::CC_DD + T::CC_SET_XIX};
3491}
3492
3493// SET n,r
3494static constexpr byte SET(unsigned b, byte reg) {
3495 return reg | byte(1 << b);
3496}
3497template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::set_N_R() {
3498 set8<REG>(SET(N, get8<REG>())); return {1, T::CC_SET_R};
3499}
3500template<typename T> template<int EE> inline byte CPUCore<T>::SET_X(unsigned bit, unsigned addr) {
3501 byte res = SET(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3502 WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3503 return res;
3504}
3505template<typename T> template<unsigned N> II CPUCore<T>::set_N_xhl() {
3506 SET_X<0>(N, getHL()); return {1, T::CC_SET_XHL};
3507}
3508template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::set_N_xix_R(unsigned a) {
3509 T::setMemPtr(a);
3510 set8<REG>(SET_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3511 return {3, T::CC_DD + T::CC_SET_XIX};
3512}
3513
3514// RL r
3515template<typename T> inline byte CPUCore<T>::RL(byte reg) {
3516 byte c = reg >> 7;
3517 reg = narrow_cast<byte>((reg << 1) | ((getF() & C_FLAG) ? 0x01 : 0));
3518 byte f = c ? C_FLAG : 0;
3519 if constexpr (T::IS_R800) {
3520 f |= table.ZSP[reg];
3521 f |= byte(getF() & (X_FLAG | Y_FLAG));
3522 } else {
3523 f |= table.ZSPXY[reg];
3524 }
3525 setF(f);
3526 return reg;
3527}
3528template<typename T> template<int EE> inline byte CPUCore<T>::RL_X(unsigned x) {
3529 byte res = RL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3530 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3531 return res;
3532}
3533template<typename T> template<Reg8 REG> II CPUCore<T>::rl_R() {
3534 set8<REG>(RL(get8<REG>())); return {1, T::CC_SET_R};
3535}
3536template<typename T> II CPUCore<T>::rl_xhl() {
3537 RL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3538}
3539template<typename T> template<Reg8 REG> II CPUCore<T>::rl_xix_R(unsigned a) {
3540 T::setMemPtr(a);
3541 set8<REG>(RL_X<T::CC_DD + T::EE_SET_XIX>(a));
3542 return {3, T::CC_DD + T::CC_SET_XIX};
3543}
3544
3545// RLC r
3546template<typename T> inline byte CPUCore<T>::RLC(byte reg) {
3547 byte c = reg >> 7;
3548 reg = narrow_cast<byte>((reg << 1) | c);
3549 byte f = c ? C_FLAG : 0;
3550 if constexpr (T::IS_R800) {
3551 f |= table.ZSP[reg];
3552 f |= byte(getF() & (X_FLAG | Y_FLAG));
3553 } else {
3554 f |= table.ZSPXY[reg];
3555 }
3556 setF(f);
3557 return reg;
3558}
3559template<typename T> template<int EE> inline byte CPUCore<T>::RLC_X(unsigned x) {
3560 byte res = RLC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3561 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3562 return res;
3563}
3564template<typename T> template<Reg8 REG> II CPUCore<T>::rlc_R() {
3565 set8<REG>(RLC(get8<REG>())); return {1, T::CC_SET_R};
3566}
3567template<typename T> II CPUCore<T>::rlc_xhl() {
3568 RLC_X<0>(getHL()); return {1, T::CC_SET_XHL};
3569}
3570template<typename T> template<Reg8 REG> II CPUCore<T>::rlc_xix_R(unsigned a) {
3571 T::setMemPtr(a);
3572 set8<REG>(RLC_X<T::CC_DD + T::EE_SET_XIX>(a));
3573 return {3, T::CC_DD + T::CC_SET_XIX};
3574}
3575
3576// RR r
3577template<typename T> inline byte CPUCore<T>::RR(byte reg) {
3578 byte c = reg & 1;
3579 reg = narrow_cast<byte>((reg >> 1) | ((getF() & C_FLAG) << 7));
3580 byte f = c ? C_FLAG : 0;
3581 if constexpr (T::IS_R800) {
3582 f |= table.ZSP[reg];
3583 f |= byte(getF() & (X_FLAG | Y_FLAG));
3584 } else {
3585 f |= table.ZSPXY[reg];
3586 }
3587 setF(f);
3588 return reg;
3589}
3590template<typename T> template<int EE> inline byte CPUCore<T>::RR_X(unsigned x) {
3591 byte res = RR(RDMEM(x, T::CC_SET_XHL_1 + EE));
3592 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3593 return res;
3594}
3595template<typename T> template<Reg8 REG> II CPUCore<T>::rr_R() {
3596 set8<REG>(RR(get8<REG>())); return {1, T::CC_SET_R};
3597}
3598template<typename T> II CPUCore<T>::rr_xhl() {
3599 RR_X<0>(getHL()); return {1, T::CC_SET_XHL};
3600}
3601template<typename T> template<Reg8 REG> II CPUCore<T>::rr_xix_R(unsigned a) {
3602 T::setMemPtr(a);
3603 set8<REG>(RR_X<T::CC_DD + T::EE_SET_XIX>(a));
3604 return {3, T::CC_DD + T::CC_SET_XIX};
3605}
3606
3607// RRC r
3608template<typename T> inline byte CPUCore<T>::RRC(byte reg) {
3609 byte c = reg & 1;
3610 reg = narrow_cast<byte>((reg >> 1) | (c << 7));
3611 byte f = c ? C_FLAG : 0;
3612 if constexpr (T::IS_R800) {
3613 f |= table.ZSP[reg];
3614 f |= byte(getF() & (X_FLAG | Y_FLAG));
3615 } else {
3616 f |= table.ZSPXY[reg];
3617 }
3618 setF(f);
3619 return reg;
3620}
3621template<typename T> template<int EE> inline byte CPUCore<T>::RRC_X(unsigned x) {
3622 byte res = RRC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3623 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3624 return res;
3625}
3626template<typename T> template<Reg8 REG> II CPUCore<T>::rrc_R() {
3627 set8<REG>(RRC(get8<REG>())); return {1, T::CC_SET_R};
3628}
3629template<typename T> II CPUCore<T>::rrc_xhl() {
3630 RRC_X<0>(getHL()); return {1, T::CC_SET_XHL};
3631}
3632template<typename T> template<Reg8 REG> II CPUCore<T>::rrc_xix_R(unsigned a) {
3633 T::setMemPtr(a);
3634 set8<REG>(RRC_X<T::CC_DD + T::EE_SET_XIX>(a));
3635 return {3, T::CC_DD + T::CC_SET_XIX};
3636}
3637
3638// SLA r
3639template<typename T> inline byte CPUCore<T>::SLA(byte reg) {
3640 byte c = reg >> 7;
3641 reg <<= 1;
3642 byte f = c ? C_FLAG : 0;
3643 if constexpr (T::IS_R800) {
3644 f |= table.ZSP[reg];
3645 f |= byte(getF() & (X_FLAG | Y_FLAG));
3646 } else {
3647 f |= table.ZSPXY[reg];
3648 }
3649 setF(f);
3650 return reg;
3651}
3652template<typename T> template<int EE> inline byte CPUCore<T>::SLA_X(unsigned x) {
3653 byte res = SLA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3654 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3655 return res;
3656}
3657template<typename T> template<Reg8 REG> II CPUCore<T>::sla_R() {
3658 set8<REG>(SLA(get8<REG>())); return {1, T::CC_SET_R};
3659}
3660template<typename T> II CPUCore<T>::sla_xhl() {
3661 SLA_X<0>(getHL()); return {1, T::CC_SET_XHL};
3662}
3663template<typename T> template<Reg8 REG> II CPUCore<T>::sla_xix_R(unsigned a) {
3664 T::setMemPtr(a);
3665 set8<REG>(SLA_X<T::CC_DD + T::EE_SET_XIX>(a));
3666 return {3, T::CC_DD + T::CC_SET_XIX};
3667}
3668
3669// SLL r
3670template<typename T> inline byte CPUCore<T>::SLL(byte reg) {
3671 assert(!T::IS_R800); // this instruction is Z80-only
3672 byte c = reg >> 7;
3673 reg = narrow_cast<byte>((reg << 1) | 1);
3674 byte f = c ? C_FLAG : 0;
3675 f |= table.ZSPXY[reg];
3676 setF(f);
3677 return reg;
3678}
3679template<typename T> template<int EE> inline byte CPUCore<T>::SLL_X(unsigned x) {
3680 byte res = SLL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3681 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3682 return res;
3683}
3684template<typename T> template<Reg8 REG> II CPUCore<T>::sll_R() {
3685 set8<REG>(SLL(get8<REG>())); return {1, T::CC_SET_R};
3686}
3687template<typename T> II CPUCore<T>::sll_xhl() {
3688 SLL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3689}
3690template<typename T> template<Reg8 REG> II CPUCore<T>::sll_xix_R(unsigned a) {
3691 T::setMemPtr(a);
3692 set8<REG>(SLL_X<T::CC_DD + T::EE_SET_XIX>(a));
3693 return {3, T::CC_DD + T::CC_SET_XIX};
3694}
3695template<typename T> II CPUCore<T>::sll2() {
3696 assert(T::IS_R800); // this instruction is R800-only
3697 byte f = (getF() & (X_FLAG | Y_FLAG)) |
3698 (getA() >> 7) | // C_FLAG
3699 0; // all other flags zero
3700 setF(f);
3701 return {3, T::CC_DD + T::CC_SET_XIX}; // TODO
3702}
3703
3704// SRA r
3705template<typename T> inline byte CPUCore<T>::SRA(byte reg) {
3706 byte c = reg & 1;
3707 reg = (reg >> 1) | (reg & 0x80);
3708 byte f = c ? C_FLAG : 0;
3709 if constexpr (T::IS_R800) {
3710 f |= table.ZSP[reg];
3711 f |= byte(getF() & (X_FLAG | Y_FLAG));
3712 } else {
3713 f |= table.ZSPXY[reg];
3714 }
3715 setF(f);
3716 return reg;
3717}
3718template<typename T> template<int EE> inline byte CPUCore<T>::SRA_X(unsigned x) {
3719 byte res = SRA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3720 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3721 return res;
3722}
3723template<typename T> template<Reg8 REG> II CPUCore<T>::sra_R() {
3724 set8<REG>(SRA(get8<REG>())); return {1, T::CC_SET_R};
3725}
3726template<typename T> II CPUCore<T>::sra_xhl() {
3727 SRA_X<0>(getHL()); return {1, T::CC_SET_XHL};
3728}
3729template<typename T> template<Reg8 REG> II CPUCore<T>::sra_xix_R(unsigned a) {
3730 T::setMemPtr(a);
3731 set8<REG>(SRA_X<T::CC_DD + T::EE_SET_XIX>(a));
3732 return {3, T::CC_DD + T::CC_SET_XIX};
3733}
3734
3735// SRL R
3736template<typename T> inline byte CPUCore<T>::SRL(byte reg) {
3737 byte c = reg & 1;
3738 reg >>= 1;
3739 byte f = c ? C_FLAG : 0;
3740 if constexpr (T::IS_R800) {
3741 f |= table.ZSP[reg];
3742 f |= byte(getF() & (X_FLAG | Y_FLAG));
3743 } else {
3744 f |= table.ZSPXY[reg];
3745 }
3746 setF(f);
3747 return reg;
3748}
3749template<typename T> template<int EE> inline byte CPUCore<T>::SRL_X(unsigned x) {
3750 byte res = SRL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3751 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3752 return res;
3753}
3754template<typename T> template<Reg8 REG> II CPUCore<T>::srl_R() {
3755 set8<REG>(SRL(get8<REG>())); return {1, T::CC_SET_R};
3756}
3757template<typename T> II CPUCore<T>::srl_xhl() {
3758 SRL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3759}
3760template<typename T> template<Reg8 REG> II CPUCore<T>::srl_xix_R(unsigned a) {
3761 T::setMemPtr(a);
3762 set8<REG>(SRL_X<T::CC_DD + T::EE_SET_XIX>(a));
3763 return {3, T::CC_DD + T::CC_SET_XIX};
3764}
3765
3766// RLA RLCA RRA RRCA
3767template<typename T> II CPUCore<T>::rla() {
3768 byte c = getF() & C_FLAG;
3769 byte f = (getA() & 0x80) ? C_FLAG : 0;
3770 if constexpr (T::IS_R800) {
3771 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG));
3772 } else {
3773 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG));
3774 }
3775 setA(narrow_cast<byte>((getA() << 1) | (c ? 1 : 0)));
3776 if constexpr (!T::IS_R800) {
3777 f |= byte(getA() & (X_FLAG | Y_FLAG));
3778 }
3779 setF(f);
3780 return {1, T::CC_RLA};
3781}
3782template<typename T> II CPUCore<T>::rlca() {
3783 setA(narrow_cast<byte>((getA() << 1) | (getA() >> 7)));
3784 byte f = 0;
3785 if constexpr (T::IS_R800) {
3786 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG));
3787 f |= byte(getA() & C_FLAG);
3788 } else {
3789 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG));
3790 f |= byte(getA() & (Y_FLAG | X_FLAG | C_FLAG));
3791 }
3792 setF(f);
3793 return {1, T::CC_RLA};
3794}
3795template<typename T> II CPUCore<T>::rra() {
3796 auto c = byte((getF() & C_FLAG) << 7);
3797 byte f = (getA() & 0x01) ? C_FLAG : 0;
3798 if constexpr (T::IS_R800) {
3799 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG));
3800 } else {
3801 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG));
3802 }
3803 setA((getA() >> 1) | c);
3804 if constexpr (!T::IS_R800) {
3805 f |= byte(getA() & (X_FLAG | Y_FLAG));
3806 }
3807 setF(f);
3808 return {1, T::CC_RLA};
3809}
3810template<typename T> II CPUCore<T>::rrca() {
3811 byte f = getA() & C_FLAG;
3812 if constexpr (T::IS_R800) {
3813 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG));
3814 } else {
3815 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG));
3816 }
3817 setA(narrow_cast<byte>((getA() >> 1) | (getA() << 7)));
3818 if constexpr (!T::IS_R800) {
3819 f |= byte(getA() & (X_FLAG | Y_FLAG));
3820 }
3821 setF(f);
3822 return {1, T::CC_RLA};
3823}
3824
3825
3826// RLD
3827template<typename T> II CPUCore<T>::rld() {
3828 byte val = RDMEM(getHL(), T::CC_RLD_1);
3829 T::setMemPtr(getHL() + 1);
3830 WRMEM(getHL(), narrow_cast<byte>((val << 4) | (getA() & 0x0F)), T::CC_RLD_2);
3831 setA((getA() & 0xF0) | (val >> 4));
3832 byte f = 0;
3833 if constexpr (T::IS_R800) {
3834 f |= byte(getF() & (C_FLAG | X_FLAG | Y_FLAG));
3835 f |= table.ZSP[getA()];
3836 } else {
3837 f |= byte(getF() & C_FLAG);
3838 f |= table.ZSPXY[getA()];
3839 }
3840 setF(f);
3841 return {1, T::CC_RLD};
3842}
3843
3844// RRD
3845template<typename T> II CPUCore<T>::rrd() {
3846 byte val = RDMEM(getHL(), T::CC_RLD_1);
3847 T::setMemPtr(getHL() + 1);
3848 WRMEM(getHL(), narrow_cast<byte>((val >> 4) | (getA() << 4)), T::CC_RLD_2);
3849 setA((getA() & 0xF0) | (val & 0x0F));
3850 byte f = 0;
3851 if constexpr (T::IS_R800) {
3852 f |= byte(getF() & (C_FLAG | X_FLAG | Y_FLAG));
3853 f |= table.ZSP[getA()];
3854 } else {
3855 f |= byte(getF() & C_FLAG);
3856 f |= table.ZSPXY[getA()];
3857 }
3858 setF(f);
3859 return {1, T::CC_RLD};
3860}
3861
3862
3863// PUSH ss
3864template<typename T> template<int EE> inline void CPUCore<T>::PUSH(word reg) {
3865 setSP(getSP() - 2);
3866 WR_WORD_rev<true, true>(getSP(), reg, T::CC_PUSH_1 + EE);
3867}
3868template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::push_SS() {
3869 PUSH<EE>(get16<REG>()); return {1, T::CC_PUSH + EE};
3870}
3871
3872// POP ss
3873template<typename T> template<int EE> inline word CPUCore<T>::POP() {
3874 word addr = getSP();
3875 setSP(addr + 2);
3876 if constexpr (T::IS_R800) {
3877 // handles both POP and RET instructions (RET with condition = true)
3878 if constexpr (EE == 0) { // not reti/retn, not pop ix/iy
3879 setCurrentPopRet();
3880 // No need for setSlowInstructions()
3881 // -> this only matters directly after a CALL
3882 // instruction and in that case we're still
3883 // executing slow instructions.
3884 }
3885 }
3886 return RD_WORD(addr, T::CC_POP_1 + EE);
3887}
3888template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::pop_SS() {
3889 set16<REG>(POP<EE>()); return {1, T::CC_POP + EE};
3890}
3891
3892
3893// CALL nn / CALL cc,nn
3894template<typename T> template<typename COND> II CPUCore<T>::call(COND cond) {
3895 word addr = RD_WORD_PC<1>(T::CC_CALL_1);
3896 T::setMemPtr(addr);
3897 if (cond(getF())) {
3898 PUSH<T::EE_CALL>(getPC() + 3);
3899 setPC(addr);
3900 if constexpr (T::IS_R800) {
3901 setCurrentCall();
3902 setSlowInstructions();
3903 }
3904 return {0/*3*/, T::CC_CALL_A};
3905 } else {
3906 return {3, T::CC_CALL_B};
3907 }
3908}
3909
3910
3911// RST n
3912template<typename T> template<unsigned ADDR> II CPUCore<T>::rst() {
3913 PUSH<0>(getPC() + 1);
3914 T::setMemPtr(ADDR);
3915 setPC(ADDR);
3916 if constexpr (T::IS_R800) {
3917 setCurrentCall();
3918 setSlowInstructions();
3919 }
3920 return {0/*1*/, T::CC_RST};
3921}
3922
3923
3924// RET
3925template<typename T> template<int EE, typename COND> inline II CPUCore<T>::RET(COND cond) {
3926 if (cond(getF())) {
3927 auto addr = POP<EE>();
3928 T::setMemPtr(addr);
3929 setPC(addr);
3930 return {0/*1*/, T::CC_RET_A + EE};
3931 } else {
3932 return {1, T::CC_RET_B + EE};
3933 }
3934}
3935template<typename T> template<typename COND> II CPUCore<T>::ret(COND cond) {
3936 return RET<T::EE_RET_C>(cond);
3937}
3938template<typename T> II CPUCore<T>::ret() {
3939 return RET<0>(CondTrue());
3940}
3941template<typename T> II CPUCore<T>::retn() { // also reti
3942 setIFF1(getIFF2());
3943 setSlowInstructions();
3944 return RET<T::EE_RETN>(CondTrue());
3945}
3946
3947
3948// JP ss
3949template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::jp_SS() {
3950 setPC(get16<REG>()); T::R800ForcePageBreak(); return {0/*1*/, T::CC_JP_HL + EE};
3951}
3952
3953// JP nn / JP cc,nn
3954template<typename T> template<typename COND> II CPUCore<T>::jp(COND cond) {
3955 word addr = RD_WORD_PC<1>(T::CC_JP_1);
3956 T::setMemPtr(addr);
3957 if (cond(getF())) {
3958 setPC(addr);
3959 T::R800ForcePageBreak();
3960 return {0/*3*/, T::CC_JP_A};
3961 } else {
3962 return {3, T::CC_JP_B};
3963 }
3964}
3965
3966// JR e
3967template<typename T> template<typename COND> II CPUCore<T>::jr(COND cond) {
3968 int8_t ofst = RDMEM_OPCODE<1>(T::CC_JR_1);
3969 if (cond(getF())) {
3970 if (((getPC() + 2) & 0xFF) == 0) {
3971 // On R800, when this instruction is located in the
3972 // last two byte of a page (a page is a 256-byte
3973 // (aligned) memory block) and even if we jump back,
3974 // thus fetching the next opcode byte does not cause a
3975 // page-break, there still is one cycle overhead. It's
3976 // as-if there is a page-break.
3977 //
3978 // This could be explained by some (very limited)
3979 // pipeline behaviour in R800: it seems that the
3980 // decision to cause a page-break on the next
3981 // instruction is already made before the jump
3982 // destination address for the current instruction is
3983 // calculated (though a destination address in another
3984 // page is also a reason for a page-break).
3985 //
3986 // It's likely all instructions behave like this, but I
3987 // think we can get away with only explicitly emulating
3988 // this behaviour in the djnz and the jr (conditional
3989 // or not) instructions: all other instructions that
3990 // cause the PC to change in a non-incremental way do
3991 // already force a page-break for another reason, so
3992 // this effect is masked. Examples of such instructions
3993 // are: JP, RET, CALL, RST, all repeated block
3994 // instructions, accepting an IRQ, (are there more
3995 // instructions or events that change PC?)
3996 //
3997 // See doc/r800-djnz.txt for more details.
3998 T::R800ForcePageBreak();
3999 }
4000 setPC(narrow_cast<word>(getPC() + 2 + ofst));
4001 T::setMemPtr(getPC());
4002 return {0/*2*/, T::CC_JR_A};
4003 } else {
4004 return {2, T::CC_JR_B};
4005 }
4006}
4007
4008// DJNZ e
4009template<typename T> II CPUCore<T>::djnz() {
4010 byte b = getB() - 1;
4011 setB(b);
4012 int8_t ofst = RDMEM_OPCODE<1>(T::CC_JR_1 + T::EE_DJNZ);
4013 if (b) {
4014 if (((getPC() + 2) & 0xFF) == 0) {
4015 // See comment in jr()
4016 T::R800ForcePageBreak();
4017 }
4018 setPC(narrow_cast<word>(getPC() + 2 + ofst));
4019 T::setMemPtr(getPC());
4020 return {0/*2*/, T::CC_JR_A + T::EE_DJNZ};
4021 } else {
4022 return {2, T::CC_JR_B + T::EE_DJNZ};
4023 }
4024}
4025
4026// EX (SP),ss
4027template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ex_xsp_SS() {
4028 word res = RD_WORD_impl<true, false>(getSP(), T::CC_EX_SP_HL_1 + EE);
4029 T::setMemPtr(res);
4030 WR_WORD_rev<false, true>(getSP(), get16<REG>(), T::CC_EX_SP_HL_2 + EE);
4031 set16<REG>(res);
4032 return {1, T::CC_EX_SP_HL + EE};
4033}
4034
4035// IN r,(c)
4036template<typename T> template<Reg8 REG> II CPUCore<T>::in_R_c() {
4037 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_IN_R_C_1);
4038 T::setMemPtr(getBC() + 1);
4039 byte res = READ_PORT(getBC(), T::CC_IN_R_C_1);
4040 byte f = 0;
4041 if constexpr (T::IS_R800) {
4042 f |= byte(getF() & (C_FLAG | X_FLAG | Y_FLAG));
4043 f |= table.ZSP[res];
4044 } else {
4045 f |= byte(getF() & C_FLAG);
4046 f |= table.ZSPXY[res];
4047 }
4048 setF(f);
4049 set8<REG>(res);
4050 return {1, T::CC_IN_R_C};
4051}
4052
4053// IN a,(n)
4054template<typename T> II CPUCore<T>::in_a_byte() {
4055 unsigned y = RDMEM_OPCODE<1>(T::CC_IN_A_N_1) + 256 * getA();
4056 T::setMemPtr(y + 1);
4057 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_IN_A_N_2);
4058 setA(READ_PORT(narrow_cast<word>(y), T::CC_IN_A_N_2));
4059 return {2, T::CC_IN_A_N};
4060}
4061
4062// OUT (c),r
4063template<typename T> template<Reg8 REG> II CPUCore<T>::out_c_R() {
4064 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4065 T::setMemPtr(getBC() + 1);
4066 WRITE_PORT(getBC(), get8<REG>(), T::CC_OUT_C_R_1);
4067 return {1, T::CC_OUT_C_R};
4068}
4069template<typename T> II CPUCore<T>::out_c_0() {
4070 // TODO not on R800
4071 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4072 T::setMemPtr(getBC() + 1);
4073 byte out_c_x = isCMOS ? 255 : 0;
4074 WRITE_PORT(getBC(), out_c_x, T::CC_OUT_C_R_1);
4075 return {1, T::CC_OUT_C_R};
4076}
4077
4078// OUT (n),a
4079template<typename T> II CPUCore<T>::out_byte_a() {
4080 byte port = RDMEM_OPCODE<1>(T::CC_OUT_N_A_1);
4081 auto y = narrow_cast<word>((getA() << 8) | port);
4082 T::setMemPtr((getA() << 8) | ((port + 1) & 255));
4083 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_OUT_N_A_2);
4084 WRITE_PORT(y, getA(), T::CC_OUT_N_A_2);
4085 return {2, T::CC_OUT_N_A};
4086}
4087
4088
4089// block CP
4090template<typename T> inline II CPUCore<T>::BLOCK_CP(int increase, bool repeat) {
4091 T::setMemPtr(T::getMemPtr() + increase);
4092 byte val = RDMEM(getHL(), T::CC_CPI_1);
4093 byte res = getA() - val;
4094 setHL(narrow_cast<word>(getHL() + increase));
4095 setBC(getBC() - 1);
4096 byte f = ((getA() ^ val ^ res) & H_FLAG) |
4097 table.ZS[res] |
4098 N_FLAG |
4099 (getBC() ? V_FLAG : 0);
4100 if constexpr (T::IS_R800) {
4101 f |= byte(getF() & (C_FLAG | X_FLAG | Y_FLAG));
4102 } else {
4103 f |= byte(getF() & C_FLAG);
4104 unsigned k = res - ((f & H_FLAG) >> 4);
4105 f |= (k << 4) & Y_FLAG; // bit 1 -> flag 5
4106 f |= k & X_FLAG; // bit 3 -> flag 3
4107 }
4108 setF(f);
4109 if (repeat && getBC() && res) {
4110 //setPC(getPC() - 2);
4111 T::setMemPtr(getPC() + 1);
4112 return {word(-1)/*1*/, T::CC_CPIR};
4113 } else {
4114 return {1, T::CC_CPI};
4115 }
4116}
4117template<typename T> II CPUCore<T>::cpd() { return BLOCK_CP(-1, false); }
4118template<typename T> II CPUCore<T>::cpi() { return BLOCK_CP( 1, false); }
4119template<typename T> II CPUCore<T>::cpdr() { return BLOCK_CP(-1, true ); }
4120template<typename T> II CPUCore<T>::cpir() { return BLOCK_CP( 1, true ); }
4121
4122
4123// block LD
4124template<typename T> inline II CPUCore<T>::BLOCK_LD(int increase, bool repeat) {
4125 byte val = RDMEM(getHL(), T::CC_LDI_1);
4126 WRMEM(getDE(), val, T::CC_LDI_2);
4127 setHL(narrow_cast<word>(getHL() + increase));
4128 setDE(narrow_cast<word>(getDE() + increase));
4129 setBC(getBC() - 1);
4130 byte f = getBC() ? V_FLAG : 0;
4131 if constexpr (T::IS_R800) {
4132 f |= byte(getF() & (S_FLAG | Z_FLAG | C_FLAG | X_FLAG | Y_FLAG));
4133 } else {
4134 f |= byte(getF() & (S_FLAG | Z_FLAG | C_FLAG));
4135 f |= byte(((getA() + val) << 4) & Y_FLAG); // bit 1 -> flag 5
4136 f |= byte((getA() + val) & X_FLAG); // bit 3 -> flag 3
4137 }
4138 setF(f);
4139 if (repeat && getBC()) {
4140 //setPC(getPC() - 2);
4141 T::setMemPtr(getPC() + 1);
4142 return {word(-1)/*1*/, T::CC_LDIR};
4143 } else {
4144 return {1, T::CC_LDI};
4145 }
4146}
4147template<typename T> II CPUCore<T>::ldd() { return BLOCK_LD(-1, false); }
4148template<typename T> II CPUCore<T>::ldi() { return BLOCK_LD( 1, false); }
4149template<typename T> II CPUCore<T>::lddr() { return BLOCK_LD(-1, true ); }
4150template<typename T> II CPUCore<T>::ldir() { return BLOCK_LD( 1, true ); }
4151
4152
4153// block IN
4154template<typename T> inline II CPUCore<T>::BLOCK_IN(int increase, bool repeat) {
4155 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_INI_1);
4156 T::setMemPtr(getBC() + increase);
4157 setBC(getBC() - 0x100); // decr before use
4158 byte val = READ_PORT(getBC(), T::CC_INI_1);
4159 WRMEM(getHL(), val, T::CC_INI_2);
4160 setHL(narrow_cast<word>(getHL() + increase));
4161 unsigned k = val + ((getC() + increase) & 0xFF);
4162 byte b = getB();
4163 if constexpr (T::IS_R800) {
4164 setF((getF() & ~Z_FLAG) | (b ? 0 : Z_FLAG) | N_FLAG);
4165 } else {
4166 setF(((val & S_FLAG) >> 6) | // N_FLAG
4167 ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4168 table.ZSXY[b] |
4169 (table.ZSPXY[(k & 0x07) ^ b] & P_FLAG));
4170 }
4171 if (repeat && b) {
4172 //setPC(getPC() - 2);
4173 return {word(-1)/*1*/, T::CC_INIR};
4174 } else {
4175 return {1, T::CC_INI};
4176 }
4177}
4178template<typename T> II CPUCore<T>::ind() { return BLOCK_IN(-1, false); }
4179template<typename T> II CPUCore<T>::ini() { return BLOCK_IN( 1, false); }
4180template<typename T> II CPUCore<T>::indr() { return BLOCK_IN(-1, true ); }
4181template<typename T> II CPUCore<T>::inir() { return BLOCK_IN( 1, true ); }
4182
4183
4184// block OUT
4185template<typename T> inline II CPUCore<T>::BLOCK_OUT(int increase, bool repeat) {
4186 byte val = RDMEM(getHL(), T::CC_OUTI_1);
4187 setHL(narrow_cast<word>(getHL() + increase));
4188 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_OUTI_2);
4189 WRITE_PORT(getBC(), val, T::CC_OUTI_2);
4190 setBC(getBC() - 0x100); // decr after use
4191 T::setMemPtr(getBC() + increase);
4192 unsigned k = val + getL();
4193 byte b = getB();
4194 if constexpr (T::IS_R800) {
4195 setF((getF() & ~Z_FLAG) | (b ? 0 : Z_FLAG) | N_FLAG);
4196 } else {
4197 setF(((val & S_FLAG) >> 6) | // N_FLAG
4198 ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4199 table.ZSXY[b] |
4200 (table.ZSPXY[(k & 0x07) ^ b] & P_FLAG));
4201 }
4202 if (repeat && b) {
4203 //setPC(getPC() - 2);
4204 return {word(-1)/*1*/, T::CC_OTIR};
4205 } else {
4206 return {1, T::CC_OUTI};
4207 }
4208}
4209template<typename T> II CPUCore<T>::outd() { return BLOCK_OUT(-1, false); }
4210template<typename T> II CPUCore<T>::outi() { return BLOCK_OUT( 1, false); }
4211template<typename T> II CPUCore<T>::otdr() { return BLOCK_OUT(-1, true ); }
4212template<typename T> II CPUCore<T>::otir() { return BLOCK_OUT( 1, true ); }
4213
4214
4215// various
4216template<typename T> template<int EE> II CPUCore<T>::nop() { return {1, T::CC_NOP + EE}; }
4217template<typename T> II CPUCore<T>::ccf() {
4218 byte f = 0;
4219 if constexpr (T::IS_R800) {
4220 // H flag is different from Z80 (and as always XY flags as well)
4221 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | X_FLAG | Y_FLAG | H_FLAG));
4222 } else {
4223 f |= byte((getF() & C_FLAG) << 4); // H_FLAG
4224 // only set X(Y) flag (don't reset if already set)
4225 if (isCMOS) {
4226 // Y flag is not changed on a CMOS Z80
4227 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | Y_FLAG));
4228 f |= byte((getF() | getA()) & X_FLAG);
4229 } else {
4230 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG));
4231 f |= byte((getF() | getA()) & (X_FLAG | Y_FLAG));
4232 }
4233 }
4234 f ^= C_FLAG;
4235 setF(f);
4236 return {1, T::CC_CCF};
4237}
4238template<typename T> II CPUCore<T>::cpl() {
4239 setA(getA() ^ 0xFF);
4240 byte f = H_FLAG | N_FLAG;
4241 if constexpr (T::IS_R800) {
4242 f |= getF();
4243 } else {
4244 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG));
4245 f |= byte(getA() & (X_FLAG | Y_FLAG));
4246 }
4247 setF(f);
4248 return {1, T::CC_CPL};
4249}
4250template<typename T> II CPUCore<T>::daa() {
4251 byte a = getA();
4252 byte f = getF();
4253 byte adjust = 0;
4254 if ((f & H_FLAG) || ((getA() & 0xf) > 9)) adjust += 6;
4255 if ((f & C_FLAG) || (getA() > 0x99)) adjust += 0x60;
4256 if (f & N_FLAG) a -= adjust; else a += adjust;
4257 if constexpr (T::IS_R800) {
4258 f &= C_FLAG | N_FLAG | X_FLAG | Y_FLAG;
4259 f |= table.ZSP[a];
4260 } else {
4261 f &= C_FLAG | N_FLAG;
4262 f |= table.ZSPXY[a];
4263 }
4264 f |= byte((getA() > 0x99) | ((getA() ^ a) & H_FLAG));
4265 setA(a);
4266 setF(f);
4267 return {1, T::CC_DAA};
4268}
4269template<typename T> II CPUCore<T>::neg() {
4270 // alternative: LUT word negTable[256]
4271 unsigned a = getA();
4272 unsigned res = -signed(a);
4273 byte f = ((res & 0x100) ? C_FLAG : 0) |
4274 N_FLAG |
4275 ((res ^ a) & H_FLAG) |
4276 ((a & res & 0x80) >> 5); // V_FLAG
4277 if constexpr (T::IS_R800) {
4278 f |= table.ZS[res & 0xFF];
4279 f |= byte(getF() & (X_FLAG | Y_FLAG));
4280 } else {
4281 f |= table.ZSXY[res & 0xFF];
4282 }
4283 setF(f);
4284 setA(narrow_cast<byte>(res));
4285 return {1, T::CC_NEG};
4286}
4287template<typename T> II CPUCore<T>::scf() {
4288 byte f = C_FLAG;
4289 if constexpr (T::IS_R800) {
4290 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG));
4291 } else {
4292 // only set X(Y) flag (don't reset if already set)
4293 if (isCMOS) {
4294 // Y flag is not changed on a CMOS Z80
4295 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG | Y_FLAG));
4296 f |= byte((getF() | getA()) & X_FLAG);
4297 } else {
4298 f |= byte(getF() & (S_FLAG | Z_FLAG | P_FLAG));
4299 f |= byte((getF() | getA()) & (X_FLAG | Y_FLAG));
4300 }
4301 }
4302 setF(f);
4303 return {1, T::CC_SCF};
4304}
4305
4306template<typename T> II CPUCore<T>::ex_af_af() {
4307 auto t = getAF2(); setAF2(getAF()); setAF(t);
4308 return {1, T::CC_EX};
4309}
4310template<typename T> II CPUCore<T>::ex_de_hl() {
4311 auto t = getDE(); setDE(getHL()); setHL(t);
4312 return {1, T::CC_EX};
4313}
4314template<typename T> II CPUCore<T>::exx() {
4315 auto t1 = getBC2(); setBC2(getBC()); setBC(t1);
4316 auto t2 = getDE2(); setDE2(getDE()); setDE(t2);
4317 auto t3 = getHL2(); setHL2(getHL()); setHL(t3);
4318 return {1, T::CC_EX};
4319}
4320
4321template<typename T> II CPUCore<T>::di() {
4322 setIFF1(false);
4323 setIFF2(false);
4324 return {1, T::CC_DI};
4325}
4326template<typename T> II CPUCore<T>::ei() {
4327 setIFF1(true);
4328 setIFF2(true);
4329 setCurrentEI(); // no ints directly after this instr
4330 setSlowInstructions();
4331 return {1, T::CC_EI};
4332}
4333template<typename T> II CPUCore<T>::halt() {
4334 setHALT(true);
4335 setSlowInstructions();
4336
4337 if (!(getIFF1() || getIFF2())) {
4338 diHaltCallback.execute();
4339 }
4340 return {1, T::CC_HALT};
4341}
4342template<typename T> template<unsigned N> II CPUCore<T>::im_N() {
4343 setIM(N); return {1, T::CC_IM};
4344}
4345
4346// LD A,I/R
4347template<typename T> template<Reg8 REG> II CPUCore<T>::ld_a_IR() {
4348 setA(get8<REG>());
4349 byte f = getIFF2() ? V_FLAG : 0;
4350 if constexpr (T::IS_R800) {
4351 f |= byte(getF() & (C_FLAG | X_FLAG | Y_FLAG));
4352 f |= table.ZS[getA()];
4353 } else {
4354 f |= byte(getF() & C_FLAG);
4355 f |= table.ZSXY[getA()];
4356 // see comment in the IRQ acceptance part of executeSlow().
4357 setCurrentLDAI(); // only Z80 (not R800) has this quirk
4358 setSlowInstructions();
4359 }
4360 setF(f);
4361 return {1, T::CC_LD_A_I};
4362}
4363
4364// LD I/R,A
4365template<typename T> II CPUCore<T>::ld_r_a() {
4366 // This code sequence:
4367 // XOR A / LD R,A / LD A,R
4368 // gives A=2 for Z80, but A=1 for R800. The difference can possibly be
4369 // explained by a difference in the relative time between writing the
4370 // new value to the R register and increasing the R register per M1
4371 // cycle. Here we implemented the R800 behaviour by storing 'A-1' into
4372 // R, that's good enough for now.
4373 byte val = getA();
4374 if constexpr (T::IS_R800) val -= 1;
4375 setR(val);
4376 return {1, T::CC_LD_A_I};
4377}
4378template<typename T> II CPUCore<T>::ld_i_a() {
4379 setI(getA());
4380 return {1, T::CC_LD_A_I};
4381}
4382
4383// MULUB A,r
4384template<typename T> template<Reg8 REG> II CPUCore<T>::mulub_a_R() {
4385 assert(T::IS_R800); // this instruction is R800-only
4386 // Verified on real R800:
4387 // YHXN flags are unchanged
4388 // SV flags are reset
4389 // Z flag is set when result is zero
4390 // C flag is set when result doesn't fit in 8-bit
4391 setHL(word(getA()) * word(get8<REG>()));
4392 setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4393 0 | // S_FLAG V_FLAG
4394 (getHL() ? 0 : Z_FLAG) |
4395 ((getHL() & 0xFF00) ? C_FLAG : 0));
4396 return {1, T::CC_MULUB};
4397}
4398
4399// MULUW HL,ss
4400template<typename T> template<Reg16 REG> II CPUCore<T>::muluw_hl_SS() {
4401 assert(T::IS_R800); // this instruction is R800-only
4402 // Verified on real R800:
4403 // YHXN flags are unchanged
4404 // SV flags are reset
4405 // Z flag is set when result is zero
4406 // C flag is set when result doesn't fit in 16-bit
4407 uint32_t res = uint32_t(getHL()) * get16<REG>();
4408 setDE(narrow_cast<word>(res >> 16));
4409 setHL(narrow_cast<word>(res >> 0));
4410 setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4411 0 | // S_FLAG V_FLAG
4412 (res ? 0 : Z_FLAG) |
4413 ((res & 0xFFFF0000) ? C_FLAG : 0));
4414 return {1, T::CC_MULUW};
4415}
4416
4417
4418// versions:
4419// 1 -> initial version
4420// 2 -> moved memptr from here to Z80TYPE (and not to R800TYPE)
4421// 3 -> timing of the emulation changed (no changes in serialization)
4422// 4 -> timing of the emulation changed again (see doc/internal/r800-call.txt)
4423// 5 -> added serialization of nmiEdge
4424template<typename T> template<typename Archive>
4425void CPUCore<T>::serialize(Archive& ar, unsigned version)
4426{
4427 T::serialize(ar, version);
4428 ar.serialize("regs", static_cast<CPURegs&>(*this));
4429 if (ar.versionBelow(version, 2)) {
4430 unsigned mPtr = 0; // dummy value (avoid warning)
4431 ar.serialize("memptr", mPtr);
4432 T::setMemPtr(mPtr);
4433 }
4434
4435 if (ar.versionBelow(version, 5)) {
4436 // NMI is unused on MSX and even on systems where it is used nmiEdge
4437 // is true only between the moment the NMI request comes in and the
4438 // moment the Z80 jumps to the NMI handler, so defaulting to false
4439 // is pretty safe.
4440 nmiEdge = false;
4441 } else {
4442 // CPU is deserialized after devices, so nmiEdge is restored to the
4443 // saved version even if IRQHelpers set it on deserialization.
4444 ar.serialize("nmiEdge", nmiEdge);
4445 }
4446
4447 // Don't serialize:
4448 // - IRQStatus, NMIStatus:
4449 // the IRQHelper deserialization makes sure these get the right value
4450 // - slowInstructions, exitLoop:
4451 // serialization happens outside the CPU emulation loop
4452
4453 if constexpr (T::IS_R800) {
4454 if (ar.versionBelow(version, 4)) {
4455 motherboard.getMSXCliComm().printWarning(
4456 "Loading an old savestate: the timing of the R800 "
4457 "emulation has changed. This may cause synchronization "
4458 "problems in replay.");
4459 }
4460 }
4461}
4462
4463// Force template instantiation
4464template class CPUCore<Z80TYPE>;
4465template class CPUCore<R800TYPE>;
4466
4469
4470} // namespace openmsx
#define MAYBE_UNUSED_LABEL
Definition CPUCore.cc:208
#define NEXT
#define NEXT_EI
#define CASE(X)
#define NEXT_STOP
BaseSetting * setting
TclObject t
void lowerIRQ()
Lowers the maskable interrupt count.
Definition CPUCore.cc:450
void setNextSyncPoint(EmuTime::param time)
Definition CPUCore.cc:505
void disasmCommand(Interpreter &interp, std::span< const TclObject > tokens, TclObject &result) const
Definition CPUCore.cc:521
void setFreq(unsigned freq)
Change the clock freq.
Definition CPUCore.cc:549
void execute(bool fastForward)
Definition CPUCore.cc:2566
void warp(EmuTime::param time)
Definition CPUCore.cc:332
CPUCore(MSXMotherBoard &motherboard, const std::string &name, const BooleanSetting &traceSetting, TclCallback &diHaltCallback, EmuTime::param time)
Definition CPUCore.cc:296
void lowerNMI()
Lowers the non-maskable interrupt count.
Definition CPUCore.cc:466
void exitCPULoopSync()
Request to exit the main CPU emulation loop.
Definition CPUCore.cc:411
EmuTime::param getCurrentTime() const
Definition CPUCore.cc:338
void exitCPULoopAsync()
Similar to exitCPULoopSync(), but this method may be called from any thread.
Definition CPUCore.cc:406
void raiseNMI()
Raises the non-maskable interrupt count.
Definition CPUCore.cc:456
void serialize(Archive &ar, unsigned version)
Definition CPUCore.cc:4425
void doReset(EmuTime::param time)
Reset the CPU.
Definition CPUCore.cc:343
void wait(EmuTime::param time)
Definition CPUCore.cc:488
EmuTime waitCycles(EmuTime::param time, unsigned cycles)
Definition CPUCore.cc:495
bool isM1Cycle(unsigned address) const
Definition CPUCore.cc:472
void raiseIRQ()
Raises the maskable interrupt count.
Definition CPUCore.cc:441
void addListElement(const T &t)
Definition TclObject.hh:131
#define NEVER_INLINE
Definition inline.hh:17
#define ALWAYS_INLINE
Definition inline.hh:16
ALWAYS_INLINE uint16_t read_UA_L16(const void *p)
Definition endian.hh:230
ALWAYS_INLINE void write_UA_L16(void *p, uint16_t x)
Definition endian.hh:190
void Table(const char *str_id, int column, ImGuiTableFlags flags, const ImVec2 &outer_size, float inner_width, std::invocable<> auto next)
Definition ImGuiCpp.hh:479
constexpr unsigned LOW
Definition CacheLine.hh:9
constexpr unsigned HIGH
Definition CacheLine.hh:10
constexpr unsigned BITS
Definition CacheLine.hh:6
bool isMainThread()
Returns true when called from the main thread.
Definition Thread.cc:15
This file implemented 3 utility functions:
Definition Autofire.cc:11
uint8_t byte
8 bit unsigned integer
Definition openmsx.hh:26
unsigned dasm(const MSXCPUInterface &interface, uint16_t pc, std::span< uint8_t, 4 > buf, std::string &dest, EmuTime::param time, function_ref< void(std::string &, uint16_t)> appendAddr)
Disassemble.
Definition Dasm.cc:26
uint16_t word
16 bit unsigned integer
Definition openmsx.hh:29
std::array< const EDStorage, 4 > A
std::array< const A, 3 > A2
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
TemporaryString tmpStrCat(Ts &&... ts)
Definition strCat.hh:742
bool operator()(byte f) const
Definition CPUCore.cc:286
bool operator()(byte f) const
Definition CPUCore.cc:290
bool operator()(byte f) const
Definition CPUCore.cc:287
bool operator()(byte f) const
Definition CPUCore.cc:289
bool operator()(byte f) const
Definition CPUCore.cc:292
bool operator()(byte f) const
Definition CPUCore.cc:293
bool operator()(byte f) const
Definition CPUCore.cc:291
bool operator()(byte) const
Definition CPUCore.cc:294
bool operator()(byte f) const
Definition CPUCore.cc:288
std::array< byte, 256 > ZSPXY
Definition CPUCore.cc:236
std::array< byte, 256 > ZSP
Definition CPUCore.cc:235
std::array< byte, 256 > ZSPH
Definition CPUCore.cc:237
std::array< byte, 256 > ZSXY
Definition CPUCore.cc:234
std::array< byte, 256 > ZS
Definition CPUCore.cc:233
#define UNREACHABLE
constexpr void repeat(T n, Op op)
Repeat the given operation 'op' 'n' times.
Definition xrange.hh:147
constexpr auto xrange(T e)
Definition xrange.hh:132