openMSX
CPUCore.cc
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1// MEMORY EMULATION
2// ----------------
3//
4// Memory access emulation is a very important part of the CPU emulation.
5// Because they happen so frequently they really need to be executed as fast as
6// possible otherwise they will completely bring down the speed of the CPU
7// emulation.
8//
9// A very fast way to emulate memory accesses is by simply reading/writing to a
10// 64kb array (for a 16-bit address space). Unfortunately this doesn't allow
11// for memory mapped IO (MMIO). These are memory regions where read/writes
12// trigger side effects, so where we need to execute device-specific code on
13// read or writes. An alternative that does work with MMIO is for every access
14// execute a virtual method call, (this is the approach taken by most current
15// MSX emulators). Unfortunately this is also a lot slower.
16//
17// It is possible to combine the speed of array accesses with the flexibility
18// of virtual methods. In openMSX it's implemented as follows: the 64kb address
19// space is divided in 256 regions of 256 bytes (called cacheLines in the code
20// below). For each such region we store a pointer, if this pointer is nullptr
21// then we have to use the slow way (=virtual method call). If it is not nullptr,
22// the pointer points to a block of memory that can be directly accessed. In
23// some contexts accesses via the pointer are known as backdoor accesses while
24// the accesses directly to the device are known as frontdoor accesses.
25//
26// We keep different pointers for read and write accesses. This allows to also
27// implement ROMs efficiently: read is handled as regular RAM, but writes end
28// up in some dummy memory region. This region is called 'unmappedWrite' in the
29// code. There is also a special region 'unmappedRead', this region is filled
30// with 0xFF and can be used to model (parts of) a device that don't react to
31// reads (so reads return 0xFF).
32//
33// Because of bankswitching (the MSX slot select mechanism, but also e.g.
34// MegaROM backswitching) the memory map as seen by the Z80 is not static. This
35// means that the cacheLine pointers also need to change during runtime. To
36// solve this we made the bankswitch code also responsible for invalidating the
37// cacheLines of the switched region. These pointers are filled-in again in a
38// lazy way: the first read or write to a cache line will first get this
39// pointer (see getReadCacheLine() and getWriteCacheLine() in the code below),
40// from then on this pointer is used for all further accesses to this region,
41// until the cache is invalidated again.
42//
43//
44// INSTRUCTION EMULATION
45// ---------------------
46//
47// UPDATE: the 'threaded interpreter model' is not enabled by default
48// main reason is the huge memory requirement while compiling
49// and that it doesn't work on non-gcc compilers
50//
51// The current implementation is based on a 'threaded interpreter model'. In
52// the text below I'll call the older implementation the 'traditional
53// interpreter model'. From a very high level these two models look like this:
54//
55// Traditional model:
56// while (!needExit()) {
57// byte opcode = fetch(PC++);
58// switch (opcode) {
59// case 0x00: nop(); break;
60// case 0x01: ld_bc_nn(); break;
61// ...
62// }
63// }
64//
65// Threaded model:
66// byte opcode = fetch(PC++); //
67// goto *(table[opcode]); // fetch-and-dispatch
68// // note: the goto * syntax is a gcc extension called computed-gotos
69//
70// op00: nop(); if (!needExit()) [fetch-and-dispatch];
71// op01: ld_bc_nn(); if (!needExit()) [fetch-and-dispatch];
72// ...
73//
74// In the first model there is a central place in the code that fetches (the
75// first byte of) the instruction and based on this byte jumps to the
76// appropriate routine. In the second model, this fetch-and-dispatch logic is
77// duplicated at the end of each instruction.
78//
79// Typically the 'dispatch' part in above paragraph is implemented (either by
80// the compiler or manually using computed goto's) via a jump table. Thus on
81// assembler level via an indirect jump. For the host CPU it's hard to predict
82// the destination address of such an indirect jump, certainly if there's only
83// one such jump for all dispatching (the traditional model). If each
84// instruction has its own indirect jump instruction (the threaded model), it
85// becomes a bit easier, because often one particular z80 instructions is
86// followed by a specific other z80 instruction (or one from a small subset).
87// For example a z80 'cp' instruction is most likely followed by a 'conditional
88// jump' z80 instruction. Modern CPUs are quite sensitive to
89// branch-(mis)predictions, so the above optimization helps quite a lot. I
90// measured a speedup of more than 10%!
91//
92// There is another advantage to the threaded model. Because also the
93// needExit() test is duplicated for each instruction, it becomes possible to
94// tweak it for individual instructions. But first let me explain this
95// exit-test in more detail.
96//
97// These are the main reasons why the emulator should stop emulating CPU
98// instructions:
99// 1) When other devices than the CPU must be emulated (e.g. video frame
100// rendering). In openMSX this is handled by the Scheduler class and
101// actually we don't exit the CPU loop (anymore) for this. Instead we
102// simply execute the device code as a subroutine. Each time right before
103// we access an IO port or do a frontdoor memory access, there is a check
104// whether we should emulate device code (search for schedule() in the code
105// below).
106// 2) To keep the inner CPU loop as fast as possible we don't check for IRQ,
107// NMI or HALT status in this loop. Instead this condition is checked only
108// once at the beginning outside of the loop (if there wasn't a pending IRQ
109// on the first instruction there also won't be one on the second
110// instruction, if all we did was emulating cpu instructions). Now when one
111// of these conditions changes, we must exit the inner loop and re-evaluate
112// them. For example after an EI instruction we must check the IRQ status
113// again.
114// 3) Various reasons like:
115// * Z80/R800 switch
116// * executing a Tcl command (could be a cpu-register debug read)
117// * exit the emulator
118// 4) 'once-in-a-while': To avoid threading problems and race conditions,
119// several threads in openMSX only 'schedule' work that will later be
120// executed by the main emulation thread. The main thread checks for such
121// task outside of the cpu emulation loop. So once-in-a-while we need to
122// exit the loop. The exact timing doesn't matter here because anyway the
123// relative timing between threads is undefined.
124// So for 1) we don't need to do anything (we don't actually exit). For 2) and
125// 3) we need to exit the loop as soon as possible (right after the current
126// instruction is finished). For 4) it's OK to exit 'eventually' (a few hundred
127// z80 instructions late is still OK).
128//
129// Condition 2) is implemented with the 'slowInstructions' mechanism. Condition
130// 3) via exitCPULoopSync() (may only get called by the main emulation thread)
131// and condition 4) is implemented via exitCPULoopAsync() (can be called from
132// any thread).
133//
134// Now back to the exit-test optimization: in the threaded model each
135// instruction ends with:
136//
137// if (needExit()) return
138// byte opcode = fetch(PC++);
139// goto *(table[opcode]);
140//
141// And if we look in more detail at fetch():
142//
143// if (canDoBackdoor(addr)) {
144// doBackdoorAccess(addr);
145// } else {
146// doFrontdoorAccess(addr);
147// }
148//
149// So there are in fact two checks per instruction. This can be reduced to only
150// one check with the following trick:
151//
152// !!!WRONG!!!
153// In the past we optimized this to only check canDoBackdoor() (and make sure
154// canDoBackdoor() returned false when needExit() would return true). This
155// worked rather well, except for one case: when we exit the CPU loop we also
156// check for pending Syncronization points. It is possible such a SyncPoint
157// raises the IRQ line. So it is important to check for exit after every
158// instruction, otherwise we would enter the IRQ routine a couple of
159// instructions too late.
160
161#include "CPUCore.hh"
162#include "MSXCPUInterface.hh"
163#include "Scheduler.hh"
164#include "MSXMotherBoard.hh"
165#include "CliComm.hh"
166#include "TclCallback.hh"
167#include "Dasm.hh"
168#include "Z80.hh"
169#include "R800.hh"
170#include "Thread.hh"
171#include "endian.hh"
172#include "inline.hh"
173#include "unreachable.hh"
174#include "xrange.hh"
175#include <iostream>
176#include <type_traits>
177#include <cassert>
178
179
180//
181// #define USE_COMPUTED_GOTO
182//
183// Computed goto's are not enabled by default:
184// - Computed goto's are a gcc extension, it's not part of the official c++
185// standard. So this will only work if you use gcc as your compiler (it
186// won't work with visual c++ for example)
187// - This is only beneficial on CPUs with branch prediction for indirect jumps
188// and a reasonable amount of cache. For example it is very benefical for a
189// intel core2 cpu (10% faster), but not for a ARM920 (a few percent slower)
190// - Compiling src/cpu/CPUCore.cc with computed goto's enabled is very demanding
191// on the compiler. On older gcc versions it requires up to 1.5GB of memory.
192// But even on more recent gcc versions it still requires around 700MB.
193//
194// Probably the easiest way to enable this, is to pass the -DUSE_COMPUTED_GOTO
195// flag to the compiler. This is for example done in the super-opt flavour.
196// See build/flavour-super-opt.mk
197
198namespace openmsx {
199
200enum Reg8 : int { A, F, B, C, D, E, H, L, IXH, IXL, IYH, IYL, REG_I, REG_R, DUMMY };
201enum Reg16 : int { AF, BC, DE, HL, IX, IY, SP };
202
203// flag positions
204constexpr byte S_FLAG = 0x80;
205constexpr byte Z_FLAG = 0x40;
206constexpr byte Y_FLAG = 0x20;
207constexpr byte H_FLAG = 0x10;
208constexpr byte X_FLAG = 0x08;
209constexpr byte V_FLAG = 0x04;
210constexpr byte P_FLAG = V_FLAG;
211constexpr byte N_FLAG = 0x02;
212constexpr byte C_FLAG = 0x01;
213
214// flag-register lookup tables
215struct Table {
216 byte ZS [256];
217 byte ZSXY [256];
218 byte ZSP [256];
219 byte ZSPXY[256];
220 byte ZSPH [256];
221};
222
223constexpr byte ZS0 = Z_FLAG;
224constexpr byte ZSXY0 = Z_FLAG;
225constexpr byte ZSP0 = Z_FLAG | V_FLAG;
226constexpr byte ZSPXY0 = Z_FLAG | V_FLAG;
227constexpr byte ZS255 = S_FLAG;
228constexpr byte ZSXY255 = S_FLAG | X_FLAG | Y_FLAG;
229
230static constexpr Table initTables()
231{
232 Table table = {};
233
234 for (auto i : xrange(256)) {
235 byte zFlag = (i == 0) ? Z_FLAG : 0;
236 byte sFlag = i & S_FLAG;
237 byte xFlag = i & X_FLAG;
238 byte yFlag = i & Y_FLAG;
239 byte vFlag = V_FLAG;
240 for (int v = 128; v != 0; v >>= 1) {
241 if (i & v) vFlag ^= V_FLAG;
242 }
243 table.ZS [i] = zFlag | sFlag;
244 table.ZSXY [i] = zFlag | sFlag | xFlag | yFlag;
245 table.ZSP [i] = zFlag | sFlag | vFlag;
246 table.ZSPXY[i] = zFlag | sFlag | xFlag | yFlag | vFlag;
247 table.ZSPH [i] = zFlag | sFlag | vFlag | H_FLAG;
248 }
249 assert(table.ZS [ 0] == ZS0);
250 assert(table.ZSXY [ 0] == ZSXY0);
251 assert(table.ZSP [ 0] == ZSP0);
252 assert(table.ZSPXY[ 0] == ZSPXY0);
253 assert(table.ZS [255] == ZS255);
254 assert(table.ZSXY [255] == ZSXY255);
255
256 return table;
257}
258
259constexpr Table table = initTables();
260
261// Global variable, because it should be shared between Z80 and R800.
262// It must not be shared between the CPUs of different MSX machines, but
263// the (logical) lifetime of this variable cannot overlap between execution
264// of two MSX machines.
265static word start_pc;
266
267// conditions
268struct CondC { bool operator()(byte f) const { return (f & C_FLAG) != 0; } };
269struct CondNC { bool operator()(byte f) const { return !(f & C_FLAG); } };
270struct CondZ { bool operator()(byte f) const { return (f & Z_FLAG) != 0; } };
271struct CondNZ { bool operator()(byte f) const { return !(f & Z_FLAG); } };
272struct CondM { bool operator()(byte f) const { return (f & S_FLAG) != 0; } };
273struct CondP { bool operator()(byte f) const { return !(f & S_FLAG); } };
274struct CondPE { bool operator()(byte f) const { return (f & V_FLAG) != 0; } };
275struct CondPO { bool operator()(byte f) const { return !(f & V_FLAG); } };
276struct CondTrue { bool operator()(byte /*f*/) const { return true; } };
277
278template<typename T> CPUCore<T>::CPUCore(
279 MSXMotherBoard& motherboard_, const std::string& name,
280 const BooleanSetting& traceSetting_,
281 TclCallback& diHaltCallback_, EmuTime::param time)
282 : CPURegs(T::IS_R800)
283 , T(time, motherboard_.getScheduler())
284 , motherboard(motherboard_)
285 , scheduler(motherboard.getScheduler())
286 , interface(nullptr)
287 , traceSetting(traceSetting_)
288 , diHaltCallback(diHaltCallback_)
289 , IRQStatus(motherboard.getDebugger(), name + ".pendingIRQ",
290 "Non-zero if there are pending IRQs (thus CPU would enter "
291 "interrupt routine in EI mode).",
292 0)
293 , IRQAccept(motherboard.getDebugger(), name + ".acceptIRQ",
294 "This probe is only useful to set a breakpoint on (the value "
295 "return by read is meaningless). The breakpoint gets triggered "
296 "right after the CPU accepted an IRQ.")
297 , freqLocked(
298 motherboard.getCommandController(), tmpStrCat(name, "_freq_locked"),
299 "real (locked) or custom (unlocked) CPU frequency",
300 true)
301 , freqValue(
302 motherboard.getCommandController(), tmpStrCat(name, "_freq"),
303 "custom CPU frequency (only valid when unlocked)",
304 T::CLOCK_FREQ, 1000000, 1000000000)
305 , freq(T::CLOCK_FREQ)
306 , NMIStatus(0)
307 , nmiEdge(false)
308 , exitLoop(false)
309 , tracingEnabled(traceSetting.getBoolean())
310 , isCMOS(motherboard.hasToshibaEngine()) // Toshiba MSX-ENGINEs embed a CMOS Z80
311{
312 static_assert(!std::is_polymorphic_v<CPUCore<T>>,
313 "keep CPUCore non-virtual to keep PC at offset 0");
314 doSetFreq();
315 doReset(time);
316}
317
318template<typename T> void CPUCore<T>::warp(EmuTime::param time)
319{
320 assert(T::getTimeFast() <= time);
321 T::setTime(time);
322}
323
324template<typename T> EmuTime::param CPUCore<T>::getCurrentTime() const
325{
326 return T::getTime();
327}
328
329template<typename T> void CPUCore<T>::doReset(EmuTime::param time)
330{
331 // AF and SP are 0xFFFF
332 // PC, R, IFF1, IFF2, HALT and IM are 0x0
333 // all others are random
334 setAF(0xFFFF);
335 setBC(0xFFFF);
336 setDE(0xFFFF);
337 setHL(0xFFFF);
338 setIX(0xFFFF);
339 setIY(0xFFFF);
340 setPC(0x0000);
341 setSP(0xFFFF);
342 setAF2(0xFFFF);
343 setBC2(0xFFFF);
344 setDE2(0xFFFF);
345 setHL2(0xFFFF);
346 setIFF1(false);
347 setIFF2(false);
348 setHALT(false);
349 setExtHALT(false);
350 setIM(0);
351 setI(0x00);
352 setR(0x00);
353 T::setMemPtr(0xFFFF);
354 clearPrevious();
355
356 // We expect this assert to be valid
357 // assert(T::getTimeFast() <= time); // time shouldn't go backwards
358 // But it's disabled for the following reason:
359 // 'motion' (IRC nickname) managed to create a replay file that
360 // contains a reset command that falls in the middle of a Z80
361 // instruction. Replayed commands go via the Scheduler, and are
362 // (typically) executed right after a complete CPU instruction. So
363 // the CPU is (slightly) ahead in time of the about to be executed
364 // reset command.
365 // Normally this situation should never occur: console commands,
366 // hotkeys, commands over clicomm, ... are all handled via the global
367 // event mechanism. Such global events are scheduled between CPU
368 // instructions, so also in a replay they should fall between CPU
369 // instructions.
370 // However if for some reason the timing of the emulation changed
371 // (improved emulation accuracy or a bug so that emulation isn't
372 // deterministic or the replay file was edited, ...), then the above
373 // reasoning no longer holds and the assert can trigger.
374 // We need to be robust against loading older replays (when emulation
375 // timing has changed). So in that respect disabling the assert is
376 // good. Though in the example above (motion's replay) it's not clear
377 // whether the assert is really triggered by mixing an old replay
378 // with a newer openMSX version. In any case so far we haven't been
379 // able to reproduce this assert by recording and replaying using a
380 // single openMSX version.
381 T::setTime(time);
382
383 assert(NMIStatus == 0); // other devices must reset their NMI source
384 assert(IRQStatus == 0); // other devices must reset their IRQ source
385}
386
387// I believe the following two methods are thread safe even without any
388// locking. The worst that can happen is that we occasionally needlessly
389// exit the CPU loop, but that's harmless
390// TODO thread issues are always tricky, can someone confirm this really
391// is thread safe
392template<typename T> void CPUCore<T>::exitCPULoopAsync()
393{
394 // can get called from non-main threads
395 exitLoop = true;
396}
397template<typename T> void CPUCore<T>::exitCPULoopSync()
398{
399 assert(Thread::isMainThread());
400 exitLoop = true;
401 T::disableLimit();
402}
403template<typename T> inline bool CPUCore<T>::needExitCPULoop()
404{
405 // always executed in main thread
406 if (exitLoop) [[unlikely]] {
407 // Note: The test-and-set is _not_ atomic! But that's fine.
408 // An atomic implementation is trivial (see below), but
409 // this version (at least on x86) avoids the more expensive
410 // instructions on the likely path.
411 exitLoop = false;
412 return true;
413 }
414 return false;
415
416 // Alternative implementation:
417 // atomically set to false and return the old value
418 //return exitLoop.exchange(false);
419}
420
421template<typename T> void CPUCore<T>::setSlowInstructions()
422{
423 slowInstructions = 2;
424 T::disableLimit();
425}
426
427template<typename T> void CPUCore<T>::raiseIRQ()
428{
429 assert(IRQStatus >= 0);
430 if (IRQStatus == 0) {
431 setSlowInstructions();
432 }
433 IRQStatus = IRQStatus + 1;
434}
435
436template<typename T> void CPUCore<T>::lowerIRQ()
437{
438 IRQStatus = IRQStatus - 1;
439 assert(IRQStatus >= 0);
440}
441
442template<typename T> void CPUCore<T>::raiseNMI()
443{
444 assert(NMIStatus >= 0);
445 if (NMIStatus == 0) {
446 nmiEdge = true;
447 setSlowInstructions();
448 }
449 NMIStatus++;
450}
451
452template<typename T> void CPUCore<T>::lowerNMI()
453{
454 NMIStatus--;
455 assert(NMIStatus >= 0);
456}
457
458template<typename T> bool CPUCore<T>::isM1Cycle(unsigned address) const
459{
460 // This method should only be called from within a MSXDevice::readMem()
461 // method. It can be used to check whether the current read action has
462 // the M1 pin active. The 'address' parameter that is give to readMem()
463 // should be passed (unchanged) to this method.
464 //
465 // This simple implementation works because the rest of the CPUCore
466 // code is careful to only update the PC register on M1 cycles. In
467 // practice that means that the PC is (only) updated at the very end of
468 // every instruction, even if is a multi-byte instruction. Or for
469 // prefix-instructions the PC is also updated after the prefix is
470 // fetched (because such instructions activate M1 twice).
471 return address == getPC();
472}
473
474template<typename T> void CPUCore<T>::wait(EmuTime::param time)
475{
476 assert(time >= getCurrentTime());
477 scheduler.schedule(time);
478 T::advanceTime(time);
479}
480
481template<typename T> EmuTime CPUCore<T>::waitCycles(EmuTime::param time, unsigned cycles)
482{
483 T::add(cycles);
484 EmuTime time2 = T::calcTime(time, cycles);
485 // note: time2 is not necessarily equal to T::getTime() because of the
486 // way how WRITE_PORT() is implemented.
487 scheduler.schedule(time2);
488 return time2;
489}
490
491template<typename T> void CPUCore<T>::setNextSyncPoint(EmuTime::param time)
492{
493 T::setLimit(time);
494}
495
496
497static constexpr char toHex(byte x)
498{
499 return (x < 10) ? (x + '0') : (x - 10 + 'A');
500}
501static constexpr void toHex(byte x, char* buf)
502{
503 buf[0] = toHex(x / 16);
504 buf[1] = toHex(x & 15);
505}
506
507template<typename T> void CPUCore<T>::disasmCommand(
508 Interpreter& interp, std::span<const TclObject> tokens, TclObject& result) const
509{
510 word address = (tokens.size() < 3) ? getPC() : tokens[2].getInt(interp);
511 byte outBuf[4];
512 std::string dasmOutput;
513 unsigned len = dasm(*interface, address, outBuf, dasmOutput,
514 T::getTimeFast());
515 result.addListElement(dasmOutput);
516 char tmp[3]; tmp[2] = 0;
517 for (auto i : xrange(len)) {
518 toHex(outBuf[i], tmp);
519 result.addListElement(tmp);
520 }
521}
522
523template<typename T> void CPUCore<T>::update(const Setting& setting) noexcept
524{
525 if (&setting == &freqLocked) {
526 doSetFreq();
527 } else if (&setting == &freqValue) {
528 doSetFreq();
529 } else if (&setting == &traceSetting) {
530 tracingEnabled = traceSetting.getBoolean();
531 }
532}
533
534template<typename T> void CPUCore<T>::setFreq(unsigned freq_)
535{
536 freq = freq_;
537 doSetFreq();
538}
539
540template<typename T> void CPUCore<T>::doSetFreq()
541{
542 if (freqLocked.getBoolean()) {
543 // locked, use value set via setFreq()
544 T::setFreq(freq);
545 } else {
546 // unlocked, use value set by user
547 T::setFreq(freqValue.getInt());
548 }
549}
550
551
552template<typename T> inline byte CPUCore<T>::READ_PORT(unsigned port, unsigned cc)
553{
554 EmuTime time = T::getTimeFast(cc);
555 scheduler.schedule(time);
556 byte result = interface->readIO(port, time);
557 // note: no forced page-break after IO
558 return result;
559}
560
561template<typename T> inline void CPUCore<T>::WRITE_PORT(unsigned port, byte value, unsigned cc)
562{
563 EmuTime time = T::getTimeFast(cc);
564 scheduler.schedule(time);
565 interface->writeIO(port, value, time);
566 // note: no forced page-break after IO
567}
568
569template<typename T> template<bool PRE_PB, bool POST_PB>
570NEVER_INLINE byte CPUCore<T>::RDMEMslow(unsigned address, unsigned cc)
571{
572 interface->tick(CacheLineCounters::NonCachedRead);
573 // not cached
574 unsigned high = address >> CacheLine::BITS;
575 if (readCacheLine[high] == nullptr) {
576 // try to cache now (not a valid entry, and not yet tried)
577 unsigned addrBase = address & CacheLine::HIGH;
578 if (const byte* line = interface->getReadCacheLine(addrBase)) {
579 // cached ok
580 T::template PRE_MEM<PRE_PB, POST_PB>(address);
581 T::template POST_MEM< POST_PB>(address);
582 readCacheLine[high] = line - addrBase;
583 return readCacheLine[high][address];
584 }
585 }
586 // uncacheable
587 readCacheLine[high] = reinterpret_cast<const byte*>(1);
588 T::template PRE_MEM<PRE_PB, POST_PB>(address);
589 EmuTime time = T::getTimeFast(cc);
590 scheduler.schedule(time);
591 byte result = interface->readMem(address, time);
592 T::template POST_MEM<POST_PB>(address);
593 return result;
594}
595template<typename T> template<bool PRE_PB, bool POST_PB>
596ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl2(unsigned address, unsigned cc)
597{
598 const byte* line = readCacheLine[address >> CacheLine::BITS];
599 if (uintptr_t(line) > 1) [[likely]] {
600 // cached, fast path
601 T::template PRE_MEM<PRE_PB, POST_PB>(address);
602 T::template POST_MEM< POST_PB>(address);
603 return line[address];
604 } else {
605 return RDMEMslow<PRE_PB, POST_PB>(address, cc); // not inlined
606 }
607}
608template<typename T> template<bool PRE_PB, bool POST_PB>
609ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl(unsigned address, unsigned cc)
610{
611 constexpr bool PRE = T::template Normalize<PRE_PB >::value;
612 constexpr bool POST = T::template Normalize<POST_PB>::value;
613 return RDMEM_impl2<PRE, POST>(address, cc);
614}
615template<typename T> template<unsigned PC_OFFSET> ALWAYS_INLINE byte CPUCore<T>::RDMEM_OPCODE(unsigned cc)
616{
617 // Real Z80 would update the PC register now. In this implementation
618 // we've chosen to instead update PC only once at the end of the
619 // instruction. (Of course we made sure this difference is not
620 // noticeable by the program).
621 //
622 // See the comments in isM1Cycle() for the motivation for this
623 // deviation. Apart from that functional aspect it also turns out to be
624 // faster to only update PC once per instruction instead of after each
625 // fetch.
626 unsigned address = (getPC() + PC_OFFSET) & 0xFFFF;
627 return RDMEM_impl<false, false>(address, cc);
628}
629template<typename T> ALWAYS_INLINE byte CPUCore<T>::RDMEM(unsigned address, unsigned cc)
630{
631 return RDMEM_impl<true, true>(address, cc);
632}
633
634template<typename T> template<bool PRE_PB, bool POST_PB>
635NEVER_INLINE unsigned CPUCore<T>::RD_WORD_slow(unsigned address, unsigned cc)
636{
637 unsigned res = RDMEM_impl<PRE_PB, false>(address, cc);
638 res += RDMEM_impl<false, POST_PB>((address + 1) & 0xFFFF, cc + T::CC_RDMEM) << 8;
639 return res;
640}
641template<typename T> template<bool PRE_PB, bool POST_PB>
642ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl2(unsigned address, unsigned cc)
643{
644 const byte* line = readCacheLine[address >> CacheLine::BITS];
645 if (((address & CacheLine::LOW) != CacheLine::LOW) && (uintptr_t(line) > 1)) [[likely]] {
646 // fast path: cached and two bytes in same cache line
647 T::template PRE_WORD<PRE_PB, POST_PB>(address);
648 T::template POST_WORD< POST_PB>(address);
649 return Endian::read_UA_L16(&line[address]);
650 } else {
651 // slow path, not inline
652 return RD_WORD_slow<PRE_PB, POST_PB>(address, cc);
653 }
654}
655template<typename T> template<bool PRE_PB, bool POST_PB>
656ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl(unsigned address, unsigned cc)
657{
658 constexpr bool PRE = T::template Normalize<PRE_PB >::value;
659 constexpr bool POST = T::template Normalize<POST_PB>::value;
660 return RD_WORD_impl2<PRE, POST>(address, cc);
661}
662template<typename T> template<unsigned PC_OFFSET> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_PC(unsigned cc)
663{
664 unsigned addr = (getPC() + PC_OFFSET) & 0xFFFF;
665 return RD_WORD_impl<false, false>(addr, cc);
666}
667template<typename T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD(
668 unsigned address, unsigned cc)
669{
670 return RD_WORD_impl<true, true>(address, cc);
671}
672
673template<typename T> template<bool PRE_PB, bool POST_PB>
674NEVER_INLINE void CPUCore<T>::WRMEMslow(unsigned address, byte value, unsigned cc)
675{
676 interface->tick(CacheLineCounters::NonCachedWrite);
677 // not cached
678 unsigned high = address >> CacheLine::BITS;
679 if (writeCacheLine[high] == nullptr) {
680 // try to cache now
681 unsigned addrBase = address & CacheLine::HIGH;
682 if (byte* line = interface->getWriteCacheLine(addrBase)) {
683 // cached ok
684 T::template PRE_MEM<PRE_PB, POST_PB>(address);
685 T::template POST_MEM< POST_PB>(address);
686 writeCacheLine[high] = line - addrBase;
687 writeCacheLine[high][address] = value;
688 return;
689 }
690 }
691 // uncacheable
692 writeCacheLine[high] = reinterpret_cast<byte*>(1);
693 T::template PRE_MEM<PRE_PB, POST_PB>(address);
694 EmuTime time = T::getTimeFast(cc);
695 scheduler.schedule(time);
696 interface->writeMem(address, value, time);
697 T::template POST_MEM<POST_PB>(address);
698}
699template<typename T> template<bool PRE_PB, bool POST_PB>
701 unsigned address, byte value, unsigned cc)
702{
703 byte* line = writeCacheLine[address >> CacheLine::BITS];
704 if (uintptr_t(line) > 1) [[likely]] {
705 // cached, fast path
706 T::template PRE_MEM<PRE_PB, POST_PB>(address);
707 T::template POST_MEM< POST_PB>(address);
708 line[address] = value;
709 } else {
710 WRMEMslow<PRE_PB, POST_PB>(address, value, cc); // not inlined
711 }
712}
713template<typename T> template<bool PRE_PB, bool POST_PB>
715 unsigned address, byte value, unsigned cc)
716{
717 constexpr bool PRE = T::template Normalize<PRE_PB >::value;
718 constexpr bool POST = T::template Normalize<POST_PB>::value;
719 WRMEM_impl2<PRE, POST>(address, value, cc);
720}
721template<typename T> ALWAYS_INLINE void CPUCore<T>::WRMEM(
722 unsigned address, byte value, unsigned cc)
723{
724 WRMEM_impl<true, true>(address, value, cc);
725}
726
727template<typename T> NEVER_INLINE void CPUCore<T>::WR_WORD_slow(
728 unsigned address, unsigned value, unsigned cc)
729{
730 WRMEM_impl<true, false>( address, value & 255, cc);
731 WRMEM_impl<false, true>((address + 1) & 0xFFFF, value >> 8, cc + T::CC_WRMEM);
732}
733template<typename T> ALWAYS_INLINE void CPUCore<T>::WR_WORD(
734 unsigned address, unsigned value, unsigned cc)
735{
736 byte* line = writeCacheLine[address >> CacheLine::BITS];
737 if (((address & CacheLine::LOW) != CacheLine::LOW) && (uintptr_t(line) > 1)) [[likely]] {
738 // fast path: cached and two bytes in same cache line
739 T::template PRE_WORD<true, true>(address);
740 T::template POST_WORD< true>(address);
741 Endian::write_UA_L16(&line[address], value);
742 } else {
743 // slow path, not inline
744 WR_WORD_slow(address, value, cc);
745 }
746}
747
748// same as WR_WORD, but writes high byte first
749template<typename T> template<bool PRE_PB, bool POST_PB>
751 unsigned address, unsigned value, unsigned cc)
752{
753 WRMEM_impl<PRE_PB, false>((address + 1) & 0xFFFF, value >> 8, cc);
754 WRMEM_impl<false, POST_PB>( address, value & 255, cc + T::CC_WRMEM);
755}
756template<typename T> template<bool PRE_PB, bool POST_PB>
758 unsigned address, unsigned value, unsigned cc)
759{
760 byte* line = writeCacheLine[address >> CacheLine::BITS];
761 if (((address & CacheLine::LOW) != CacheLine::LOW) && (uintptr_t(line) > 1)) [[likely]] {
762 // fast path: cached and two bytes in same cache line
763 T::template PRE_WORD<PRE_PB, POST_PB>(address);
764 T::template POST_WORD< POST_PB>(address);
765 Endian::write_UA_L16(&line[address], value);
766 } else {
767 // slow path, not inline
768 WR_WORD_rev_slow<PRE_PB, POST_PB>(address, value, cc);
769 }
770}
771template<typename T> template<bool PRE_PB, bool POST_PB>
773 unsigned address, unsigned value, unsigned cc)
774{
775 constexpr bool PRE = T::template Normalize<PRE_PB >::value;
776 constexpr bool POST = T::template Normalize<POST_PB>::value;
777 WR_WORD_rev2<PRE, POST>(address, value, cc);
778}
779
780
781// NMI interrupt
782template<typename T> inline void CPUCore<T>::nmi()
783{
784 incR(1);
785 setHALT(false);
786 setIFF1(false);
787 PUSH<T::EE_NMI_1>(getPC());
788 setPC(0x0066);
789 T::add(T::CC_NMI);
790}
791
792// IM0 interrupt
793template<typename T> inline void CPUCore<T>::irq0()
794{
795 // TODO current implementation only works for 1-byte instructions
796 // ok for MSX
797 assert(interface->readIRQVector() == 0xFF);
798 incR(1);
799 setHALT(false);
800 setIFF1(false);
801 setIFF2(false);
802 PUSH<T::EE_IRQ0_1>(getPC());
803 setPC(0x0038);
804 T::setMemPtr(getPC());
805 T::add(T::CC_IRQ0);
806}
807
808// IM1 interrupt
809template<typename T> inline void CPUCore<T>::irq1()
810{
811 incR(1);
812 setHALT(false);
813 setIFF1(false);
814 setIFF2(false);
815 PUSH<T::EE_IRQ1_1>(getPC());
816 setPC(0x0038);
817 T::setMemPtr(getPC());
818 T::add(T::CC_IRQ1);
819}
820
821// IM2 interrupt
822template<typename T> inline void CPUCore<T>::irq2()
823{
824 incR(1);
825 setHALT(false);
826 setIFF1(false);
827 setIFF2(false);
828 PUSH<T::EE_IRQ2_1>(getPC());
829 unsigned x = interface->readIRQVector() | (getI() << 8);
830 setPC(RD_WORD(x, T::CC_IRQ2_2));
831 T::setMemPtr(getPC());
832 T::add(T::CC_IRQ2);
833}
834
835template<typename T>
836void CPUCore<T>::executeInstructions()
837{
838 checkNoCurrentFlags();
839#ifdef USE_COMPUTED_GOTO
840 // Addresses of all main-opcode routines,
841 // Note that 40/49/53/5B/64/6D/7F is replaced by 00 (ld r,r == nop)
842 static void* opcodeTable[256] = {
843 &&op00, &&op01, &&op02, &&op03, &&op04, &&op05, &&op06, &&op07,
844 &&op08, &&op09, &&op0A, &&op0B, &&op0C, &&op0D, &&op0E, &&op0F,
845 &&op10, &&op11, &&op12, &&op13, &&op14, &&op15, &&op16, &&op17,
846 &&op18, &&op19, &&op1A, &&op1B, &&op1C, &&op1D, &&op1E, &&op1F,
847 &&op20, &&op21, &&op22, &&op23, &&op24, &&op25, &&op26, &&op27,
848 &&op28, &&op29, &&op2A, &&op2B, &&op2C, &&op2D, &&op2E, &&op2F,
849 &&op30, &&op31, &&op32, &&op33, &&op34, &&op35, &&op36, &&op37,
850 &&op38, &&op39, &&op3A, &&op3B, &&op3C, &&op3D, &&op3E, &&op3F,
851 &&op00, &&op41, &&op42, &&op43, &&op44, &&op45, &&op46, &&op47,
852 &&op48, &&op00, &&op4A, &&op4B, &&op4C, &&op4D, &&op4E, &&op4F,
853 &&op50, &&op51, &&op00, &&op53, &&op54, &&op55, &&op56, &&op57,
854 &&op58, &&op59, &&op5A, &&op00, &&op5C, &&op5D, &&op5E, &&op5F,
855 &&op60, &&op61, &&op62, &&op63, &&op00, &&op65, &&op66, &&op67,
856 &&op68, &&op69, &&op6A, &&op6B, &&op6C, &&op00, &&op6E, &&op6F,
857 &&op70, &&op71, &&op72, &&op73, &&op74, &&op75, &&op76, &&op77,
858 &&op78, &&op79, &&op7A, &&op7B, &&op7C, &&op7D, &&op7E, &&op00,
859 &&op80, &&op81, &&op82, &&op83, &&op84, &&op85, &&op86, &&op87,
860 &&op88, &&op89, &&op8A, &&op8B, &&op8C, &&op8D, &&op8E, &&op8F,
861 &&op90, &&op91, &&op92, &&op93, &&op94, &&op95, &&op96, &&op97,
862 &&op98, &&op99, &&op9A, &&op9B, &&op9C, &&op9D, &&op9E, &&op9F,
863 &&opA0, &&opA1, &&opA2, &&opA3, &&opA4, &&opA5, &&opA6, &&opA7,
864 &&opA8, &&opA9, &&opAA, &&opAB, &&opAC, &&opAD, &&opAE, &&opAF,
865 &&opB0, &&opB1, &&opB2, &&opB3, &&opB4, &&opB5, &&opB6, &&opB7,
866 &&opB8, &&opB9, &&opBA, &&opBB, &&opBC, &&opBD, &&opBE, &&opBF,
867 &&opC0, &&opC1, &&opC2, &&opC3, &&opC4, &&opC5, &&opC6, &&opC7,
868 &&opC8, &&opC9, &&opCA, &&opCB, &&opCC, &&opCD, &&opCE, &&opCF,
869 &&opD0, &&opD1, &&opD2, &&opD3, &&opD4, &&opD5, &&opD6, &&opD7,
870 &&opD8, &&opD9, &&opDA, &&opDB, &&opDC, &&opDD, &&opDE, &&opDF,
871 &&opE0, &&opE1, &&opE2, &&opE3, &&opE4, &&opE5, &&opE6, &&opE7,
872 &&opE8, &&opE9, &&opEA, &&opEB, &&opEC, &&opED, &&opEE, &&opEF,
873 &&opF0, &&opF1, &&opF2, &&opF3, &&opF4, &&opF5, &&opF6, &&opF7,
874 &&opF8, &&opF9, &&opFA, &&opFB, &&opFC, &&opFD, &&opFE, &&opFF,
875 };
876
877// Check T::limitReached(). If it's OK to continue,
878// fetch and execute next instruction.
879#define NEXT \
880 setPC(getPC() + ii.length); \
881 T::add(ii.cycles); \
882 T::R800Refresh(*this); \
883 if (!T::limitReached()) [[likely]] { \
884 incR(1); \
885 unsigned address = getPC(); \
886 const byte* line = readCacheLine[address >> CacheLine::BITS]; \
887 if (uintptr_t(line) > 1) [[likely]] { \
888 T::template PRE_MEM<false, false>(address); \
889 T::template POST_MEM< false>(address); \
890 byte op = line[address]; \
891 goto *(opcodeTable[op]); \
892 } else { \
893 goto fetchSlow; \
894 } \
895 } \
896 return;
897
898// After some instructions we must always exit the CPU loop (ei, halt, retn)
899#define NEXT_STOP \
900 setPC(getPC() + ii.length); \
901 T::add(ii.cycles); \
902 T::R800Refresh(*this); \
903 assert(T::limitReached()); \
904 return;
905
906#define NEXT_EI \
907 setPC(getPC() + ii.length); \
908 T::add(ii.cycles); \
909 /* !! NO T::R800Refresh(*this); !! */ \
910 assert(T::limitReached()); \
911 return;
912
913// Define a label (instead of case in a switch statement)
914#define CASE(X) op##X:
915
916#else // USE_COMPUTED_GOTO
917
918#define NEXT \
919 setPC(getPC() + ii.length); \
920 T::add(ii.cycles); \
921 T::R800Refresh(*this); \
922 if (!T::limitReached()) [[likely]] { \
923 goto start; \
924 } \
925 return;
926
927#define NEXT_STOP \
928 setPC(getPC() + ii.length); \
929 T::add(ii.cycles); \
930 T::R800Refresh(*this); \
931 assert(T::limitReached()); \
932 return;
933
934#define NEXT_EI \
935 setPC(getPC() + ii.length); \
936 T::add(ii.cycles); \
937 /* !! NO T::R800Refresh(*this); !! */ \
938 assert(T::limitReached()); \
939 return;
940
941#define CASE(X) case 0x##X:
942
943#endif // USE_COMPUTED_GOTO
944
945#ifndef USE_COMPUTED_GOTO
946start:
947#endif
948 unsigned ixy; // for dd_cb/fd_cb
949 byte opcodeMain = RDMEM_OPCODE<0>(T::CC_MAIN);
950 incR(1);
951#ifdef USE_COMPUTED_GOTO
952 goto *(opcodeTable[opcodeMain]);
953
954fetchSlow: {
955 unsigned address = getPC();
956 byte opcodeSlow = RDMEMslow<false, false>(address, T::CC_MAIN);
957 goto *(opcodeTable[opcodeSlow]);
958}
959#endif
960
961#ifndef USE_COMPUTED_GOTO
962switchopcode:
963 switch (opcodeMain) {
964CASE(40) // ld b,b
965CASE(49) // ld c,c
966CASE(52) // ld d,d
967CASE(5B) // ld e,e
968CASE(64) // ld h,h
969CASE(6D) // ld l,l
970CASE(7F) // ld a,a
971#endif
972CASE(00) { II ii = nop(); NEXT; }
973CASE(07) { II ii = rlca(); NEXT; }
974CASE(0F) { II ii = rrca(); NEXT; }
975CASE(17) { II ii = rla(); NEXT; }
976CASE(1F) { II ii = rra(); NEXT; }
977CASE(08) { II ii = ex_af_af(); NEXT; }
978CASE(27) { II ii = daa(); NEXT; }
979CASE(2F) { II ii = cpl(); NEXT; }
980CASE(37) { II ii = scf(); NEXT; }
981CASE(3F) { II ii = ccf(); NEXT; }
982CASE(20) { II ii = jr(CondNZ()); NEXT; }
983CASE(28) { II ii = jr(CondZ ()); NEXT; }
984CASE(30) { II ii = jr(CondNC()); NEXT; }
985CASE(38) { II ii = jr(CondC ()); NEXT; }
986CASE(18) { II ii = jr(CondTrue()); NEXT; }
987CASE(10) { II ii = djnz(); NEXT; }
988CASE(32) { II ii = ld_xbyte_a(); NEXT; }
989CASE(3A) { II ii = ld_a_xbyte(); NEXT; }
990CASE(22) { II ii = ld_xword_SS<HL,0>(); NEXT; }
991CASE(2A) { II ii = ld_SS_xword<HL,0>(); NEXT; }
992CASE(02) { II ii = ld_SS_a<BC>(); NEXT; }
993CASE(12) { II ii = ld_SS_a<DE>(); NEXT; }
994CASE(1A) { II ii = ld_a_SS<DE>(); NEXT; }
995CASE(0A) { II ii = ld_a_SS<BC>(); NEXT; }
996CASE(03) { II ii = inc_SS<BC,0>(); NEXT; }
997CASE(13) { II ii = inc_SS<DE,0>(); NEXT; }
998CASE(23) { II ii = inc_SS<HL,0>(); NEXT; }
999CASE(33) { II ii = inc_SS<SP,0>(); NEXT; }
1000CASE(0B) { II ii = dec_SS<BC,0>(); NEXT; }
1001CASE(1B) { II ii = dec_SS<DE,0>(); NEXT; }
1002CASE(2B) { II ii = dec_SS<HL,0>(); NEXT; }
1003CASE(3B) { II ii = dec_SS<SP,0>(); NEXT; }
1004CASE(09) { II ii = add_SS_TT<HL,BC,0>(); NEXT; }
1005CASE(19) { II ii = add_SS_TT<HL,DE,0>(); NEXT; }
1006CASE(29) { II ii = add_SS_SS<HL ,0>(); NEXT; }
1007CASE(39) { II ii = add_SS_TT<HL,SP,0>(); NEXT; }
1008CASE(01) { II ii = ld_SS_word<BC,0>(); NEXT; }
1009CASE(11) { II ii = ld_SS_word<DE,0>(); NEXT; }
1010CASE(21) { II ii = ld_SS_word<HL,0>(); NEXT; }
1011CASE(31) { II ii = ld_SS_word<SP,0>(); NEXT; }
1012CASE(04) { II ii = inc_R<B,0>(); NEXT; }
1013CASE(0C) { II ii = inc_R<C,0>(); NEXT; }
1014CASE(14) { II ii = inc_R<D,0>(); NEXT; }
1015CASE(1C) { II ii = inc_R<E,0>(); NEXT; }
1016CASE(24) { II ii = inc_R<H,0>(); NEXT; }
1017CASE(2C) { II ii = inc_R<L,0>(); NEXT; }
1018CASE(3C) { II ii = inc_R<A,0>(); NEXT; }
1019CASE(34) { II ii = inc_xhl(); NEXT; }
1020CASE(05) { II ii = dec_R<B,0>(); NEXT; }
1021CASE(0D) { II ii = dec_R<C,0>(); NEXT; }
1022CASE(15) { II ii = dec_R<D,0>(); NEXT; }
1023CASE(1D) { II ii = dec_R<E,0>(); NEXT; }
1024CASE(25) { II ii = dec_R<H,0>(); NEXT; }
1025CASE(2D) { II ii = dec_R<L,0>(); NEXT; }
1026CASE(3D) { II ii = dec_R<A,0>(); NEXT; }
1027CASE(35) { II ii = dec_xhl(); NEXT; }
1028CASE(06) { II ii = ld_R_byte<B,0>(); NEXT; }
1029CASE(0E) { II ii = ld_R_byte<C,0>(); NEXT; }
1030CASE(16) { II ii = ld_R_byte<D,0>(); NEXT; }
1031CASE(1E) { II ii = ld_R_byte<E,0>(); NEXT; }
1032CASE(26) { II ii = ld_R_byte<H,0>(); NEXT; }
1033CASE(2E) { II ii = ld_R_byte<L,0>(); NEXT; }
1034CASE(3E) { II ii = ld_R_byte<A,0>(); NEXT; }
1035CASE(36) { II ii = ld_xhl_byte(); NEXT; }
1036
1037CASE(41) { II ii = ld_R_R<B,C,0>(); NEXT; }
1038CASE(42) { II ii = ld_R_R<B,D,0>(); NEXT; }
1039CASE(43) { II ii = ld_R_R<B,E,0>(); NEXT; }
1040CASE(44) { II ii = ld_R_R<B,H,0>(); NEXT; }
1041CASE(45) { II ii = ld_R_R<B,L,0>(); NEXT; }
1042CASE(47) { II ii = ld_R_R<B,A,0>(); NEXT; }
1043CASE(48) { II ii = ld_R_R<C,B,0>(); NEXT; }
1044CASE(4A) { II ii = ld_R_R<C,D,0>(); NEXT; }
1045CASE(4B) { II ii = ld_R_R<C,E,0>(); NEXT; }
1046CASE(4C) { II ii = ld_R_R<C,H,0>(); NEXT; }
1047CASE(4D) { II ii = ld_R_R<C,L,0>(); NEXT; }
1048CASE(4F) { II ii = ld_R_R<C,A,0>(); NEXT; }
1049CASE(50) { II ii = ld_R_R<D,B,0>(); NEXT; }
1050CASE(51) { II ii = ld_R_R<D,C,0>(); NEXT; }
1051CASE(53) { II ii = ld_R_R<D,E,0>(); NEXT; }
1052CASE(54) { II ii = ld_R_R<D,H,0>(); NEXT; }
1053CASE(55) { II ii = ld_R_R<D,L,0>(); NEXT; }
1054CASE(57) { II ii = ld_R_R<D,A,0>(); NEXT; }
1055CASE(58) { II ii = ld_R_R<E,B,0>(); NEXT; }
1056CASE(59) { II ii = ld_R_R<E,C,0>(); NEXT; }
1057CASE(5A) { II ii = ld_R_R<E,D,0>(); NEXT; }
1058CASE(5C) { II ii = ld_R_R<E,H,0>(); NEXT; }
1059CASE(5D) { II ii = ld_R_R<E,L,0>(); NEXT; }
1060CASE(5F) { II ii = ld_R_R<E,A,0>(); NEXT; }
1061CASE(60) { II ii = ld_R_R<H,B,0>(); NEXT; }
1062CASE(61) { II ii = ld_R_R<H,C,0>(); NEXT; }
1063CASE(62) { II ii = ld_R_R<H,D,0>(); NEXT; }
1064CASE(63) { II ii = ld_R_R<H,E,0>(); NEXT; }
1065CASE(65) { II ii = ld_R_R<H,L,0>(); NEXT; }
1066CASE(67) { II ii = ld_R_R<H,A,0>(); NEXT; }
1067CASE(68) { II ii = ld_R_R<L,B,0>(); NEXT; }
1068CASE(69) { II ii = ld_R_R<L,C,0>(); NEXT; }
1069CASE(6A) { II ii = ld_R_R<L,D,0>(); NEXT; }
1070CASE(6B) { II ii = ld_R_R<L,E,0>(); NEXT; }
1071CASE(6C) { II ii = ld_R_R<L,H,0>(); NEXT; }
1072CASE(6F) { II ii = ld_R_R<L,A,0>(); NEXT; }
1073CASE(78) { II ii = ld_R_R<A,B,0>(); NEXT; }
1074CASE(79) { II ii = ld_R_R<A,C,0>(); NEXT; }
1075CASE(7A) { II ii = ld_R_R<A,D,0>(); NEXT; }
1076CASE(7B) { II ii = ld_R_R<A,E,0>(); NEXT; }
1077CASE(7C) { II ii = ld_R_R<A,H,0>(); NEXT; }
1078CASE(7D) { II ii = ld_R_R<A,L,0>(); NEXT; }
1079CASE(70) { II ii = ld_xhl_R<B>(); NEXT; }
1080CASE(71) { II ii = ld_xhl_R<C>(); NEXT; }
1081CASE(72) { II ii = ld_xhl_R<D>(); NEXT; }
1082CASE(73) { II ii = ld_xhl_R<E>(); NEXT; }
1083CASE(74) { II ii = ld_xhl_R<H>(); NEXT; }
1084CASE(75) { II ii = ld_xhl_R<L>(); NEXT; }
1085CASE(77) { II ii = ld_xhl_R<A>(); NEXT; }
1086CASE(46) { II ii = ld_R_xhl<B>(); NEXT; }
1087CASE(4E) { II ii = ld_R_xhl<C>(); NEXT; }
1088CASE(56) { II ii = ld_R_xhl<D>(); NEXT; }
1089CASE(5E) { II ii = ld_R_xhl<E>(); NEXT; }
1090CASE(66) { II ii = ld_R_xhl<H>(); NEXT; }
1091CASE(6E) { II ii = ld_R_xhl<L>(); NEXT; }
1092CASE(7E) { II ii = ld_R_xhl<A>(); NEXT; }
1093CASE(76) { II ii = halt(); NEXT_STOP; }
1094
1095CASE(80) { II ii = add_a_R<B,0>(); NEXT; }
1096CASE(81) { II ii = add_a_R<C,0>(); NEXT; }
1097CASE(82) { II ii = add_a_R<D,0>(); NEXT; }
1098CASE(83) { II ii = add_a_R<E,0>(); NEXT; }
1099CASE(84) { II ii = add_a_R<H,0>(); NEXT; }
1100CASE(85) { II ii = add_a_R<L,0>(); NEXT; }
1101CASE(86) { II ii = add_a_xhl(); NEXT; }
1102CASE(87) { II ii = add_a_a(); NEXT; }
1103CASE(88) { II ii = adc_a_R<B,0>(); NEXT; }
1104CASE(89) { II ii = adc_a_R<C,0>(); NEXT; }
1105CASE(8A) { II ii = adc_a_R<D,0>(); NEXT; }
1106CASE(8B) { II ii = adc_a_R<E,0>(); NEXT; }
1107CASE(8C) { II ii = adc_a_R<H,0>(); NEXT; }
1108CASE(8D) { II ii = adc_a_R<L,0>(); NEXT; }
1109CASE(8E) { II ii = adc_a_xhl(); NEXT; }
1110CASE(8F) { II ii = adc_a_a(); NEXT; }
1111CASE(90) { II ii = sub_R<B,0>(); NEXT; }
1112CASE(91) { II ii = sub_R<C,0>(); NEXT; }
1113CASE(92) { II ii = sub_R<D,0>(); NEXT; }
1114CASE(93) { II ii = sub_R<E,0>(); NEXT; }
1115CASE(94) { II ii = sub_R<H,0>(); NEXT; }
1116CASE(95) { II ii = sub_R<L,0>(); NEXT; }
1117CASE(96) { II ii = sub_xhl(); NEXT; }
1118CASE(97) { II ii = sub_a(); NEXT; }
1119CASE(98) { II ii = sbc_a_R<B,0>(); NEXT; }
1120CASE(99) { II ii = sbc_a_R<C,0>(); NEXT; }
1121CASE(9A) { II ii = sbc_a_R<D,0>(); NEXT; }
1122CASE(9B) { II ii = sbc_a_R<E,0>(); NEXT; }
1123CASE(9C) { II ii = sbc_a_R<H,0>(); NEXT; }
1124CASE(9D) { II ii = sbc_a_R<L,0>(); NEXT; }
1125CASE(9E) { II ii = sbc_a_xhl(); NEXT; }
1126CASE(9F) { II ii = sbc_a_a(); NEXT; }
1127CASE(A0) { II ii = and_R<B,0>(); NEXT; }
1128CASE(A1) { II ii = and_R<C,0>(); NEXT; }
1129CASE(A2) { II ii = and_R<D,0>(); NEXT; }
1130CASE(A3) { II ii = and_R<E,0>(); NEXT; }
1131CASE(A4) { II ii = and_R<H,0>(); NEXT; }
1132CASE(A5) { II ii = and_R<L,0>(); NEXT; }
1133CASE(A6) { II ii = and_xhl(); NEXT; }
1134CASE(A7) { II ii = and_a(); NEXT; }
1135CASE(A8) { II ii = xor_R<B,0>(); NEXT; }
1136CASE(A9) { II ii = xor_R<C,0>(); NEXT; }
1137CASE(AA) { II ii = xor_R<D,0>(); NEXT; }
1138CASE(AB) { II ii = xor_R<E,0>(); NEXT; }
1139CASE(AC) { II ii = xor_R<H,0>(); NEXT; }
1140CASE(AD) { II ii = xor_R<L,0>(); NEXT; }
1141CASE(AE) { II ii = xor_xhl(); NEXT; }
1142CASE(AF) { II ii = xor_a(); NEXT; }
1143CASE(B0) { II ii = or_R<B,0>(); NEXT; }
1144CASE(B1) { II ii = or_R<C,0>(); NEXT; }
1145CASE(B2) { II ii = or_R<D,0>(); NEXT; }
1146CASE(B3) { II ii = or_R<E,0>(); NEXT; }
1147CASE(B4) { II ii = or_R<H,0>(); NEXT; }
1148CASE(B5) { II ii = or_R<L,0>(); NEXT; }
1149CASE(B6) { II ii = or_xhl(); NEXT; }
1150CASE(B7) { II ii = or_a(); NEXT; }
1151CASE(B8) { II ii = cp_R<B,0>(); NEXT; }
1152CASE(B9) { II ii = cp_R<C,0>(); NEXT; }
1153CASE(BA) { II ii = cp_R<D,0>(); NEXT; }
1154CASE(BB) { II ii = cp_R<E,0>(); NEXT; }
1155CASE(BC) { II ii = cp_R<H,0>(); NEXT; }
1156CASE(BD) { II ii = cp_R<L,0>(); NEXT; }
1157CASE(BE) { II ii = cp_xhl(); NEXT; }
1158CASE(BF) { II ii = cp_a(); NEXT; }
1159
1160CASE(D3) { II ii = out_byte_a(); NEXT; }
1161CASE(DB) { II ii = in_a_byte(); NEXT; }
1162CASE(D9) { II ii = exx(); NEXT; }
1163CASE(E3) { II ii = ex_xsp_SS<HL,0>(); NEXT; }
1164CASE(EB) { II ii = ex_de_hl(); NEXT; }
1165CASE(E9) { II ii = jp_SS<HL,0>(); NEXT; }
1166CASE(F9) { II ii = ld_sp_SS<HL,0>(); NEXT; }
1167CASE(F3) { II ii = di(); NEXT; }
1168CASE(FB) { II ii = ei(); NEXT_EI; }
1169CASE(C6) { II ii = add_a_byte(); NEXT; }
1170CASE(CE) { II ii = adc_a_byte(); NEXT; }
1171CASE(D6) { II ii = sub_byte(); NEXT; }
1172CASE(DE) { II ii = sbc_a_byte(); NEXT; }
1173CASE(E6) { II ii = and_byte(); NEXT; }
1174CASE(EE) { II ii = xor_byte(); NEXT; }
1175CASE(F6) { II ii = or_byte(); NEXT; }
1176CASE(FE) { II ii = cp_byte(); NEXT; }
1177CASE(C0) { II ii = ret(CondNZ()); NEXT; }
1178CASE(C8) { II ii = ret(CondZ ()); NEXT; }
1179CASE(D0) { II ii = ret(CondNC()); NEXT; }
1180CASE(D8) { II ii = ret(CondC ()); NEXT; }
1181CASE(E0) { II ii = ret(CondPO()); NEXT; }
1182CASE(E8) { II ii = ret(CondPE()); NEXT; }
1183CASE(F0) { II ii = ret(CondP ()); NEXT; }
1184CASE(F8) { II ii = ret(CondM ()); NEXT; }
1185CASE(C9) { II ii = ret(); NEXT; }
1186CASE(C2) { II ii = jp(CondNZ()); NEXT; }
1187CASE(CA) { II ii = jp(CondZ ()); NEXT; }
1188CASE(D2) { II ii = jp(CondNC()); NEXT; }
1189CASE(DA) { II ii = jp(CondC ()); NEXT; }
1190CASE(E2) { II ii = jp(CondPO()); NEXT; }
1191CASE(EA) { II ii = jp(CondPE()); NEXT; }
1192CASE(F2) { II ii = jp(CondP ()); NEXT; }
1193CASE(FA) { II ii = jp(CondM ()); NEXT; }
1194CASE(C3) { II ii = jp(CondTrue()); NEXT; }
1195CASE(C4) { II ii = call(CondNZ()); NEXT; }
1196CASE(CC) { II ii = call(CondZ ()); NEXT; }
1197CASE(D4) { II ii = call(CondNC()); NEXT; }
1198CASE(DC) { II ii = call(CondC ()); NEXT; }
1199CASE(E4) { II ii = call(CondPO()); NEXT; }
1200CASE(EC) { II ii = call(CondPE()); NEXT; }
1201CASE(F4) { II ii = call(CondP ()); NEXT; }
1202CASE(FC) { II ii = call(CondM ()); NEXT; }
1203CASE(CD) { II ii = call(CondTrue()); NEXT; }
1204CASE(C1) { II ii = pop_SS <BC,0>(); NEXT; }
1205CASE(D1) { II ii = pop_SS <DE,0>(); NEXT; }
1206CASE(E1) { II ii = pop_SS <HL,0>(); NEXT; }
1207CASE(F1) { II ii = pop_SS <AF,0>(); NEXT; }
1208CASE(C5) { II ii = push_SS<BC,0>(); NEXT; }
1209CASE(D5) { II ii = push_SS<DE,0>(); NEXT; }
1210CASE(E5) { II ii = push_SS<HL,0>(); NEXT; }
1211CASE(F5) { II ii = push_SS<AF,0>(); NEXT; }
1212CASE(C7) { II ii = rst<0x00>(); NEXT; }
1213CASE(CF) { II ii = rst<0x08>(); NEXT; }
1214CASE(D7) { II ii = rst<0x10>(); NEXT; }
1215CASE(DF) { II ii = rst<0x18>(); NEXT; }
1216CASE(E7) { II ii = rst<0x20>(); NEXT; }
1217CASE(EF) { II ii = rst<0x28>(); NEXT; }
1218CASE(F7) { II ii = rst<0x30>(); NEXT; }
1219CASE(FF) { II ii = rst<0x38>(); NEXT; }
1220CASE(CB) {
1221 setPC(getPC() + 1); // M1 cycle at this point
1222 byte cb_opcode = RDMEM_OPCODE<0>(T::CC_PREFIX);
1223 incR(1);
1224 switch (cb_opcode) {
1225 case 0x00: { II ii = rlc_R<B>(); NEXT; }
1226 case 0x01: { II ii = rlc_R<C>(); NEXT; }
1227 case 0x02: { II ii = rlc_R<D>(); NEXT; }
1228 case 0x03: { II ii = rlc_R<E>(); NEXT; }
1229 case 0x04: { II ii = rlc_R<H>(); NEXT; }
1230 case 0x05: { II ii = rlc_R<L>(); NEXT; }
1231 case 0x07: { II ii = rlc_R<A>(); NEXT; }
1232 case 0x06: { II ii = rlc_xhl(); NEXT; }
1233 case 0x08: { II ii = rrc_R<B>(); NEXT; }
1234 case 0x09: { II ii = rrc_R<C>(); NEXT; }
1235 case 0x0a: { II ii = rrc_R<D>(); NEXT; }
1236 case 0x0b: { II ii = rrc_R<E>(); NEXT; }
1237 case 0x0c: { II ii = rrc_R<H>(); NEXT; }
1238 case 0x0d: { II ii = rrc_R<L>(); NEXT; }
1239 case 0x0f: { II ii = rrc_R<A>(); NEXT; }
1240 case 0x0e: { II ii = rrc_xhl(); NEXT; }
1241 case 0x10: { II ii = rl_R<B>(); NEXT; }
1242 case 0x11: { II ii = rl_R<C>(); NEXT; }
1243 case 0x12: { II ii = rl_R<D>(); NEXT; }
1244 case 0x13: { II ii = rl_R<E>(); NEXT; }
1245 case 0x14: { II ii = rl_R<H>(); NEXT; }
1246 case 0x15: { II ii = rl_R<L>(); NEXT; }
1247 case 0x17: { II ii = rl_R<A>(); NEXT; }
1248 case 0x16: { II ii = rl_xhl(); NEXT; }
1249 case 0x18: { II ii = rr_R<B>(); NEXT; }
1250 case 0x19: { II ii = rr_R<C>(); NEXT; }
1251 case 0x1a: { II ii = rr_R<D>(); NEXT; }
1252 case 0x1b: { II ii = rr_R<E>(); NEXT; }
1253 case 0x1c: { II ii = rr_R<H>(); NEXT; }
1254 case 0x1d: { II ii = rr_R<L>(); NEXT; }
1255 case 0x1f: { II ii = rr_R<A>(); NEXT; }
1256 case 0x1e: { II ii = rr_xhl(); NEXT; }
1257 case 0x20: { II ii = sla_R<B>(); NEXT; }
1258 case 0x21: { II ii = sla_R<C>(); NEXT; }
1259 case 0x22: { II ii = sla_R<D>(); NEXT; }
1260 case 0x23: { II ii = sla_R<E>(); NEXT; }
1261 case 0x24: { II ii = sla_R<H>(); NEXT; }
1262 case 0x25: { II ii = sla_R<L>(); NEXT; }
1263 case 0x27: { II ii = sla_R<A>(); NEXT; }
1264 case 0x26: { II ii = sla_xhl(); NEXT; }
1265 case 0x28: { II ii = sra_R<B>(); NEXT; }
1266 case 0x29: { II ii = sra_R<C>(); NEXT; }
1267 case 0x2a: { II ii = sra_R<D>(); NEXT; }
1268 case 0x2b: { II ii = sra_R<E>(); NEXT; }
1269 case 0x2c: { II ii = sra_R<H>(); NEXT; }
1270 case 0x2d: { II ii = sra_R<L>(); NEXT; }
1271 case 0x2f: { II ii = sra_R<A>(); NEXT; }
1272 case 0x2e: { II ii = sra_xhl(); NEXT; }
1273 case 0x30: { II ii = T::IS_R800 ? sla_R<B>() : sll_R<B>(); NEXT; }
1274 case 0x31: { II ii = T::IS_R800 ? sla_R<C>() : sll_R<C>(); NEXT; }
1275 case 0x32: { II ii = T::IS_R800 ? sla_R<D>() : sll_R<D>(); NEXT; }
1276 case 0x33: { II ii = T::IS_R800 ? sla_R<E>() : sll_R<E>(); NEXT; }
1277 case 0x34: { II ii = T::IS_R800 ? sla_R<H>() : sll_R<H>(); NEXT; }
1278 case 0x35: { II ii = T::IS_R800 ? sla_R<L>() : sll_R<L>(); NEXT; }
1279 case 0x37: { II ii = T::IS_R800 ? sla_R<A>() : sll_R<A>(); NEXT; }
1280 case 0x36: { II ii = T::IS_R800 ? sla_xhl() : sll_xhl(); NEXT; }
1281 case 0x38: { II ii = srl_R<B>(); NEXT; }
1282 case 0x39: { II ii = srl_R<C>(); NEXT; }
1283 case 0x3a: { II ii = srl_R<D>(); NEXT; }
1284 case 0x3b: { II ii = srl_R<E>(); NEXT; }
1285 case 0x3c: { II ii = srl_R<H>(); NEXT; }
1286 case 0x3d: { II ii = srl_R<L>(); NEXT; }
1287 case 0x3f: { II ii = srl_R<A>(); NEXT; }
1288 case 0x3e: { II ii = srl_xhl(); NEXT; }
1289
1290 case 0x40: { II ii = bit_N_R<0,B>(); NEXT; }
1291 case 0x41: { II ii = bit_N_R<0,C>(); NEXT; }
1292 case 0x42: { II ii = bit_N_R<0,D>(); NEXT; }
1293 case 0x43: { II ii = bit_N_R<0,E>(); NEXT; }
1294 case 0x44: { II ii = bit_N_R<0,H>(); NEXT; }
1295 case 0x45: { II ii = bit_N_R<0,L>(); NEXT; }
1296 case 0x47: { II ii = bit_N_R<0,A>(); NEXT; }
1297 case 0x48: { II ii = bit_N_R<1,B>(); NEXT; }
1298 case 0x49: { II ii = bit_N_R<1,C>(); NEXT; }
1299 case 0x4a: { II ii = bit_N_R<1,D>(); NEXT; }
1300 case 0x4b: { II ii = bit_N_R<1,E>(); NEXT; }
1301 case 0x4c: { II ii = bit_N_R<1,H>(); NEXT; }
1302 case 0x4d: { II ii = bit_N_R<1,L>(); NEXT; }
1303 case 0x4f: { II ii = bit_N_R<1,A>(); NEXT; }
1304 case 0x50: { II ii = bit_N_R<2,B>(); NEXT; }
1305 case 0x51: { II ii = bit_N_R<2,C>(); NEXT; }
1306 case 0x52: { II ii = bit_N_R<2,D>(); NEXT; }
1307 case 0x53: { II ii = bit_N_R<2,E>(); NEXT; }
1308 case 0x54: { II ii = bit_N_R<2,H>(); NEXT; }
1309 case 0x55: { II ii = bit_N_R<2,L>(); NEXT; }
1310 case 0x57: { II ii = bit_N_R<2,A>(); NEXT; }
1311 case 0x58: { II ii = bit_N_R<3,B>(); NEXT; }
1312 case 0x59: { II ii = bit_N_R<3,C>(); NEXT; }
1313 case 0x5a: { II ii = bit_N_R<3,D>(); NEXT; }
1314 case 0x5b: { II ii = bit_N_R<3,E>(); NEXT; }
1315 case 0x5c: { II ii = bit_N_R<3,H>(); NEXT; }
1316 case 0x5d: { II ii = bit_N_R<3,L>(); NEXT; }
1317 case 0x5f: { II ii = bit_N_R<3,A>(); NEXT; }
1318 case 0x60: { II ii = bit_N_R<4,B>(); NEXT; }
1319 case 0x61: { II ii = bit_N_R<4,C>(); NEXT; }
1320 case 0x62: { II ii = bit_N_R<4,D>(); NEXT; }
1321 case 0x63: { II ii = bit_N_R<4,E>(); NEXT; }
1322 case 0x64: { II ii = bit_N_R<4,H>(); NEXT; }
1323 case 0x65: { II ii = bit_N_R<4,L>(); NEXT; }
1324 case 0x67: { II ii = bit_N_R<4,A>(); NEXT; }
1325 case 0x68: { II ii = bit_N_R<5,B>(); NEXT; }
1326 case 0x69: { II ii = bit_N_R<5,C>(); NEXT; }
1327 case 0x6a: { II ii = bit_N_R<5,D>(); NEXT; }
1328 case 0x6b: { II ii = bit_N_R<5,E>(); NEXT; }
1329 case 0x6c: { II ii = bit_N_R<5,H>(); NEXT; }
1330 case 0x6d: { II ii = bit_N_R<5,L>(); NEXT; }
1331 case 0x6f: { II ii = bit_N_R<5,A>(); NEXT; }
1332 case 0x70: { II ii = bit_N_R<6,B>(); NEXT; }
1333 case 0x71: { II ii = bit_N_R<6,C>(); NEXT; }
1334 case 0x72: { II ii = bit_N_R<6,D>(); NEXT; }
1335 case 0x73: { II ii = bit_N_R<6,E>(); NEXT; }
1336 case 0x74: { II ii = bit_N_R<6,H>(); NEXT; }
1337 case 0x75: { II ii = bit_N_R<6,L>(); NEXT; }
1338 case 0x77: { II ii = bit_N_R<6,A>(); NEXT; }
1339 case 0x78: { II ii = bit_N_R<7,B>(); NEXT; }
1340 case 0x79: { II ii = bit_N_R<7,C>(); NEXT; }
1341 case 0x7a: { II ii = bit_N_R<7,D>(); NEXT; }
1342 case 0x7b: { II ii = bit_N_R<7,E>(); NEXT; }
1343 case 0x7c: { II ii = bit_N_R<7,H>(); NEXT; }
1344 case 0x7d: { II ii = bit_N_R<7,L>(); NEXT; }
1345 case 0x7f: { II ii = bit_N_R<7,A>(); NEXT; }
1346 case 0x46: { II ii = bit_N_xhl<0>(); NEXT; }
1347 case 0x4e: { II ii = bit_N_xhl<1>(); NEXT; }
1348 case 0x56: { II ii = bit_N_xhl<2>(); NEXT; }
1349 case 0x5e: { II ii = bit_N_xhl<3>(); NEXT; }
1350 case 0x66: { II ii = bit_N_xhl<4>(); NEXT; }
1351 case 0x6e: { II ii = bit_N_xhl<5>(); NEXT; }
1352 case 0x76: { II ii = bit_N_xhl<6>(); NEXT; }
1353 case 0x7e: { II ii = bit_N_xhl<7>(); NEXT; }
1354
1355 case 0x80: { II ii = res_N_R<0,B>(); NEXT; }
1356 case 0x81: { II ii = res_N_R<0,C>(); NEXT; }
1357 case 0x82: { II ii = res_N_R<0,D>(); NEXT; }
1358 case 0x83: { II ii = res_N_R<0,E>(); NEXT; }
1359 case 0x84: { II ii = res_N_R<0,H>(); NEXT; }
1360 case 0x85: { II ii = res_N_R<0,L>(); NEXT; }
1361 case 0x87: { II ii = res_N_R<0,A>(); NEXT; }
1362 case 0x88: { II ii = res_N_R<1,B>(); NEXT; }
1363 case 0x89: { II ii = res_N_R<1,C>(); NEXT; }
1364 case 0x8a: { II ii = res_N_R<1,D>(); NEXT; }
1365 case 0x8b: { II ii = res_N_R<1,E>(); NEXT; }
1366 case 0x8c: { II ii = res_N_R<1,H>(); NEXT; }
1367 case 0x8d: { II ii = res_N_R<1,L>(); NEXT; }
1368 case 0x8f: { II ii = res_N_R<1,A>(); NEXT; }
1369 case 0x90: { II ii = res_N_R<2,B>(); NEXT; }
1370 case 0x91: { II ii = res_N_R<2,C>(); NEXT; }
1371 case 0x92: { II ii = res_N_R<2,D>(); NEXT; }
1372 case 0x93: { II ii = res_N_R<2,E>(); NEXT; }
1373 case 0x94: { II ii = res_N_R<2,H>(); NEXT; }
1374 case 0x95: { II ii = res_N_R<2,L>(); NEXT; }
1375 case 0x97: { II ii = res_N_R<2,A>(); NEXT; }
1376 case 0x98: { II ii = res_N_R<3,B>(); NEXT; }
1377 case 0x99: { II ii = res_N_R<3,C>(); NEXT; }
1378 case 0x9a: { II ii = res_N_R<3,D>(); NEXT; }
1379 case 0x9b: { II ii = res_N_R<3,E>(); NEXT; }
1380 case 0x9c: { II ii = res_N_R<3,H>(); NEXT; }
1381 case 0x9d: { II ii = res_N_R<3,L>(); NEXT; }
1382 case 0x9f: { II ii = res_N_R<3,A>(); NEXT; }
1383 case 0xa0: { II ii = res_N_R<4,B>(); NEXT; }
1384 case 0xa1: { II ii = res_N_R<4,C>(); NEXT; }
1385 case 0xa2: { II ii = res_N_R<4,D>(); NEXT; }
1386 case 0xa3: { II ii = res_N_R<4,E>(); NEXT; }
1387 case 0xa4: { II ii = res_N_R<4,H>(); NEXT; }
1388 case 0xa5: { II ii = res_N_R<4,L>(); NEXT; }
1389 case 0xa7: { II ii = res_N_R<4,A>(); NEXT; }
1390 case 0xa8: { II ii = res_N_R<5,B>(); NEXT; }
1391 case 0xa9: { II ii = res_N_R<5,C>(); NEXT; }
1392 case 0xaa: { II ii = res_N_R<5,D>(); NEXT; }
1393 case 0xab: { II ii = res_N_R<5,E>(); NEXT; }
1394 case 0xac: { II ii = res_N_R<5,H>(); NEXT; }
1395 case 0xad: { II ii = res_N_R<5,L>(); NEXT; }
1396 case 0xaf: { II ii = res_N_R<5,A>(); NEXT; }
1397 case 0xb0: { II ii = res_N_R<6,B>(); NEXT; }
1398 case 0xb1: { II ii = res_N_R<6,C>(); NEXT; }
1399 case 0xb2: { II ii = res_N_R<6,D>(); NEXT; }
1400 case 0xb3: { II ii = res_N_R<6,E>(); NEXT; }
1401 case 0xb4: { II ii = res_N_R<6,H>(); NEXT; }
1402 case 0xb5: { II ii = res_N_R<6,L>(); NEXT; }
1403 case 0xb7: { II ii = res_N_R<6,A>(); NEXT; }
1404 case 0xb8: { II ii = res_N_R<7,B>(); NEXT; }
1405 case 0xb9: { II ii = res_N_R<7,C>(); NEXT; }
1406 case 0xba: { II ii = res_N_R<7,D>(); NEXT; }
1407 case 0xbb: { II ii = res_N_R<7,E>(); NEXT; }
1408 case 0xbc: { II ii = res_N_R<7,H>(); NEXT; }
1409 case 0xbd: { II ii = res_N_R<7,L>(); NEXT; }
1410 case 0xbf: { II ii = res_N_R<7,A>(); NEXT; }
1411 case 0x86: { II ii = res_N_xhl<0>(); NEXT; }
1412 case 0x8e: { II ii = res_N_xhl<1>(); NEXT; }
1413 case 0x96: { II ii = res_N_xhl<2>(); NEXT; }
1414 case 0x9e: { II ii = res_N_xhl<3>(); NEXT; }
1415 case 0xa6: { II ii = res_N_xhl<4>(); NEXT; }
1416 case 0xae: { II ii = res_N_xhl<5>(); NEXT; }
1417 case 0xb6: { II ii = res_N_xhl<6>(); NEXT; }
1418 case 0xbe: { II ii = res_N_xhl<7>(); NEXT; }
1419
1420 case 0xc0: { II ii = set_N_R<0,B>(); NEXT; }
1421 case 0xc1: { II ii = set_N_R<0,C>(); NEXT; }
1422 case 0xc2: { II ii = set_N_R<0,D>(); NEXT; }
1423 case 0xc3: { II ii = set_N_R<0,E>(); NEXT; }
1424 case 0xc4: { II ii = set_N_R<0,H>(); NEXT; }
1425 case 0xc5: { II ii = set_N_R<0,L>(); NEXT; }
1426 case 0xc7: { II ii = set_N_R<0,A>(); NEXT; }
1427 case 0xc8: { II ii = set_N_R<1,B>(); NEXT; }
1428 case 0xc9: { II ii = set_N_R<1,C>(); NEXT; }
1429 case 0xca: { II ii = set_N_R<1,D>(); NEXT; }
1430 case 0xcb: { II ii = set_N_R<1,E>(); NEXT; }
1431 case 0xcc: { II ii = set_N_R<1,H>(); NEXT; }
1432 case 0xcd: { II ii = set_N_R<1,L>(); NEXT; }
1433 case 0xcf: { II ii = set_N_R<1,A>(); NEXT; }
1434 case 0xd0: { II ii = set_N_R<2,B>(); NEXT; }
1435 case 0xd1: { II ii = set_N_R<2,C>(); NEXT; }
1436 case 0xd2: { II ii = set_N_R<2,D>(); NEXT; }
1437 case 0xd3: { II ii = set_N_R<2,E>(); NEXT; }
1438 case 0xd4: { II ii = set_N_R<2,H>(); NEXT; }
1439 case 0xd5: { II ii = set_N_R<2,L>(); NEXT; }
1440 case 0xd7: { II ii = set_N_R<2,A>(); NEXT; }
1441 case 0xd8: { II ii = set_N_R<3,B>(); NEXT; }
1442 case 0xd9: { II ii = set_N_R<3,C>(); NEXT; }
1443 case 0xda: { II ii = set_N_R<3,D>(); NEXT; }
1444 case 0xdb: { II ii = set_N_R<3,E>(); NEXT; }
1445 case 0xdc: { II ii = set_N_R<3,H>(); NEXT; }
1446 case 0xdd: { II ii = set_N_R<3,L>(); NEXT; }
1447 case 0xdf: { II ii = set_N_R<3,A>(); NEXT; }
1448 case 0xe0: { II ii = set_N_R<4,B>(); NEXT; }
1449 case 0xe1: { II ii = set_N_R<4,C>(); NEXT; }
1450 case 0xe2: { II ii = set_N_R<4,D>(); NEXT; }
1451 case 0xe3: { II ii = set_N_R<4,E>(); NEXT; }
1452 case 0xe4: { II ii = set_N_R<4,H>(); NEXT; }
1453 case 0xe5: { II ii = set_N_R<4,L>(); NEXT; }
1454 case 0xe7: { II ii = set_N_R<4,A>(); NEXT; }
1455 case 0xe8: { II ii = set_N_R<5,B>(); NEXT; }
1456 case 0xe9: { II ii = set_N_R<5,C>(); NEXT; }
1457 case 0xea: { II ii = set_N_R<5,D>(); NEXT; }
1458 case 0xeb: { II ii = set_N_R<5,E>(); NEXT; }
1459 case 0xec: { II ii = set_N_R<5,H>(); NEXT; }
1460 case 0xed: { II ii = set_N_R<5,L>(); NEXT; }
1461 case 0xef: { II ii = set_N_R<5,A>(); NEXT; }
1462 case 0xf0: { II ii = set_N_R<6,B>(); NEXT; }
1463 case 0xf1: { II ii = set_N_R<6,C>(); NEXT; }
1464 case 0xf2: { II ii = set_N_R<6,D>(); NEXT; }
1465 case 0xf3: { II ii = set_N_R<6,E>(); NEXT; }
1466 case 0xf4: { II ii = set_N_R<6,H>(); NEXT; }
1467 case 0xf5: { II ii = set_N_R<6,L>(); NEXT; }
1468 case 0xf7: { II ii = set_N_R<6,A>(); NEXT; }
1469 case 0xf8: { II ii = set_N_R<7,B>(); NEXT; }
1470 case 0xf9: { II ii = set_N_R<7,C>(); NEXT; }
1471 case 0xfa: { II ii = set_N_R<7,D>(); NEXT; }
1472 case 0xfb: { II ii = set_N_R<7,E>(); NEXT; }
1473 case 0xfc: { II ii = set_N_R<7,H>(); NEXT; }
1474 case 0xfd: { II ii = set_N_R<7,L>(); NEXT; }
1475 case 0xff: { II ii = set_N_R<7,A>(); NEXT; }
1476 case 0xc6: { II ii = set_N_xhl<0>(); NEXT; }
1477 case 0xce: { II ii = set_N_xhl<1>(); NEXT; }
1478 case 0xd6: { II ii = set_N_xhl<2>(); NEXT; }
1479 case 0xde: { II ii = set_N_xhl<3>(); NEXT; }
1480 case 0xe6: { II ii = set_N_xhl<4>(); NEXT; }
1481 case 0xee: { II ii = set_N_xhl<5>(); NEXT; }
1482 case 0xf6: { II ii = set_N_xhl<6>(); NEXT; }
1483 case 0xfe: { II ii = set_N_xhl<7>(); NEXT; }
1484 default: UNREACHABLE; return;
1485 }
1486}
1487CASE(ED) {
1488 setPC(getPC() + 1); // M1 cycle at this point
1489 byte ed_opcode = RDMEM_OPCODE<0>(T::CC_PREFIX);
1490 incR(1);
1491 switch (ed_opcode) {
1492 case 0x00: case 0x01: case 0x02: case 0x03:
1493 case 0x04: case 0x05: case 0x06: case 0x07:
1494 case 0x08: case 0x09: case 0x0a: case 0x0b:
1495 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1496 case 0x10: case 0x11: case 0x12: case 0x13:
1497 case 0x14: case 0x15: case 0x16: case 0x17:
1498 case 0x18: case 0x19: case 0x1a: case 0x1b:
1499 case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1500 case 0x20: case 0x21: case 0x22: case 0x23:
1501 case 0x24: case 0x25: case 0x26: case 0x27:
1502 case 0x28: case 0x29: case 0x2a: case 0x2b:
1503 case 0x2c: case 0x2d: case 0x2e: case 0x2f:
1504 case 0x30: case 0x31: case 0x32: case 0x33:
1505 case 0x34: case 0x35: case 0x36: case 0x37:
1506 case 0x38: case 0x39: case 0x3a: case 0x3b:
1507 case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1508
1509 case 0x77: case 0x7f:
1510
1511 case 0x80: case 0x81: case 0x82: case 0x83:
1512 case 0x84: case 0x85: case 0x86: case 0x87:
1513 case 0x88: case 0x89: case 0x8a: case 0x8b:
1514 case 0x8c: case 0x8d: case 0x8e: case 0x8f:
1515 case 0x90: case 0x91: case 0x92: case 0x93:
1516 case 0x94: case 0x95: case 0x96: case 0x97:
1517 case 0x98: case 0x99: case 0x9a: case 0x9b:
1518 case 0x9c: case 0x9d: case 0x9e: case 0x9f:
1519 case 0xa4: case 0xa5: case 0xa6: case 0xa7:
1520 case 0xac: case 0xad: case 0xae: case 0xaf:
1521 case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1522 case 0xbc: case 0xbd: case 0xbe: case 0xbf:
1523
1524 case 0xc0: case 0xc2:
1525 case 0xc4: case 0xc5: case 0xc6: case 0xc7:
1526 case 0xc8: case 0xca: case 0xcb:
1527 case 0xcc: case 0xcd: case 0xce: case 0xcf:
1528 case 0xd0: case 0xd2: case 0xd3:
1529 case 0xd4: case 0xd5: case 0xd6: case 0xd7:
1530 case 0xd8: case 0xda: case 0xdb:
1531 case 0xdc: case 0xdd: case 0xde: case 0xdf:
1532 case 0xe0: case 0xe1: case 0xe2: case 0xe3:
1533 case 0xe4: case 0xe5: case 0xe6: case 0xe7:
1534 case 0xe8: case 0xe9: case 0xea: case 0xeb:
1535 case 0xec: case 0xed: case 0xee: case 0xef:
1536 case 0xf0: case 0xf1: case 0xf2:
1537 case 0xf4: case 0xf5: case 0xf6: case 0xf7:
1538 case 0xf8: case 0xf9: case 0xfa: case 0xfb:
1539 case 0xfc: case 0xfd: case 0xfe: case 0xff:
1540 { II ii = nop(); NEXT; }
1541
1542 case 0x40: { II ii = in_R_c<B>(); NEXT; }
1543 case 0x48: { II ii = in_R_c<C>(); NEXT; }
1544 case 0x50: { II ii = in_R_c<D>(); NEXT; }
1545 case 0x58: { II ii = in_R_c<E>(); NEXT; }
1546 case 0x60: { II ii = in_R_c<H>(); NEXT; }
1547 case 0x68: { II ii = in_R_c<L>(); NEXT; }
1548 case 0x70: { II ii = in_R_c<DUMMY>(); NEXT; }
1549 case 0x78: { II ii = in_R_c<A>(); NEXT; }
1550
1551 case 0x41: { II ii = out_c_R<B>(); NEXT; }
1552 case 0x49: { II ii = out_c_R<C>(); NEXT; }
1553 case 0x51: { II ii = out_c_R<D>(); NEXT; }
1554 case 0x59: { II ii = out_c_R<E>(); NEXT; }
1555 case 0x61: { II ii = out_c_R<H>(); NEXT; }
1556 case 0x69: { II ii = out_c_R<L>(); NEXT; }
1557 case 0x71: { II ii = out_c_0(); NEXT; }
1558 case 0x79: { II ii = out_c_R<A>(); NEXT; }
1559
1560 case 0x42: { II ii = sbc_hl_SS<BC>(); NEXT; }
1561 case 0x52: { II ii = sbc_hl_SS<DE>(); NEXT; }
1562 case 0x62: { II ii = sbc_hl_hl (); NEXT; }
1563 case 0x72: { II ii = sbc_hl_SS<SP>(); NEXT; }
1564
1565 case 0x4a: { II ii = adc_hl_SS<BC>(); NEXT; }
1566 case 0x5a: { II ii = adc_hl_SS<DE>(); NEXT; }
1567 case 0x6a: { II ii = adc_hl_hl (); NEXT; }
1568 case 0x7a: { II ii = adc_hl_SS<SP>(); NEXT; }
1569
1570 case 0x43: { II ii = ld_xword_SS_ED<BC>(); NEXT; }
1571 case 0x53: { II ii = ld_xword_SS_ED<DE>(); NEXT; }
1572 case 0x63: { II ii = ld_xword_SS_ED<HL>(); NEXT; }
1573 case 0x73: { II ii = ld_xword_SS_ED<SP>(); NEXT; }
1574
1575 case 0x4b: { II ii = ld_SS_xword_ED<BC>(); NEXT; }
1576 case 0x5b: { II ii = ld_SS_xword_ED<DE>(); NEXT; }
1577 case 0x6b: { II ii = ld_SS_xword_ED<HL>(); NEXT; }
1578 case 0x7b: { II ii = ld_SS_xword_ED<SP>(); NEXT; }
1579
1580 case 0x47: { II ii = ld_i_a(); NEXT; }
1581 case 0x4f: { II ii = ld_r_a(); NEXT; }
1582 case 0x57: { II ii = ld_a_IR<REG_I>(); if (T::IS_R800) { NEXT; } else { NEXT_STOP; }}
1583 case 0x5f: { II ii = ld_a_IR<REG_R>(); if (T::IS_R800) { NEXT; } else { NEXT_STOP; }}
1584
1585 case 0x67: { II ii = rrd(); NEXT; }
1586 case 0x6f: { II ii = rld(); NEXT; }
1587
1588 case 0x45: case 0x4d: case 0x55: case 0x5d:
1589 case 0x65: case 0x6d: case 0x75: case 0x7d:
1590 { II ii = retn(); NEXT_STOP; }
1591 case 0x46: case 0x4e: case 0x66: case 0x6e:
1592 { II ii = im_N<0>(); NEXT; }
1593 case 0x56: case 0x76:
1594 { II ii = im_N<1>(); NEXT; }
1595 case 0x5e: case 0x7e:
1596 { II ii = im_N<2>(); NEXT; }
1597 case 0x44: case 0x4c: case 0x54: case 0x5c:
1598 case 0x64: case 0x6c: case 0x74: case 0x7c:
1599 { II ii = neg(); NEXT; }
1600
1601 case 0xa0: { II ii = ldi(); NEXT; }
1602 case 0xa1: { II ii = cpi(); NEXT; }
1603 case 0xa2: { II ii = ini(); NEXT; }
1604 case 0xa3: { II ii = outi(); NEXT; }
1605 case 0xa8: { II ii = ldd(); NEXT; }
1606 case 0xa9: { II ii = cpd(); NEXT; }
1607 case 0xaa: { II ii = ind(); NEXT; }
1608 case 0xab: { II ii = outd(); NEXT; }
1609 case 0xb0: { II ii = ldir(); NEXT; }
1610 case 0xb1: { II ii = cpir(); NEXT; }
1611 case 0xb2: { II ii = inir(); NEXT; }
1612 case 0xb3: { II ii = otir(); NEXT; }
1613 case 0xb8: { II ii = lddr(); NEXT; }
1614 case 0xb9: { II ii = cpdr(); NEXT; }
1615 case 0xba: { II ii = indr(); NEXT; }
1616 case 0xbb: { II ii = otdr(); NEXT; }
1617
1618 case 0xc1: { II ii = T::IS_R800 ? mulub_a_R<B>() : nop(); NEXT; }
1619 case 0xc9: { II ii = T::IS_R800 ? mulub_a_R<C>() : nop(); NEXT; }
1620 case 0xd1: { II ii = T::IS_R800 ? mulub_a_R<D>() : nop(); NEXT; }
1621 case 0xd9: { II ii = T::IS_R800 ? mulub_a_R<E>() : nop(); NEXT; }
1622 case 0xc3: { II ii = T::IS_R800 ? muluw_hl_SS<BC>() : nop(); NEXT; }
1623 case 0xf3: { II ii = T::IS_R800 ? muluw_hl_SS<SP>() : nop(); NEXT; }
1624 default: UNREACHABLE; return;
1625 }
1626}
1627opDD_2:
1628CASE(DD) {
1629 setPC(getPC() + 1); // M1 cycle at this point
1630 byte opcodeDD = RDMEM_OPCODE<0>(T::CC_DD + T::CC_MAIN);
1631 incR(1);
1632 switch (opcodeDD) {
1633 case 0x00: // nop();
1634 case 0x01: // ld_bc_word();
1635 case 0x02: // ld_xbc_a();
1636 case 0x03: // inc_bc();
1637 case 0x04: // inc_b();
1638 case 0x05: // dec_b();
1639 case 0x06: // ld_b_byte();
1640 case 0x07: // rlca();
1641 case 0x08: // ex_af_af();
1642 case 0x0a: // ld_a_xbc();
1643 case 0x0b: // dec_bc();
1644 case 0x0c: // inc_c();
1645 case 0x0d: // dec_c();
1646 case 0x0e: // ld_c_byte();
1647 case 0x0f: // rrca();
1648 case 0x10: // djnz();
1649 case 0x11: // ld_de_word();
1650 case 0x12: // ld_xde_a();
1651 case 0x13: // inc_de();
1652 case 0x14: // inc_d();
1653 case 0x15: // dec_d();
1654 case 0x16: // ld_d_byte();
1655 case 0x17: // rla();
1656 case 0x18: // jr();
1657 case 0x1a: // ld_a_xde();
1658 case 0x1b: // dec_de();
1659 case 0x1c: // inc_e();
1660 case 0x1d: // dec_e();
1661 case 0x1e: // ld_e_byte();
1662 case 0x1f: // rra();
1663 case 0x20: // jr_nz();
1664 case 0x27: // daa();
1665 case 0x28: // jr_z();
1666 case 0x2f: // cpl();
1667 case 0x30: // jr_nc();
1668 case 0x31: // ld_sp_word();
1669 case 0x32: // ld_xbyte_a();
1670 case 0x33: // inc_sp();
1671 case 0x37: // scf();
1672 case 0x38: // jr_c();
1673 case 0x3a: // ld_a_xbyte();
1674 case 0x3b: // dec_sp();
1675 case 0x3c: // inc_a();
1676 case 0x3d: // dec_a();
1677 case 0x3e: // ld_a_byte();
1678 case 0x3f: // ccf();
1679
1680 case 0x40: // ld_b_b();
1681 case 0x41: // ld_b_c();
1682 case 0x42: // ld_b_d();
1683 case 0x43: // ld_b_e();
1684 case 0x47: // ld_b_a();
1685 case 0x48: // ld_c_b();
1686 case 0x49: // ld_c_c();
1687 case 0x4a: // ld_c_d();
1688 case 0x4b: // ld_c_e();
1689 case 0x4f: // ld_c_a();
1690 case 0x50: // ld_d_b();
1691 case 0x51: // ld_d_c();
1692 case 0x52: // ld_d_d();
1693 case 0x53: // ld_d_e();
1694 case 0x57: // ld_d_a();
1695 case 0x58: // ld_e_b();
1696 case 0x59: // ld_e_c();
1697 case 0x5a: // ld_e_d();
1698 case 0x5b: // ld_e_e();
1699 case 0x5f: // ld_e_a();
1700 case 0x64: // ld_ixh_ixh(); == nop
1701 case 0x6d: // ld_ixl_ixl(); == nop
1702 case 0x76: // halt();
1703 case 0x78: // ld_a_b();
1704 case 0x79: // ld_a_c();
1705 case 0x7a: // ld_a_d();
1706 case 0x7b: // ld_a_e();
1707 case 0x7f: // ld_a_a();
1708
1709 case 0x80: // add_a_b();
1710 case 0x81: // add_a_c();
1711 case 0x82: // add_a_d();
1712 case 0x83: // add_a_e();
1713 case 0x87: // add_a_a();
1714 case 0x88: // adc_a_b();
1715 case 0x89: // adc_a_c();
1716 case 0x8a: // adc_a_d();
1717 case 0x8b: // adc_a_e();
1718 case 0x8f: // adc_a_a();
1719 case 0x90: // sub_b();
1720 case 0x91: // sub_c();
1721 case 0x92: // sub_d();
1722 case 0x93: // sub_e();
1723 case 0x97: // sub_a();
1724 case 0x98: // sbc_a_b();
1725 case 0x99: // sbc_a_c();
1726 case 0x9a: // sbc_a_d();
1727 case 0x9b: // sbc_a_e();
1728 case 0x9f: // sbc_a_a();
1729 case 0xa0: // and_b();
1730 case 0xa1: // and_c();
1731 case 0xa2: // and_d();
1732 case 0xa3: // and_e();
1733 case 0xa7: // and_a();
1734 case 0xa8: // xor_b();
1735 case 0xa9: // xor_c();
1736 case 0xaa: // xor_d();
1737 case 0xab: // xor_e();
1738 case 0xaf: // xor_a();
1739 case 0xb0: // or_b();
1740 case 0xb1: // or_c();
1741 case 0xb2: // or_d();
1742 case 0xb3: // or_e();
1743 case 0xb7: // or_a();
1744 case 0xb8: // cp_b();
1745 case 0xb9: // cp_c();
1746 case 0xba: // cp_d();
1747 case 0xbb: // cp_e();
1748 case 0xbf: // cp_a();
1749
1750 case 0xc0: // ret_nz();
1751 case 0xc1: // pop_bc();
1752 case 0xc2: // jp_nz();
1753 case 0xc3: // jp();
1754 case 0xc4: // call_nz();
1755 case 0xc5: // push_bc();
1756 case 0xc6: // add_a_byte();
1757 case 0xc7: // rst_00();
1758 case 0xc8: // ret_z();
1759 case 0xc9: // ret();
1760 case 0xca: // jp_z();
1761 case 0xcc: // call_z();
1762 case 0xcd: // call();
1763 case 0xce: // adc_a_byte();
1764 case 0xcf: // rst_08();
1765 case 0xd0: // ret_nc();
1766 case 0xd1: // pop_de();
1767 case 0xd2: // jp_nc();
1768 case 0xd3: // out_byte_a();
1769 case 0xd4: // call_nc();
1770 case 0xd5: // push_de();
1771 case 0xd6: // sub_byte();
1772 case 0xd7: // rst_10();
1773 case 0xd8: // ret_c();
1774 case 0xd9: // exx();
1775 case 0xda: // jp_c();
1776 case 0xdb: // in_a_byte();
1777 case 0xdc: // call_c();
1778 case 0xde: // sbc_a_byte();
1779 case 0xdf: // rst_18();
1780 case 0xe0: // ret_po();
1781 case 0xe2: // jp_po();
1782 case 0xe4: // call_po();
1783 case 0xe6: // and_byte();
1784 case 0xe7: // rst_20();
1785 case 0xe8: // ret_pe();
1786 case 0xea: // jp_pe();
1787 case 0xeb: // ex_de_hl();
1788 case 0xec: // call_pe();
1789 case 0xed: // ed();
1790 case 0xee: // xor_byte();
1791 case 0xef: // rst_28();
1792 case 0xf0: // ret_p();
1793 case 0xf1: // pop_af();
1794 case 0xf2: // jp_p();
1795 case 0xf3: // di();
1796 case 0xf4: // call_p();
1797 case 0xf5: // push_af();
1798 case 0xf6: // or_byte();
1799 case 0xf7: // rst_30();
1800 case 0xf8: // ret_m();
1801 case 0xfa: // jp_m();
1802 case 0xfb: // ei();
1803 case 0xfc: // call_m();
1804 case 0xfe: // cp_byte();
1805 case 0xff: // rst_38();
1806 if /*constexpr*/ (T::IS_R800) {
1807 II ii = nop();
1808 ii.cycles += T::CC_DD;
1809 NEXT;
1810 } else {
1811 T::add(T::CC_DD);
1812 #ifdef USE_COMPUTED_GOTO
1813 goto *(opcodeTable[opcodeDD]);
1814 #else
1815 opcodeMain = opcodeDD;
1816 goto switchopcode;
1817 #endif
1818 }
1819
1820 case 0x09: { II ii = add_SS_TT<IX,BC,T::CC_DD>(); NEXT; }
1821 case 0x19: { II ii = add_SS_TT<IX,DE,T::CC_DD>(); NEXT; }
1822 case 0x29: { II ii = add_SS_SS<IX ,T::CC_DD>(); NEXT; }
1823 case 0x39: { II ii = add_SS_TT<IX,SP,T::CC_DD>(); NEXT; }
1824 case 0x21: { II ii = ld_SS_word<IX,T::CC_DD>(); NEXT; }
1825 case 0x22: { II ii = ld_xword_SS<IX,T::CC_DD>(); NEXT; }
1826 case 0x2a: { II ii = ld_SS_xword<IX,T::CC_DD>(); NEXT; }
1827 case 0x23: { II ii = inc_SS<IX,T::CC_DD>(); NEXT; }
1828 case 0x2b: { II ii = dec_SS<IX,T::CC_DD>(); NEXT; }
1829 case 0x24: { II ii = inc_R<IXH,T::CC_DD>(); NEXT; }
1830 case 0x2c: { II ii = inc_R<IXL,T::CC_DD>(); NEXT; }
1831 case 0x25: { II ii = dec_R<IXH,T::CC_DD>(); NEXT; }
1832 case 0x2d: { II ii = dec_R<IXL,T::CC_DD>(); NEXT; }
1833 case 0x26: { II ii = ld_R_byte<IXH,T::CC_DD>(); NEXT; }
1834 case 0x2e: { II ii = ld_R_byte<IXL,T::CC_DD>(); NEXT; }
1835 case 0x34: { II ii = inc_xix<IX>(); NEXT; }
1836 case 0x35: { II ii = dec_xix<IX>(); NEXT; }
1837 case 0x36: { II ii = ld_xix_byte<IX>(); NEXT; }
1838
1839 case 0x44: { II ii = ld_R_R<B,IXH,T::CC_DD>(); NEXT; }
1840 case 0x45: { II ii = ld_R_R<B,IXL,T::CC_DD>(); NEXT; }
1841 case 0x4c: { II ii = ld_R_R<C,IXH,T::CC_DD>(); NEXT; }
1842 case 0x4d: { II ii = ld_R_R<C,IXL,T::CC_DD>(); NEXT; }
1843 case 0x54: { II ii = ld_R_R<D,IXH,T::CC_DD>(); NEXT; }
1844 case 0x55: { II ii = ld_R_R<D,IXL,T::CC_DD>(); NEXT; }
1845 case 0x5c: { II ii = ld_R_R<E,IXH,T::CC_DD>(); NEXT; }
1846 case 0x5d: { II ii = ld_R_R<E,IXL,T::CC_DD>(); NEXT; }
1847 case 0x7c: { II ii = ld_R_R<A,IXH,T::CC_DD>(); NEXT; }
1848 case 0x7d: { II ii = ld_R_R<A,IXL,T::CC_DD>(); NEXT; }
1849 case 0x60: { II ii = ld_R_R<IXH,B,T::CC_DD>(); NEXT; }
1850 case 0x61: { II ii = ld_R_R<IXH,C,T::CC_DD>(); NEXT; }
1851 case 0x62: { II ii = ld_R_R<IXH,D,T::CC_DD>(); NEXT; }
1852 case 0x63: { II ii = ld_R_R<IXH,E,T::CC_DD>(); NEXT; }
1853 case 0x65: { II ii = ld_R_R<IXH,IXL,T::CC_DD>(); NEXT; }
1854 case 0x67: { II ii = ld_R_R<IXH,A,T::CC_DD>(); NEXT; }
1855 case 0x68: { II ii = ld_R_R<IXL,B,T::CC_DD>(); NEXT; }
1856 case 0x69: { II ii = ld_R_R<IXL,C,T::CC_DD>(); NEXT; }
1857 case 0x6a: { II ii = ld_R_R<IXL,D,T::CC_DD>(); NEXT; }
1858 case 0x6b: { II ii = ld_R_R<IXL,E,T::CC_DD>(); NEXT; }
1859 case 0x6c: { II ii = ld_R_R<IXL,IXH,T::CC_DD>(); NEXT; }
1860 case 0x6f: { II ii = ld_R_R<IXL,A,T::CC_DD>(); NEXT; }
1861 case 0x70: { II ii = ld_xix_R<IX,B>(); NEXT; }
1862 case 0x71: { II ii = ld_xix_R<IX,C>(); NEXT; }
1863 case 0x72: { II ii = ld_xix_R<IX,D>(); NEXT; }
1864 case 0x73: { II ii = ld_xix_R<IX,E>(); NEXT; }
1865 case 0x74: { II ii = ld_xix_R<IX,H>(); NEXT; }
1866 case 0x75: { II ii = ld_xix_R<IX,L>(); NEXT; }
1867 case 0x77: { II ii = ld_xix_R<IX,A>(); NEXT; }
1868 case 0x46: { II ii = ld_R_xix<B,IX>(); NEXT; }
1869 case 0x4e: { II ii = ld_R_xix<C,IX>(); NEXT; }
1870 case 0x56: { II ii = ld_R_xix<D,IX>(); NEXT; }
1871 case 0x5e: { II ii = ld_R_xix<E,IX>(); NEXT; }
1872 case 0x66: { II ii = ld_R_xix<H,IX>(); NEXT; }
1873 case 0x6e: { II ii = ld_R_xix<L,IX>(); NEXT; }
1874 case 0x7e: { II ii = ld_R_xix<A,IX>(); NEXT; }
1875
1876 case 0x84: { II ii = add_a_R<IXH,T::CC_DD>(); NEXT; }
1877 case 0x85: { II ii = add_a_R<IXL,T::CC_DD>(); NEXT; }
1878 case 0x86: { II ii = add_a_xix<IX>(); NEXT; }
1879 case 0x8c: { II ii = adc_a_R<IXH,T::CC_DD>(); NEXT; }
1880 case 0x8d: { II ii = adc_a_R<IXL,T::CC_DD>(); NEXT; }
1881 case 0x8e: { II ii = adc_a_xix<IX>(); NEXT; }
1882 case 0x94: { II ii = sub_R<IXH,T::CC_DD>(); NEXT; }
1883 case 0x95: { II ii = sub_R<IXL,T::CC_DD>(); NEXT; }
1884 case 0x96: { II ii = sub_xix<IX>(); NEXT; }
1885 case 0x9c: { II ii = sbc_a_R<IXH,T::CC_DD>(); NEXT; }
1886 case 0x9d: { II ii = sbc_a_R<IXL,T::CC_DD>(); NEXT; }
1887 case 0x9e: { II ii = sbc_a_xix<IX>(); NEXT; }
1888 case 0xa4: { II ii = and_R<IXH,T::CC_DD>(); NEXT; }
1889 case 0xa5: { II ii = and_R<IXL,T::CC_DD>(); NEXT; }
1890 case 0xa6: { II ii = and_xix<IX>(); NEXT; }
1891 case 0xac: { II ii = xor_R<IXH,T::CC_DD>(); NEXT; }
1892 case 0xad: { II ii = xor_R<IXL,T::CC_DD>(); NEXT; }
1893 case 0xae: { II ii = xor_xix<IX>(); NEXT; }
1894 case 0xb4: { II ii = or_R<IXH,T::CC_DD>(); NEXT; }
1895 case 0xb5: { II ii = or_R<IXL,T::CC_DD>(); NEXT; }
1896 case 0xb6: { II ii = or_xix<IX>(); NEXT; }
1897 case 0xbc: { II ii = cp_R<IXH,T::CC_DD>(); NEXT; }
1898 case 0xbd: { II ii = cp_R<IXL,T::CC_DD>(); NEXT; }
1899 case 0xbe: { II ii = cp_xix<IX>(); NEXT; }
1900
1901 case 0xe1: { II ii = pop_SS <IX,T::CC_DD>(); NEXT; }
1902 case 0xe5: { II ii = push_SS<IX,T::CC_DD>(); NEXT; }
1903 case 0xe3: { II ii = ex_xsp_SS<IX,T::CC_DD>(); NEXT; }
1904 case 0xe9: { II ii = jp_SS<IX,T::CC_DD>(); NEXT; }
1905 case 0xf9: { II ii = ld_sp_SS<IX,T::CC_DD>(); NEXT; }
1906 case 0xcb: ixy = getIX(); goto xx_cb;
1907 case 0xdd: T::add(T::CC_DD); goto opDD_2;
1908 case 0xfd: T::add(T::CC_DD); goto opFD_2;
1909 default: UNREACHABLE; return;
1910 }
1911}
1912opFD_2:
1913CASE(FD) {
1914 setPC(getPC() + 1); // M1 cycle at this point
1915 byte opcodeFD = RDMEM_OPCODE<0>(T::CC_DD + T::CC_MAIN);
1916 incR(1);
1917 switch (opcodeFD) {
1918 case 0x00: // nop();
1919 case 0x01: // ld_bc_word();
1920 case 0x02: // ld_xbc_a();
1921 case 0x03: // inc_bc();
1922 case 0x04: // inc_b();
1923 case 0x05: // dec_b();
1924 case 0x06: // ld_b_byte();
1925 case 0x07: // rlca();
1926 case 0x08: // ex_af_af();
1927 case 0x0a: // ld_a_xbc();
1928 case 0x0b: // dec_bc();
1929 case 0x0c: // inc_c();
1930 case 0x0d: // dec_c();
1931 case 0x0e: // ld_c_byte();
1932 case 0x0f: // rrca();
1933 case 0x10: // djnz();
1934 case 0x11: // ld_de_word();
1935 case 0x12: // ld_xde_a();
1936 case 0x13: // inc_de();
1937 case 0x14: // inc_d();
1938 case 0x15: // dec_d();
1939 case 0x16: // ld_d_byte();
1940 case 0x17: // rla();
1941 case 0x18: // jr();
1942 case 0x1a: // ld_a_xde();
1943 case 0x1b: // dec_de();
1944 case 0x1c: // inc_e();
1945 case 0x1d: // dec_e();
1946 case 0x1e: // ld_e_byte();
1947 case 0x1f: // rra();
1948 case 0x20: // jr_nz();
1949 case 0x27: // daa();
1950 case 0x28: // jr_z();
1951 case 0x2f: // cpl();
1952 case 0x30: // jr_nc();
1953 case 0x31: // ld_sp_word();
1954 case 0x32: // ld_xbyte_a();
1955 case 0x33: // inc_sp();
1956 case 0x37: // scf();
1957 case 0x38: // jr_c();
1958 case 0x3a: // ld_a_xbyte();
1959 case 0x3b: // dec_sp();
1960 case 0x3c: // inc_a();
1961 case 0x3d: // dec_a();
1962 case 0x3e: // ld_a_byte();
1963 case 0x3f: // ccf();
1964
1965 case 0x40: // ld_b_b();
1966 case 0x41: // ld_b_c();
1967 case 0x42: // ld_b_d();
1968 case 0x43: // ld_b_e();
1969 case 0x47: // ld_b_a();
1970 case 0x48: // ld_c_b();
1971 case 0x49: // ld_c_c();
1972 case 0x4a: // ld_c_d();
1973 case 0x4b: // ld_c_e();
1974 case 0x4f: // ld_c_a();
1975 case 0x50: // ld_d_b();
1976 case 0x51: // ld_d_c();
1977 case 0x52: // ld_d_d();
1978 case 0x53: // ld_d_e();
1979 case 0x57: // ld_d_a();
1980 case 0x58: // ld_e_b();
1981 case 0x59: // ld_e_c();
1982 case 0x5a: // ld_e_d();
1983 case 0x5b: // ld_e_e();
1984 case 0x5f: // ld_e_a();
1985 case 0x64: // ld_ixh_ixh(); == nop
1986 case 0x6d: // ld_ixl_ixl(); == nop
1987 case 0x76: // halt();
1988 case 0x78: // ld_a_b();
1989 case 0x79: // ld_a_c();
1990 case 0x7a: // ld_a_d();
1991 case 0x7b: // ld_a_e();
1992 case 0x7f: // ld_a_a();
1993
1994 case 0x80: // add_a_b();
1995 case 0x81: // add_a_c();
1996 case 0x82: // add_a_d();
1997 case 0x83: // add_a_e();
1998 case 0x87: // add_a_a();
1999 case 0x88: // adc_a_b();
2000 case 0x89: // adc_a_c();
2001 case 0x8a: // adc_a_d();
2002 case 0x8b: // adc_a_e();
2003 case 0x8f: // adc_a_a();
2004 case 0x90: // sub_b();
2005 case 0x91: // sub_c();
2006 case 0x92: // sub_d();
2007 case 0x93: // sub_e();
2008 case 0x97: // sub_a();
2009 case 0x98: // sbc_a_b();
2010 case 0x99: // sbc_a_c();
2011 case 0x9a: // sbc_a_d();
2012 case 0x9b: // sbc_a_e();
2013 case 0x9f: // sbc_a_a();
2014 case 0xa0: // and_b();
2015 case 0xa1: // and_c();
2016 case 0xa2: // and_d();
2017 case 0xa3: // and_e();
2018 case 0xa7: // and_a();
2019 case 0xa8: // xor_b();
2020 case 0xa9: // xor_c();
2021 case 0xaa: // xor_d();
2022 case 0xab: // xor_e();
2023 case 0xaf: // xor_a();
2024 case 0xb0: // or_b();
2025 case 0xb1: // or_c();
2026 case 0xb2: // or_d();
2027 case 0xb3: // or_e();
2028 case 0xb7: // or_a();
2029 case 0xb8: // cp_b();
2030 case 0xb9: // cp_c();
2031 case 0xba: // cp_d();
2032 case 0xbb: // cp_e();
2033 case 0xbf: // cp_a();
2034
2035 case 0xc0: // ret_nz();
2036 case 0xc1: // pop_bc();
2037 case 0xc2: // jp_nz();
2038 case 0xc3: // jp();
2039 case 0xc4: // call_nz();
2040 case 0xc5: // push_bc();
2041 case 0xc6: // add_a_byte();
2042 case 0xc7: // rst_00();
2043 case 0xc8: // ret_z();
2044 case 0xc9: // ret();
2045 case 0xca: // jp_z();
2046 case 0xcc: // call_z();
2047 case 0xcd: // call();
2048 case 0xce: // adc_a_byte();
2049 case 0xcf: // rst_08();
2050 case 0xd0: // ret_nc();
2051 case 0xd1: // pop_de();
2052 case 0xd2: // jp_nc();
2053 case 0xd3: // out_byte_a();
2054 case 0xd4: // call_nc();
2055 case 0xd5: // push_de();
2056 case 0xd6: // sub_byte();
2057 case 0xd7: // rst_10();
2058 case 0xd8: // ret_c();
2059 case 0xd9: // exx();
2060 case 0xda: // jp_c();
2061 case 0xdb: // in_a_byte();
2062 case 0xdc: // call_c();
2063 case 0xde: // sbc_a_byte();
2064 case 0xdf: // rst_18();
2065 case 0xe0: // ret_po();
2066 case 0xe2: // jp_po();
2067 case 0xe4: // call_po();
2068 case 0xe6: // and_byte();
2069 case 0xe7: // rst_20();
2070 case 0xe8: // ret_pe();
2071 case 0xea: // jp_pe();
2072 case 0xeb: // ex_de_hl();
2073 case 0xec: // call_pe();
2074 case 0xed: // ed();
2075 case 0xee: // xor_byte();
2076 case 0xef: // rst_28();
2077 case 0xf0: // ret_p();
2078 case 0xf1: // pop_af();
2079 case 0xf2: // jp_p();
2080 case 0xf3: // di();
2081 case 0xf4: // call_p();
2082 case 0xf5: // push_af();
2083 case 0xf6: // or_byte();
2084 case 0xf7: // rst_30();
2085 case 0xf8: // ret_m();
2086 case 0xfa: // jp_m();
2087 case 0xfb: // ei();
2088 case 0xfc: // call_m();
2089 case 0xfe: // cp_byte();
2090 case 0xff: // rst_38();
2091 if constexpr (T::IS_R800) {
2092 II ii = nop();
2093 ii.cycles += T::CC_DD;
2094 NEXT;
2095 } else {
2096 T::add(T::CC_DD);
2097 #ifdef USE_COMPUTED_GOTO
2098 goto *(opcodeTable[opcodeFD]);
2099 #else
2100 opcodeMain = opcodeFD;
2101 goto switchopcode;
2102 #endif
2103 }
2104
2105 case 0x09: { II ii = add_SS_TT<IY,BC,T::CC_DD>(); NEXT; }
2106 case 0x19: { II ii = add_SS_TT<IY,DE,T::CC_DD>(); NEXT; }
2107 case 0x29: { II ii = add_SS_SS<IY ,T::CC_DD>(); NEXT; }
2108 case 0x39: { II ii = add_SS_TT<IY,SP,T::CC_DD>(); NEXT; }
2109 case 0x21: { II ii = ld_SS_word<IY,T::CC_DD>(); NEXT; }
2110 case 0x22: { II ii = ld_xword_SS<IY,T::CC_DD>(); NEXT; }
2111 case 0x2a: { II ii = ld_SS_xword<IY,T::CC_DD>(); NEXT; }
2112 case 0x23: { II ii = inc_SS<IY,T::CC_DD>(); NEXT; }
2113 case 0x2b: { II ii = dec_SS<IY,T::CC_DD>(); NEXT; }
2114 case 0x24: { II ii = inc_R<IYH,T::CC_DD>(); NEXT; }
2115 case 0x2c: { II ii = inc_R<IYL,T::CC_DD>(); NEXT; }
2116 case 0x25: { II ii = dec_R<IYH,T::CC_DD>(); NEXT; }
2117 case 0x2d: { II ii = dec_R<IYL,T::CC_DD>(); NEXT; }
2118 case 0x26: { II ii = ld_R_byte<IYH,T::CC_DD>(); NEXT; }
2119 case 0x2e: { II ii = ld_R_byte<IYL,T::CC_DD>(); NEXT; }
2120 case 0x34: { II ii = inc_xix<IY>(); NEXT; }
2121 case 0x35: { II ii = dec_xix<IY>(); NEXT; }
2122 case 0x36: { II ii = ld_xix_byte<IY>(); NEXT; }
2123
2124 case 0x44: { II ii = ld_R_R<B,IYH,T::CC_DD>(); NEXT; }
2125 case 0x45: { II ii = ld_R_R<B,IYL,T::CC_DD>(); NEXT; }
2126 case 0x4c: { II ii = ld_R_R<C,IYH,T::CC_DD>(); NEXT; }
2127 case 0x4d: { II ii = ld_R_R<C,IYL,T::CC_DD>(); NEXT; }
2128 case 0x54: { II ii = ld_R_R<D,IYH,T::CC_DD>(); NEXT; }
2129 case 0x55: { II ii = ld_R_R<D,IYL,T::CC_DD>(); NEXT; }
2130 case 0x5c: { II ii = ld_R_R<E,IYH,T::CC_DD>(); NEXT; }
2131 case 0x5d: { II ii = ld_R_R<E,IYL,T::CC_DD>(); NEXT; }
2132 case 0x7c: { II ii = ld_R_R<A,IYH,T::CC_DD>(); NEXT; }
2133 case 0x7d: { II ii = ld_R_R<A,IYL,T::CC_DD>(); NEXT; }
2134 case 0x60: { II ii = ld_R_R<IYH,B,T::CC_DD>(); NEXT; }
2135 case 0x61: { II ii = ld_R_R<IYH,C,T::CC_DD>(); NEXT; }
2136 case 0x62: { II ii = ld_R_R<IYH,D,T::CC_DD>(); NEXT; }
2137 case 0x63: { II ii = ld_R_R<IYH,E,T::CC_DD>(); NEXT; }
2138 case 0x65: { II ii = ld_R_R<IYH,IYL,T::CC_DD>(); NEXT; }
2139 case 0x67: { II ii = ld_R_R<IYH,A,T::CC_DD>(); NEXT; }
2140 case 0x68: { II ii = ld_R_R<IYL,B,T::CC_DD>(); NEXT; }
2141 case 0x69: { II ii = ld_R_R<IYL,C,T::CC_DD>(); NEXT; }
2142 case 0x6a: { II ii = ld_R_R<IYL,D,T::CC_DD>(); NEXT; }
2143 case 0x6b: { II ii = ld_R_R<IYL,E,T::CC_DD>(); NEXT; }
2144 case 0x6c: { II ii = ld_R_R<IYL,IYH,T::CC_DD>(); NEXT; }
2145 case 0x6f: { II ii = ld_R_R<IYL,A,T::CC_DD>(); NEXT; }
2146 case 0x70: { II ii = ld_xix_R<IY,B>(); NEXT; }
2147 case 0x71: { II ii = ld_xix_R<IY,C>(); NEXT; }
2148 case 0x72: { II ii = ld_xix_R<IY,D>(); NEXT; }
2149 case 0x73: { II ii = ld_xix_R<IY,E>(); NEXT; }
2150 case 0x74: { II ii = ld_xix_R<IY,H>(); NEXT; }
2151 case 0x75: { II ii = ld_xix_R<IY,L>(); NEXT; }
2152 case 0x77: { II ii = ld_xix_R<IY,A>(); NEXT; }
2153 case 0x46: { II ii = ld_R_xix<B,IY>(); NEXT; }
2154 case 0x4e: { II ii = ld_R_xix<C,IY>(); NEXT; }
2155 case 0x56: { II ii = ld_R_xix<D,IY>(); NEXT; }
2156 case 0x5e: { II ii = ld_R_xix<E,IY>(); NEXT; }
2157 case 0x66: { II ii = ld_R_xix<H,IY>(); NEXT; }
2158 case 0x6e: { II ii = ld_R_xix<L,IY>(); NEXT; }
2159 case 0x7e: { II ii = ld_R_xix<A,IY>(); NEXT; }
2160
2161 case 0x84: { II ii = add_a_R<IYH,T::CC_DD>(); NEXT; }
2162 case 0x85: { II ii = add_a_R<IYL,T::CC_DD>(); NEXT; }
2163 case 0x86: { II ii = add_a_xix<IY>(); NEXT; }
2164 case 0x8c: { II ii = adc_a_R<IYH,T::CC_DD>(); NEXT; }
2165 case 0x8d: { II ii = adc_a_R<IYL,T::CC_DD>(); NEXT; }
2166 case 0x8e: { II ii = adc_a_xix<IY>(); NEXT; }
2167 case 0x94: { II ii = sub_R<IYH,T::CC_DD>(); NEXT; }
2168 case 0x95: { II ii = sub_R<IYL,T::CC_DD>(); NEXT; }
2169 case 0x96: { II ii = sub_xix<IY>(); NEXT; }
2170 case 0x9c: { II ii = sbc_a_R<IYH,T::CC_DD>(); NEXT; }
2171 case 0x9d: { II ii = sbc_a_R<IYL,T::CC_DD>(); NEXT; }
2172 case 0x9e: { II ii = sbc_a_xix<IY>(); NEXT; }
2173 case 0xa4: { II ii = and_R<IYH,T::CC_DD>(); NEXT; }
2174 case 0xa5: { II ii = and_R<IYL,T::CC_DD>(); NEXT; }
2175 case 0xa6: { II ii = and_xix<IY>(); NEXT; }
2176 case 0xac: { II ii = xor_R<IYH,T::CC_DD>(); NEXT; }
2177 case 0xad: { II ii = xor_R<IYL,T::CC_DD>(); NEXT; }
2178 case 0xae: { II ii = xor_xix<IY>(); NEXT; }
2179 case 0xb4: { II ii = or_R<IYH,T::CC_DD>(); NEXT; }
2180 case 0xb5: { II ii = or_R<IYL,T::CC_DD>(); NEXT; }
2181 case 0xb6: { II ii = or_xix<IY>(); NEXT; }
2182 case 0xbc: { II ii = cp_R<IYH,T::CC_DD>(); NEXT; }
2183 case 0xbd: { II ii = cp_R<IYL,T::CC_DD>(); NEXT; }
2184 case 0xbe: { II ii = cp_xix<IY>(); NEXT; }
2185
2186 case 0xe1: { II ii = pop_SS <IY,T::CC_DD>(); NEXT; }
2187 case 0xe5: { II ii = push_SS<IY,T::CC_DD>(); NEXT; }
2188 case 0xe3: { II ii = ex_xsp_SS<IY,T::CC_DD>(); NEXT; }
2189 case 0xe9: { II ii = jp_SS<IY,T::CC_DD>(); NEXT; }
2190 case 0xf9: { II ii = ld_sp_SS<IY,T::CC_DD>(); NEXT; }
2191 case 0xcb: ixy = getIY(); goto xx_cb;
2192 case 0xdd: T::add(T::CC_DD); goto opDD_2;
2193 case 0xfd: T::add(T::CC_DD); goto opFD_2;
2194 default: UNREACHABLE; return;
2195 }
2196}
2197#ifndef USE_COMPUTED_GOTO
2198 default: UNREACHABLE; return;
2199}
2200#endif
2201
2202xx_cb: {
2203 unsigned tmp = RD_WORD_PC<1>(T::CC_DD + T::CC_DD_CB);
2204 int8_t ofst = tmp & 0xFF;
2205 unsigned addr = (ixy + ofst) & 0xFFFF;
2206 byte xxcb_opcode = tmp >> 8;
2207 switch (xxcb_opcode) {
2208 case 0x00: { II ii = rlc_xix_R<B>(addr); NEXT; }
2209 case 0x01: { II ii = rlc_xix_R<C>(addr); NEXT; }
2210 case 0x02: { II ii = rlc_xix_R<D>(addr); NEXT; }
2211 case 0x03: { II ii = rlc_xix_R<E>(addr); NEXT; }
2212 case 0x04: { II ii = rlc_xix_R<H>(addr); NEXT; }
2213 case 0x05: { II ii = rlc_xix_R<L>(addr); NEXT; }
2214 case 0x06: { II ii = rlc_xix_R<DUMMY>(addr); NEXT; }
2215 case 0x07: { II ii = rlc_xix_R<A>(addr); NEXT; }
2216 case 0x08: { II ii = rrc_xix_R<B>(addr); NEXT; }
2217 case 0x09: { II ii = rrc_xix_R<C>(addr); NEXT; }
2218 case 0x0a: { II ii = rrc_xix_R<D>(addr); NEXT; }
2219 case 0x0b: { II ii = rrc_xix_R<E>(addr); NEXT; }
2220 case 0x0c: { II ii = rrc_xix_R<H>(addr); NEXT; }
2221 case 0x0d: { II ii = rrc_xix_R<L>(addr); NEXT; }
2222 case 0x0e: { II ii = rrc_xix_R<DUMMY>(addr); NEXT; }
2223 case 0x0f: { II ii = rrc_xix_R<A>(addr); NEXT; }
2224 case 0x10: { II ii = rl_xix_R<B>(addr); NEXT; }
2225 case 0x11: { II ii = rl_xix_R<C>(addr); NEXT; }
2226 case 0x12: { II ii = rl_xix_R<D>(addr); NEXT; }
2227 case 0x13: { II ii = rl_xix_R<E>(addr); NEXT; }
2228 case 0x14: { II ii = rl_xix_R<H>(addr); NEXT; }
2229 case 0x15: { II ii = rl_xix_R<L>(addr); NEXT; }
2230 case 0x16: { II ii = rl_xix_R<DUMMY>(addr); NEXT; }
2231 case 0x17: { II ii = rl_xix_R<A>(addr); NEXT; }
2232 case 0x18: { II ii = rr_xix_R<B>(addr); NEXT; }
2233 case 0x19: { II ii = rr_xix_R<C>(addr); NEXT; }
2234 case 0x1a: { II ii = rr_xix_R<D>(addr); NEXT; }
2235 case 0x1b: { II ii = rr_xix_R<E>(addr); NEXT; }
2236 case 0x1c: { II ii = rr_xix_R<H>(addr); NEXT; }
2237 case 0x1d: { II ii = rr_xix_R<L>(addr); NEXT; }
2238 case 0x1e: { II ii = rr_xix_R<DUMMY>(addr); NEXT; }
2239 case 0x1f: { II ii = rr_xix_R<A>(addr); NEXT; }
2240 case 0x20: { II ii = sla_xix_R<B>(addr); NEXT; }
2241 case 0x21: { II ii = sla_xix_R<C>(addr); NEXT; }
2242 case 0x22: { II ii = sla_xix_R<D>(addr); NEXT; }
2243 case 0x23: { II ii = sla_xix_R<E>(addr); NEXT; }
2244 case 0x24: { II ii = sla_xix_R<H>(addr); NEXT; }
2245 case 0x25: { II ii = sla_xix_R<L>(addr); NEXT; }
2246 case 0x26: { II ii = sla_xix_R<DUMMY>(addr); NEXT; }
2247 case 0x27: { II ii = sla_xix_R<A>(addr); NEXT; }
2248 case 0x28: { II ii = sra_xix_R<B>(addr); NEXT; }
2249 case 0x29: { II ii = sra_xix_R<C>(addr); NEXT; }
2250 case 0x2a: { II ii = sra_xix_R<D>(addr); NEXT; }
2251 case 0x2b: { II ii = sra_xix_R<E>(addr); NEXT; }
2252 case 0x2c: { II ii = sra_xix_R<H>(addr); NEXT; }
2253 case 0x2d: { II ii = sra_xix_R<L>(addr); NEXT; }
2254 case 0x2e: { II ii = sra_xix_R<DUMMY>(addr); NEXT; }
2255 case 0x2f: { II ii = sra_xix_R<A>(addr); NEXT; }
2256 case 0x30: { II ii = T::IS_R800 ? sll2() : sll_xix_R<B>(addr); NEXT; }
2257 case 0x31: { II ii = T::IS_R800 ? sll2() : sll_xix_R<C>(addr); NEXT; }
2258 case 0x32: { II ii = T::IS_R800 ? sll2() : sll_xix_R<D>(addr); NEXT; }
2259 case 0x33: { II ii = T::IS_R800 ? sll2() : sll_xix_R<E>(addr); NEXT; }
2260 case 0x34: { II ii = T::IS_R800 ? sll2() : sll_xix_R<H>(addr); NEXT; }
2261 case 0x35: { II ii = T::IS_R800 ? sll2() : sll_xix_R<L>(addr); NEXT; }
2262 case 0x36: { II ii = T::IS_R800 ? sll2() : sll_xix_R<DUMMY>(addr); NEXT; }
2263 case 0x37: { II ii = T::IS_R800 ? sll2() : sll_xix_R<A>(addr); NEXT; }
2264 case 0x38: { II ii = srl_xix_R<B>(addr); NEXT; }
2265 case 0x39: { II ii = srl_xix_R<C>(addr); NEXT; }
2266 case 0x3a: { II ii = srl_xix_R<D>(addr); NEXT; }
2267 case 0x3b: { II ii = srl_xix_R<E>(addr); NEXT; }
2268 case 0x3c: { II ii = srl_xix_R<H>(addr); NEXT; }
2269 case 0x3d: { II ii = srl_xix_R<L>(addr); NEXT; }
2270 case 0x3e: { II ii = srl_xix_R<DUMMY>(addr); NEXT; }
2271 case 0x3f: { II ii = srl_xix_R<A>(addr); NEXT; }
2272
2273 case 0x40: case 0x41: case 0x42: case 0x43:
2274 case 0x44: case 0x45: case 0x46: case 0x47:
2275 { II ii = bit_N_xix<0>(addr); NEXT; }
2276 case 0x48: case 0x49: case 0x4a: case 0x4b:
2277 case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2278 { II ii = bit_N_xix<1>(addr); NEXT; }
2279 case 0x50: case 0x51: case 0x52: case 0x53:
2280 case 0x54: case 0x55: case 0x56: case 0x57:
2281 { II ii = bit_N_xix<2>(addr); NEXT; }
2282 case 0x58: case 0x59: case 0x5a: case 0x5b:
2283 case 0x5c: case 0x5d: case 0x5e: case 0x5f:
2284 { II ii = bit_N_xix<3>(addr); NEXT; }
2285 case 0x60: case 0x61: case 0x62: case 0x63:
2286 case 0x64: case 0x65: case 0x66: case 0x67:
2287 { II ii = bit_N_xix<4>(addr); NEXT; }
2288 case 0x68: case 0x69: case 0x6a: case 0x6b:
2289 case 0x6c: case 0x6d: case 0x6e: case 0x6f:
2290 { II ii = bit_N_xix<5>(addr); NEXT; }
2291 case 0x70: case 0x71: case 0x72: case 0x73:
2292 case 0x74: case 0x75: case 0x76: case 0x77:
2293 { II ii = bit_N_xix<6>(addr); NEXT; }
2294 case 0x78: case 0x79: case 0x7a: case 0x7b:
2295 case 0x7c: case 0x7d: case 0x7e: case 0x7f:
2296 { II ii = bit_N_xix<7>(addr); NEXT; }
2297
2298 case 0x80: { II ii = res_N_xix_R<0,B>(addr); NEXT; }
2299 case 0x81: { II ii = res_N_xix_R<0,C>(addr); NEXT; }
2300 case 0x82: { II ii = res_N_xix_R<0,D>(addr); NEXT; }
2301 case 0x83: { II ii = res_N_xix_R<0,E>(addr); NEXT; }
2302 case 0x84: { II ii = res_N_xix_R<0,H>(addr); NEXT; }
2303 case 0x85: { II ii = res_N_xix_R<0,L>(addr); NEXT; }
2304 case 0x87: { II ii = res_N_xix_R<0,A>(addr); NEXT; }
2305 case 0x88: { II ii = res_N_xix_R<1,B>(addr); NEXT; }
2306 case 0x89: { II ii = res_N_xix_R<1,C>(addr); NEXT; }
2307 case 0x8a: { II ii = res_N_xix_R<1,D>(addr); NEXT; }
2308 case 0x8b: { II ii = res_N_xix_R<1,E>(addr); NEXT; }
2309 case 0x8c: { II ii = res_N_xix_R<1,H>(addr); NEXT; }
2310 case 0x8d: { II ii = res_N_xix_R<1,L>(addr); NEXT; }
2311 case 0x8f: { II ii = res_N_xix_R<1,A>(addr); NEXT; }
2312 case 0x90: { II ii = res_N_xix_R<2,B>(addr); NEXT; }
2313 case 0x91: { II ii = res_N_xix_R<2,C>(addr); NEXT; }
2314 case 0x92: { II ii = res_N_xix_R<2,D>(addr); NEXT; }
2315 case 0x93: { II ii = res_N_xix_R<2,E>(addr); NEXT; }
2316 case 0x94: { II ii = res_N_xix_R<2,H>(addr); NEXT; }
2317 case 0x95: { II ii = res_N_xix_R<2,L>(addr); NEXT; }
2318 case 0x97: { II ii = res_N_xix_R<2,A>(addr); NEXT; }
2319 case 0x98: { II ii = res_N_xix_R<3,B>(addr); NEXT; }
2320 case 0x99: { II ii = res_N_xix_R<3,C>(addr); NEXT; }
2321 case 0x9a: { II ii = res_N_xix_R<3,D>(addr); NEXT; }
2322 case 0x9b: { II ii = res_N_xix_R<3,E>(addr); NEXT; }
2323 case 0x9c: { II ii = res_N_xix_R<3,H>(addr); NEXT; }
2324 case 0x9d: { II ii = res_N_xix_R<3,L>(addr); NEXT; }
2325 case 0x9f: { II ii = res_N_xix_R<3,A>(addr); NEXT; }
2326 case 0xa0: { II ii = res_N_xix_R<4,B>(addr); NEXT; }
2327 case 0xa1: { II ii = res_N_xix_R<4,C>(addr); NEXT; }
2328 case 0xa2: { II ii = res_N_xix_R<4,D>(addr); NEXT; }
2329 case 0xa3: { II ii = res_N_xix_R<4,E>(addr); NEXT; }
2330 case 0xa4: { II ii = res_N_xix_R<4,H>(addr); NEXT; }
2331 case 0xa5: { II ii = res_N_xix_R<4,L>(addr); NEXT; }
2332 case 0xa7: { II ii = res_N_xix_R<4,A>(addr); NEXT; }
2333 case 0xa8: { II ii = res_N_xix_R<5,B>(addr); NEXT; }
2334 case 0xa9: { II ii = res_N_xix_R<5,C>(addr); NEXT; }
2335 case 0xaa: { II ii = res_N_xix_R<5,D>(addr); NEXT; }
2336 case 0xab: { II ii = res_N_xix_R<5,E>(addr); NEXT; }
2337 case 0xac: { II ii = res_N_xix_R<5,H>(addr); NEXT; }
2338 case 0xad: { II ii = res_N_xix_R<5,L>(addr); NEXT; }
2339 case 0xaf: { II ii = res_N_xix_R<5,A>(addr); NEXT; }
2340 case 0xb0: { II ii = res_N_xix_R<6,B>(addr); NEXT; }
2341 case 0xb1: { II ii = res_N_xix_R<6,C>(addr); NEXT; }
2342 case 0xb2: { II ii = res_N_xix_R<6,D>(addr); NEXT; }
2343 case 0xb3: { II ii = res_N_xix_R<6,E>(addr); NEXT; }
2344 case 0xb4: { II ii = res_N_xix_R<6,H>(addr); NEXT; }
2345 case 0xb5: { II ii = res_N_xix_R<6,L>(addr); NEXT; }
2346 case 0xb7: { II ii = res_N_xix_R<6,A>(addr); NEXT; }
2347 case 0xb8: { II ii = res_N_xix_R<7,B>(addr); NEXT; }
2348 case 0xb9: { II ii = res_N_xix_R<7,C>(addr); NEXT; }
2349 case 0xba: { II ii = res_N_xix_R<7,D>(addr); NEXT; }
2350 case 0xbb: { II ii = res_N_xix_R<7,E>(addr); NEXT; }
2351 case 0xbc: { II ii = res_N_xix_R<7,H>(addr); NEXT; }
2352 case 0xbd: { II ii = res_N_xix_R<7,L>(addr); NEXT; }
2353 case 0xbf: { II ii = res_N_xix_R<7,A>(addr); NEXT; }
2354 case 0x86: { II ii = res_N_xix_R<0,DUMMY>(addr); NEXT; }
2355 case 0x8e: { II ii = res_N_xix_R<1,DUMMY>(addr); NEXT; }
2356 case 0x96: { II ii = res_N_xix_R<2,DUMMY>(addr); NEXT; }
2357 case 0x9e: { II ii = res_N_xix_R<3,DUMMY>(addr); NEXT; }
2358 case 0xa6: { II ii = res_N_xix_R<4,DUMMY>(addr); NEXT; }
2359 case 0xae: { II ii = res_N_xix_R<5,DUMMY>(addr); NEXT; }
2360 case 0xb6: { II ii = res_N_xix_R<6,DUMMY>(addr); NEXT; }
2361 case 0xbe: { II ii = res_N_xix_R<7,DUMMY>(addr); NEXT; }
2362
2363 case 0xc0: { II ii = set_N_xix_R<0,B>(addr); NEXT; }
2364 case 0xc1: { II ii = set_N_xix_R<0,C>(addr); NEXT; }
2365 case 0xc2: { II ii = set_N_xix_R<0,D>(addr); NEXT; }
2366 case 0xc3: { II ii = set_N_xix_R<0,E>(addr); NEXT; }
2367 case 0xc4: { II ii = set_N_xix_R<0,H>(addr); NEXT; }
2368 case 0xc5: { II ii = set_N_xix_R<0,L>(addr); NEXT; }
2369 case 0xc7: { II ii = set_N_xix_R<0,A>(addr); NEXT; }
2370 case 0xc8: { II ii = set_N_xix_R<1,B>(addr); NEXT; }
2371 case 0xc9: { II ii = set_N_xix_R<1,C>(addr); NEXT; }
2372 case 0xca: { II ii = set_N_xix_R<1,D>(addr); NEXT; }
2373 case 0xcb: { II ii = set_N_xix_R<1,E>(addr); NEXT; }
2374 case 0xcc: { II ii = set_N_xix_R<1,H>(addr); NEXT; }
2375 case 0xcd: { II ii = set_N_xix_R<1,L>(addr); NEXT; }
2376 case 0xcf: { II ii = set_N_xix_R<1,A>(addr); NEXT; }
2377 case 0xd0: { II ii = set_N_xix_R<2,B>(addr); NEXT; }
2378 case 0xd1: { II ii = set_N_xix_R<2,C>(addr); NEXT; }
2379 case 0xd2: { II ii = set_N_xix_R<2,D>(addr); NEXT; }
2380 case 0xd3: { II ii = set_N_xix_R<2,E>(addr); NEXT; }
2381 case 0xd4: { II ii = set_N_xix_R<2,H>(addr); NEXT; }
2382 case 0xd5: { II ii = set_N_xix_R<2,L>(addr); NEXT; }
2383 case 0xd7: { II ii = set_N_xix_R<2,A>(addr); NEXT; }
2384 case 0xd8: { II ii = set_N_xix_R<3,B>(addr); NEXT; }
2385 case 0xd9: { II ii = set_N_xix_R<3,C>(addr); NEXT; }
2386 case 0xda: { II ii = set_N_xix_R<3,D>(addr); NEXT; }
2387 case 0xdb: { II ii = set_N_xix_R<3,E>(addr); NEXT; }
2388 case 0xdc: { II ii = set_N_xix_R<3,H>(addr); NEXT; }
2389 case 0xdd: { II ii = set_N_xix_R<3,L>(addr); NEXT; }
2390 case 0xdf: { II ii = set_N_xix_R<3,A>(addr); NEXT; }
2391 case 0xe0: { II ii = set_N_xix_R<4,B>(addr); NEXT; }
2392 case 0xe1: { II ii = set_N_xix_R<4,C>(addr); NEXT; }
2393 case 0xe2: { II ii = set_N_xix_R<4,D>(addr); NEXT; }
2394 case 0xe3: { II ii = set_N_xix_R<4,E>(addr); NEXT; }
2395 case 0xe4: { II ii = set_N_xix_R<4,H>(addr); NEXT; }
2396 case 0xe5: { II ii = set_N_xix_R<4,L>(addr); NEXT; }
2397 case 0xe7: { II ii = set_N_xix_R<4,A>(addr); NEXT; }
2398 case 0xe8: { II ii = set_N_xix_R<5,B>(addr); NEXT; }
2399 case 0xe9: { II ii = set_N_xix_R<5,C>(addr); NEXT; }
2400 case 0xea: { II ii = set_N_xix_R<5,D>(addr); NEXT; }
2401 case 0xeb: { II ii = set_N_xix_R<5,E>(addr); NEXT; }
2402 case 0xec: { II ii = set_N_xix_R<5,H>(addr); NEXT; }
2403 case 0xed: { II ii = set_N_xix_R<5,L>(addr); NEXT; }
2404 case 0xef: { II ii = set_N_xix_R<5,A>(addr); NEXT; }
2405 case 0xf0: { II ii = set_N_xix_R<6,B>(addr); NEXT; }
2406 case 0xf1: { II ii = set_N_xix_R<6,C>(addr); NEXT; }
2407 case 0xf2: { II ii = set_N_xix_R<6,D>(addr); NEXT; }
2408 case 0xf3: { II ii = set_N_xix_R<6,E>(addr); NEXT; }
2409 case 0xf4: { II ii = set_N_xix_R<6,H>(addr); NEXT; }
2410 case 0xf5: { II ii = set_N_xix_R<6,L>(addr); NEXT; }
2411 case 0xf7: { II ii = set_N_xix_R<6,A>(addr); NEXT; }
2412 case 0xf8: { II ii = set_N_xix_R<7,B>(addr); NEXT; }
2413 case 0xf9: { II ii = set_N_xix_R<7,C>(addr); NEXT; }
2414 case 0xfa: { II ii = set_N_xix_R<7,D>(addr); NEXT; }
2415 case 0xfb: { II ii = set_N_xix_R<7,E>(addr); NEXT; }
2416 case 0xfc: { II ii = set_N_xix_R<7,H>(addr); NEXT; }
2417 case 0xfd: { II ii = set_N_xix_R<7,L>(addr); NEXT; }
2418 case 0xff: { II ii = set_N_xix_R<7,A>(addr); NEXT; }
2419 case 0xc6: { II ii = set_N_xix_R<0,DUMMY>(addr); NEXT; }
2420 case 0xce: { II ii = set_N_xix_R<1,DUMMY>(addr); NEXT; }
2421 case 0xd6: { II ii = set_N_xix_R<2,DUMMY>(addr); NEXT; }
2422 case 0xde: { II ii = set_N_xix_R<3,DUMMY>(addr); NEXT; }
2423 case 0xe6: { II ii = set_N_xix_R<4,DUMMY>(addr); NEXT; }
2424 case 0xee: { II ii = set_N_xix_R<5,DUMMY>(addr); NEXT; }
2425 case 0xf6: { II ii = set_N_xix_R<6,DUMMY>(addr); NEXT; }
2426 case 0xfe: { II ii = set_N_xix_R<7,DUMMY>(addr); NEXT; }
2427 default: UNREACHABLE;
2428 }
2429 }
2430}
2431
2432template<typename T> inline void CPUCore<T>::cpuTracePre()
2433{
2434 start_pc = getPC();
2435}
2436template<typename T> inline void CPUCore<T>::cpuTracePost()
2437{
2438 if (tracingEnabled) [[unlikely]] {
2439 cpuTracePost_slow();
2440 }
2441}
2442template<typename T> void CPUCore<T>::cpuTracePost_slow()
2443{
2444 byte opBuf[4];
2445 std::string dasmOutput;
2446 dasm(*interface, start_pc, opBuf, dasmOutput, T::getTimeFast());
2447 std::cout << strCat(hex_string<4>(start_pc),
2448 " : ", dasmOutput,
2449 " AF=", hex_string<4>(getAF()),
2450 " BC=", hex_string<4>(getBC()),
2451 " DE=", hex_string<4>(getDE()),
2452 " HL=", hex_string<4>(getHL()),
2453 " IX=", hex_string<4>(getIX()),
2454 " IY=", hex_string<4>(getIY()),
2455 " SP=", hex_string<4>(getSP()),
2456 '\n')
2457 << std::flush;
2458}
2459
2460template<typename T> ExecIRQ CPUCore<T>::getExecIRQ() const
2461{
2462 if (nmiEdge) [[unlikely]] return ExecIRQ::NMI;
2463 if (IRQStatus && getIFF1() && !prevWasEI()) [[unlikely]] return ExecIRQ::IRQ;
2464 return ExecIRQ::NONE;
2465}
2466
2467template<typename T> void CPUCore<T>::executeSlow(ExecIRQ execIRQ)
2468{
2469 if (execIRQ == ExecIRQ::NMI) [[unlikely]] {
2470 nmiEdge = false;
2471 nmi(); // NMI occurred
2472 } else if (execIRQ == ExecIRQ::IRQ) [[unlikely]] {
2473 // normal interrupt
2474 if (prevWasLDAI()) [[unlikely]] {
2475 // HACK!!!
2476 // The 'ld a,i' or 'ld a,r' instruction copies the IFF2
2477 // bit to the V flag. Though when the Z80 accepts an
2478 // IRQ directly after this instruction, the V flag is 0
2479 // (instead of the expected value 1). This can probably
2480 // be explained if you look at the pipeline of the Z80.
2481 // But for speed reasons we implement it here as a
2482 // fix-up (a hack) in the IRQ routine. This behaviour
2483 // is actually a bug in the Z80.
2484 // Thanks to n_n for reporting this behaviour. I think
2485 // this was discovered by GuyveR800. Also thanks to
2486 // n_n for writing a test program that demonstrates
2487 // this quirk.
2488 // I also wrote a test program that demonstrates this
2489 // behaviour is the same whether 'ld a,i' is preceded
2490 // by a 'ei' instruction or not (so it's not caused by
2491 // the 'delayed IRQ acceptance of ei').
2492 assert(getF() & V_FLAG);
2493 setF(getF() & ~V_FLAG);
2494 }
2495 IRQAccept.signal();
2496 switch (getIM()) {
2497 case 0: irq0();
2498 break;
2499 case 1: irq1();
2500 break;
2501 case 2: irq2();
2502 break;
2503 default:
2505 }
2506 } else if (getHALT()) [[unlikely]] {
2507 // in halt mode
2508 incR(T::advanceHalt(T::HALT_STATES, scheduler.getNext()));
2509 setSlowInstructions();
2510 } else {
2511 cpuTracePre();
2512 assert(T::limitReached()); // we want only one instruction
2513 executeInstructions();
2514 endInstruction();
2515
2516 if constexpr (T::IS_R800) {
2517 if (/*unlikely*/(prev2WasCall()) && /*likely*/(!prevWasPopRet())) [[unlikely]] {
2518 // On R800 a CALL or RST instruction not _immediately_
2519 // followed by a (single-byte) POP or RET instruction
2520 // causes an extra cycle in that following instruction.
2521 // No idea why yet. See doc/internal/r800-call.txt
2522 // for more information.
2523 //
2524 // TODO this implementation adds the extra cycle at
2525 // the end of the instruction POP/RET. It is not known
2526 // where in the instruction the real R800 adds this cycle.
2527 T::add(1);
2528 }
2529 }
2530 cpuTracePost();
2531 }
2532}
2533
2534template<typename T> void CPUCore<T>::execute(bool fastForward)
2535{
2536 // In fast-forward mode, breakpoints, watchpoints or debug condtions
2537 // won't trigger. It is possible we already are in break mode, but
2538 // break is ignored in fast-forward mode.
2539 assert(fastForward || !interface->isBreaked());
2540 if (fastForward) {
2541 interface->setFastForward(true);
2542 }
2543 execute2(fastForward);
2544 interface->setFastForward(false);
2545}
2546
2547template<typename T> void CPUCore<T>::execute2(bool fastForward)
2548{
2549 // note: Don't use getTimeFast() here, because 'once in a while' we
2550 // need to CPUClock::sync() to avoid overflow.
2551 // Should be done at least once per second (approx). So only
2552 // once in this method is enough.
2553 scheduler.schedule(T::getTime());
2554 setSlowInstructions();
2555
2556 // Note: we call scheduler _after_ executing the instruction and before
2557 // deciding between executeFast() and executeSlow() (because a
2558 // SyncPoint could set an IRQ and then we must choose executeSlow())
2559 if (fastForward ||
2560 (!interface->anyBreakPoints() && !tracingEnabled)) {
2561 // fast path, no breakpoints, no tracing
2562 do {
2563 if (slowInstructions) {
2564 --slowInstructions;
2565 executeSlow(getExecIRQ());
2566 scheduler.schedule(T::getTimeFast());
2567 } else {
2568 while (slowInstructions == 0) {
2569 T::enableLimit(); // does CPUClock::sync()
2570 if (!T::limitReached()) [[likely]] {
2571 // multiple instructions
2572 executeInstructions();
2573 // note: pipeline only shifted one
2574 // step for multiple instructions
2575 endInstruction();
2576 }
2577 scheduler.schedule(T::getTimeFast());
2578 if (needExitCPULoop()) return;
2579 }
2580 }
2581 } while (!needExitCPULoop());
2582 } else {
2583 do {
2584 if (slowInstructions == 0) {
2585 cpuTracePre();
2586 assert(T::limitReached()); // only one instruction
2587 executeInstructions();
2588 endInstruction();
2589 cpuTracePost();
2590 } else {
2591 --slowInstructions;
2592 executeSlow(getExecIRQ());
2593 }
2594 // Don't use getTimeFast() here, we need a call to
2595 // CPUClock::sync() 'once in a while'. (During a
2596 // reverse fast-forward this wasn't always the case).
2597 scheduler.schedule(T::getTime());
2598
2599 // Only check for breakpoints when we're not about to jump to an IRQ handler.
2600 //
2601 // This fixes the following problem reported by Grauw:
2602 //
2603 // I found a breakpoints bug: sometimes a breakpoint gets hit twice even
2604 // though the code is executed once. This manifests itself in my profiler
2605 // as an imbalance between section begin- and end-calls.
2606 //
2607 // Turns out this occurs when an interrupt occurs exactly on the line of
2608 // the breakpoint, then the breakpoint gets hit before immediately going
2609 // to the ISR, as well as when returning from the ISR.
2610 //
2611 // The IRQ is handled by the Z80 at the end of an instruction. So it
2612 // should change the PC before the next instruction is fetched and the
2613 // breakpoints should be evaluated during instruction fetch.
2614 //
2615 // I think Grauw's analysis is correct. Though for performance reasons we
2616 // don't emulate the Z80 like that: we don't check for IRQs at the end of
2617 // every instruction. In the openMSX emulation model, we can only enter an
2618 // ISR:
2619 // - (One instruction after) switching from DI to EI mode.
2620 // - After emulating device code. This can be:
2621 // * When the Z80 communicated with the device (IO or memory mapped IO).
2622 // * The device had set a synchronization point.
2623 // In all cases disableLimit() gets called which will cause
2624 // limitReached() to return true (and possibly slowInstructions to be > 0).
2625 // So after most emulated Z80 instructions there can't be a pending IRQ, so
2626 // checking for it is wasteful. Also synchronization points are handled
2627 // between emulated Z80 instructions, that means me must check for pending
2628 // IRQs at the start (instead of end) of an instruction.
2629 //
2630 auto execIRQ = getExecIRQ();
2631 if ((execIRQ == ExecIRQ::NONE) &&
2632 interface->checkBreakPoints(getPC())) {
2633 assert(interface->isBreaked());
2634 break;
2635 }
2636 } while (!needExitCPULoop());
2637 }
2638}
2639
2640template<typename T> template<Reg8 R8> ALWAYS_INLINE byte CPUCore<T>::get8() const {
2641 if constexpr (R8 == A) { return getA(); }
2642 else if constexpr (R8 == F) { return getF(); }
2643 else if constexpr (R8 == B) { return getB(); }
2644 else if constexpr (R8 == C) { return getC(); }
2645 else if constexpr (R8 == D) { return getD(); }
2646 else if constexpr (R8 == E) { return getE(); }
2647 else if constexpr (R8 == H) { return getH(); }
2648 else if constexpr (R8 == L) { return getL(); }
2649 else if constexpr (R8 == IXH) { return getIXh(); }
2650 else if constexpr (R8 == IXL) { return getIXl(); }
2651 else if constexpr (R8 == IYH) { return getIYh(); }
2652 else if constexpr (R8 == IYL) { return getIYl(); }
2653 else if constexpr (R8 == REG_I) { return getI(); }
2654 else if constexpr (R8 == REG_R) { return getR(); }
2655 else if constexpr (R8 == DUMMY) { return 0; }
2656 else { UNREACHABLE; return 0; }
2657}
2658template<typename T> template<Reg16 R16> ALWAYS_INLINE unsigned CPUCore<T>::get16() const {
2659 if constexpr (R16 == AF) { return getAF(); }
2660 else if constexpr (R16 == BC) { return getBC(); }
2661 else if constexpr (R16 == DE) { return getDE(); }
2662 else if constexpr (R16 == HL) { return getHL(); }
2663 else if constexpr (R16 == IX) { return getIX(); }
2664 else if constexpr (R16 == IY) { return getIY(); }
2665 else if constexpr (R16 == SP) { return getSP(); }
2666 else { UNREACHABLE; return 0; }
2667}
2668template<typename T> template<Reg8 R8> ALWAYS_INLINE void CPUCore<T>::set8(byte x) {
2669 if constexpr (R8 == A) { setA(x); }
2670 else if constexpr (R8 == F) { setF(x); }
2671 else if constexpr (R8 == B) { setB(x); }
2672 else if constexpr (R8 == C) { setC(x); }
2673 else if constexpr (R8 == D) { setD(x); }
2674 else if constexpr (R8 == E) { setE(x); }
2675 else if constexpr (R8 == H) { setH(x); }
2676 else if constexpr (R8 == L) { setL(x); }
2677 else if constexpr (R8 == IXH) { setIXh(x); }
2678 else if constexpr (R8 == IXL) { setIXl(x); }
2679 else if constexpr (R8 == IYH) { setIYh(x); }
2680 else if constexpr (R8 == IYL) { setIYl(x); }
2681 else if constexpr (R8 == REG_I) { setI(x); }
2682 else if constexpr (R8 == REG_R) { setR(x); }
2683 else if constexpr (R8 == DUMMY) { /* nothing */ }
2684 else { UNREACHABLE; }
2685}
2686template<typename T> template<Reg16 R16> ALWAYS_INLINE void CPUCore<T>::set16(unsigned x) {
2687 if constexpr (R16 == AF) { setAF(x); }
2688 else if constexpr (R16 == BC) { setBC(x); }
2689 else if constexpr (R16 == DE) { setDE(x); }
2690 else if constexpr (R16 == HL) { setHL(x); }
2691 else if constexpr (R16 == IX) { setIX(x); }
2692 else if constexpr (R16 == IY) { setIY(x); }
2693 else if constexpr (R16 == SP) { setSP(x); }
2694 else { UNREACHABLE; }
2695}
2696
2697// LD r,r
2698template<typename T> template<Reg8 DST, Reg8 SRC, int EE> II CPUCore<T>::ld_R_R() {
2699 set8<DST>(get8<SRC>()); return {1, T::CC_LD_R_R + EE};
2700}
2701
2702// LD SP,ss
2703template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ld_sp_SS() {
2704 setSP(get16<REG>()); return {1, T::CC_LD_SP_HL + EE};
2705}
2706
2707// LD (ss),a
2708template<typename T> template<Reg16 REG> II CPUCore<T>::ld_SS_a() {
2709 T::setMemPtr((getA() << 8) | ((get16<REG>() + 1) & 0xFF));
2710 WRMEM(get16<REG>(), getA(), T::CC_LD_SS_A_1);
2711 return {1, T::CC_LD_SS_A};
2712}
2713
2714// LD (HL),r
2715template<typename T> template<Reg8 SRC> II CPUCore<T>::ld_xhl_R() {
2716 WRMEM(getHL(), get8<SRC>(), T::CC_LD_HL_R_1);
2717 return {1, T::CC_LD_HL_R};
2718}
2719
2720// LD (IXY+e),r
2721template<typename T> template<Reg16 IXY, Reg8 SRC> II CPUCore<T>::ld_xix_R() {
2722 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_LD_XIX_R_1);
2723 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2724 T::setMemPtr(addr);
2725 WRMEM(addr, get8<SRC>(), T::CC_DD + T::CC_LD_XIX_R_2);
2726 return {2, T::CC_DD + T::CC_LD_XIX_R};
2727}
2728
2729// LD (HL),n
2730template<typename T> II CPUCore<T>::ld_xhl_byte() {
2731 byte val = RDMEM_OPCODE<1>(T::CC_LD_HL_N_1);
2732 WRMEM(getHL(), val, T::CC_LD_HL_N_2);
2733 return {2, T::CC_LD_HL_N};
2734}
2735
2736// LD (IXY+e),n
2737template<typename T> template<Reg16 IXY> II CPUCore<T>::ld_xix_byte() {
2738 unsigned tmp = RD_WORD_PC<1>(T::CC_DD + T::CC_LD_XIX_N_1);
2739 int8_t ofst = tmp & 0xFF;
2740 byte val = tmp >> 8;
2741 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2742 T::setMemPtr(addr);
2743 WRMEM(addr, val, T::CC_DD + T::CC_LD_XIX_N_2);
2744 return {3, T::CC_DD + T::CC_LD_XIX_N};
2745}
2746
2747// LD (nn),A
2748template<typename T> II CPUCore<T>::ld_xbyte_a() {
2749 unsigned x = RD_WORD_PC<1>(T::CC_LD_NN_A_1);
2750 T::setMemPtr((getA() << 8) | ((x + 1) & 0xFF));
2751 WRMEM(x, getA(), T::CC_LD_NN_A_2);
2752 return {3, T::CC_LD_NN_A};
2753}
2754
2755// LD (nn),ss
2756template<typename T> template<int EE> inline II CPUCore<T>::WR_NN_Y(unsigned reg) {
2757 unsigned addr = RD_WORD_PC<1>(T::CC_LD_XX_HL_1 + EE);
2758 T::setMemPtr(addr + 1);
2759 WR_WORD(addr, reg, T::CC_LD_XX_HL_2 + EE);
2760 return {3, T::CC_LD_XX_HL + EE};
2761}
2762template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ld_xword_SS() {
2763 return WR_NN_Y<EE >(get16<REG>());
2764}
2765template<typename T> template<Reg16 REG> II CPUCore<T>::ld_xword_SS_ED() {
2766 return WR_NN_Y<T::EE_ED>(get16<REG>());
2767}
2768
2769// LD A,(ss)
2770template<typename T> template<Reg16 REG> II CPUCore<T>::ld_a_SS() {
2771 T::setMemPtr(get16<REG>() + 1);
2772 setA(RDMEM(get16<REG>(), T::CC_LD_A_SS_1));
2773 return {1, T::CC_LD_A_SS};
2774}
2775
2776// LD A,(nn)
2777template<typename T> II CPUCore<T>::ld_a_xbyte() {
2778 unsigned addr = RD_WORD_PC<1>(T::CC_LD_A_NN_1);
2779 T::setMemPtr(addr + 1);
2780 setA(RDMEM(addr, T::CC_LD_A_NN_2));
2781 return {3, T::CC_LD_A_NN};
2782}
2783
2784// LD r,n
2785template<typename T> template<Reg8 DST, int EE> II CPUCore<T>::ld_R_byte() {
2786 set8<DST>(RDMEM_OPCODE<1>(T::CC_LD_R_N_1 + EE)); return {2, T::CC_LD_R_N + EE};
2787}
2788
2789// LD r,(hl)
2790template<typename T> template<Reg8 DST> II CPUCore<T>::ld_R_xhl() {
2791 set8<DST>(RDMEM(getHL(), T::CC_LD_R_HL_1)); return {1, T::CC_LD_R_HL};
2792}
2793
2794// LD r,(IXY+e)
2795template<typename T> template<Reg8 DST, Reg16 IXY> II CPUCore<T>::ld_R_xix() {
2796 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_LD_R_XIX_1);
2797 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2798 T::setMemPtr(addr);
2799 set8<DST>(RDMEM(addr, T::CC_DD + T::CC_LD_R_XIX_2));
2800 return {2, T::CC_DD + T::CC_LD_R_XIX};
2801}
2802
2803// LD ss,(nn)
2804template<typename T> template<int EE> inline unsigned CPUCore<T>::RD_P_XX() {
2805 unsigned addr = RD_WORD_PC<1>(T::CC_LD_HL_XX_1 + EE);
2806 T::setMemPtr(addr + 1);
2807 unsigned result = RD_WORD(addr, T::CC_LD_HL_XX_2 + EE);
2808 return result;
2809}
2810template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ld_SS_xword() {
2811 set16<REG>(RD_P_XX<EE>()); return {3, T::CC_LD_HL_XX + EE};
2812}
2813template<typename T> template<Reg16 REG> II CPUCore<T>::ld_SS_xword_ED() {
2814 set16<REG>(RD_P_XX<T::EE_ED>()); return {3, T::CC_LD_HL_XX + T::EE_ED};
2815}
2816
2817// LD ss,nn
2818template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ld_SS_word() {
2819 set16<REG>(RD_WORD_PC<1>(T::CC_LD_SS_NN_1 + EE)); return {3, T::CC_LD_SS_NN + EE};
2820}
2821
2822
2823// ADC A,r
2824template<typename T> inline void CPUCore<T>::ADC(byte reg) {
2825 unsigned res = getA() + reg + ((getF() & C_FLAG) ? 1 : 0);
2826 byte f = ((res & 0x100) ? C_FLAG : 0) |
2827 ((getA() ^ res ^ reg) & H_FLAG) |
2828 (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2829 0; // N_FLAG
2830 if constexpr (T::IS_R800) {
2831 f |= table.ZS[res & 0xFF];
2832 f |= getF() & (X_FLAG | Y_FLAG);
2833 } else {
2834 f |= table.ZSXY[res & 0xFF];
2835 }
2836 setF(f);
2837 setA(res);
2838}
2839template<typename T> inline II CPUCore<T>::adc_a_a() {
2840 unsigned res = 2 * getA() + ((getF() & C_FLAG) ? 1 : 0);
2841 byte f = ((res & 0x100) ? C_FLAG : 0) |
2842 (res & H_FLAG) |
2843 (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2844 0; // N_FLAG
2845 if constexpr (T::IS_R800) {
2846 f |= table.ZS[res & 0xFF];
2847 f |= getF() & (X_FLAG | Y_FLAG);
2848 } else {
2849 f |= table.ZSXY[res & 0xFF];
2850 }
2851 setF(f);
2852 setA(res);
2853 return {1, T::CC_CP_R};
2854}
2855template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::adc_a_R() {
2856 ADC(get8<SRC>()); return {1, T::CC_CP_R + EE};
2857}
2858template<typename T> II CPUCore<T>::adc_a_byte() {
2859 ADC(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2860}
2861template<typename T> II CPUCore<T>::adc_a_xhl() {
2862 ADC(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2863}
2864template<typename T> template<Reg16 IXY> II CPUCore<T>::adc_a_xix() {
2865 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2866 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2867 T::setMemPtr(addr);
2868 ADC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2869 return {2, T::CC_DD + T::CC_CP_XIX};
2870}
2871
2872// ADD A,r
2873template<typename T> inline void CPUCore<T>::ADD(byte reg) {
2874 unsigned res = getA() + reg;
2875 byte f = ((res & 0x100) ? C_FLAG : 0) |
2876 ((getA() ^ res ^ reg) & H_FLAG) |
2877 (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2878 0; // N_FLAG
2879 if constexpr (T::IS_R800) {
2880 f |= table.ZS[res & 0xFF];
2881 f |= getF() & (X_FLAG | Y_FLAG);
2882 } else {
2883 f |= table.ZSXY[res & 0xFF];
2884 }
2885 setF(f);
2886 setA(res);
2887}
2888template<typename T> inline II CPUCore<T>::add_a_a() {
2889 unsigned res = 2 * getA();
2890 byte f = ((res & 0x100) ? C_FLAG : 0) |
2891 (res & H_FLAG) |
2892 (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2893 0; // N_FLAG
2894 if constexpr (T::IS_R800) {
2895 f |= table.ZS[res & 0xFF];
2896 f |= getF() & (X_FLAG | Y_FLAG);
2897 } else {
2898 f |= table.ZSXY[res & 0xFF];
2899 }
2900 setF(f);
2901 setA(res);
2902 return {1, T::CC_CP_R};
2903}
2904template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::add_a_R() {
2905 ADD(get8<SRC>()); return {1, T::CC_CP_R + EE};
2906}
2907template<typename T> II CPUCore<T>::add_a_byte() {
2908 ADD(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2909}
2910template<typename T> II CPUCore<T>::add_a_xhl() {
2911 ADD(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2912}
2913template<typename T> template<Reg16 IXY> II CPUCore<T>::add_a_xix() {
2914 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2915 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2916 T::setMemPtr(addr);
2917 ADD(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2918 return {2, T::CC_DD + T::CC_CP_XIX};
2919}
2920
2921// AND r
2922template<typename T> inline void CPUCore<T>::AND(byte reg) {
2923 setA(getA() & reg);
2924 byte f = 0;
2925 if constexpr (T::IS_R800) {
2926 f |= table.ZSPH[getA()];
2927 f |= getF() & (X_FLAG | Y_FLAG);
2928 } else {
2929 f |= table.ZSPXY[getA()] | H_FLAG;
2930 }
2931 setF(f);
2932}
2933template<typename T> II CPUCore<T>::and_a() {
2934 byte f = 0;
2935 if constexpr (T::IS_R800) {
2936 f |= table.ZSPH[getA()];
2937 f |= getF() & (X_FLAG | Y_FLAG);
2938 } else {
2939 f |= table.ZSPXY[getA()] | H_FLAG;
2940 }
2941 setF(f);
2942 return {1, T::CC_CP_R};
2943}
2944template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::and_R() {
2945 AND(get8<SRC>()); return {1, T::CC_CP_R + EE};
2946}
2947template<typename T> II CPUCore<T>::and_byte() {
2948 AND(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2949}
2950template<typename T> II CPUCore<T>::and_xhl() {
2951 AND(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2952}
2953template<typename T> template<Reg16 IXY> II CPUCore<T>::and_xix() {
2954 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2955 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2956 T::setMemPtr(addr);
2957 AND(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2958 return {2, T::CC_DD + T::CC_CP_XIX};
2959}
2960
2961// CP r
2962template<typename T> inline void CPUCore<T>::CP(byte reg) {
2963 unsigned q = getA() - reg;
2964 byte f = table.ZS[q & 0xFF] |
2965 ((q & 0x100) ? C_FLAG : 0) |
2966 N_FLAG |
2967 ((getA() ^ q ^ reg) & H_FLAG) |
2968 (((reg ^ getA()) & (getA() ^ q) & 0x80) >> 5); // V_FLAG
2969 if constexpr (T::IS_R800) {
2970 f |= getF() & (X_FLAG | Y_FLAG);
2971 } else {
2972 f |= reg & (X_FLAG | Y_FLAG); // XY from operand, not from result
2973 }
2974 setF(f);
2975}
2976template<typename T> II CPUCore<T>::cp_a() {
2977 byte f = ZS0 | N_FLAG;
2978 if constexpr (T::IS_R800) {
2979 f |= getF() & (X_FLAG | Y_FLAG);
2980 } else {
2981 f |= getA() & (X_FLAG | Y_FLAG); // XY from operand, not from result
2982 }
2983 setF(f);
2984 return {1, T::CC_CP_R};
2985}
2986template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::cp_R() {
2987 CP(get8<SRC>()); return {1, T::CC_CP_R + EE};
2988}
2989template<typename T> II CPUCore<T>::cp_byte() {
2990 CP(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
2991}
2992template<typename T> II CPUCore<T>::cp_xhl() {
2993 CP(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
2994}
2995template<typename T> template<Reg16 IXY> II CPUCore<T>::cp_xix() {
2996 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
2997 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2998 T::setMemPtr(addr);
2999 CP(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3000 return {2, T::CC_DD + T::CC_CP_XIX};
3001}
3002
3003// OR r
3004template<typename T> inline void CPUCore<T>::OR(byte reg) {
3005 setA(getA() | reg);
3006 byte f = 0;
3007 if constexpr (T::IS_R800) {
3008 f |= table.ZSP[getA()];
3009 f |= getF() & (X_FLAG | Y_FLAG);
3010 } else {
3011 f |= table.ZSPXY[getA()];
3012 }
3013 setF(f);
3014}
3015template<typename T> II CPUCore<T>::or_a() {
3016 byte f = 0;
3017 if constexpr (T::IS_R800) {
3018 f |= table.ZSP[getA()];
3019 f |= getF() & (X_FLAG | Y_FLAG);
3020 } else {
3021 f |= table.ZSPXY[getA()];
3022 }
3023 setF(f);
3024 return {1, T::CC_CP_R};
3025}
3026template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::or_R() {
3027 OR(get8<SRC>()); return {1, T::CC_CP_R + EE};
3028}
3029template<typename T> II CPUCore<T>::or_byte() {
3030 OR(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3031}
3032template<typename T> II CPUCore<T>::or_xhl() {
3033 OR(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3034}
3035template<typename T> template<Reg16 IXY> II CPUCore<T>::or_xix() {
3036 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3037 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3038 T::setMemPtr(addr);
3039 OR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3040 return {2, T::CC_DD + T::CC_CP_XIX};
3041}
3042
3043// SBC A,r
3044template<typename T> inline void CPUCore<T>::SBC(byte reg) {
3045 unsigned res = getA() - reg - ((getF() & C_FLAG) ? 1 : 0);
3046 byte f = ((res & 0x100) ? C_FLAG : 0) |
3047 N_FLAG |
3048 ((getA() ^ res ^ reg) & H_FLAG) |
3049 (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3050 if constexpr (T::IS_R800) {
3051 f |= table.ZS[res & 0xFF];
3052 f |= getF() & (X_FLAG | Y_FLAG);
3053 } else {
3054 f |= table.ZSXY[res & 0xFF];
3055 }
3056 setF(f);
3057 setA(res);
3058}
3059template<typename T> II CPUCore<T>::sbc_a_a() {
3060 if constexpr (T::IS_R800) {
3061 word t = (getF() & C_FLAG)
3062 ? (255 * 256 | ZS255 | C_FLAG | H_FLAG | N_FLAG)
3063 : ( 0 * 256 | ZS0 | N_FLAG);
3064 setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3065 } else {
3066 setAF((getF() & C_FLAG) ?
3067 (255 * 256 | ZSXY255 | C_FLAG | H_FLAG | N_FLAG) :
3068 ( 0 * 256 | ZSXY0 | N_FLAG));
3069 }
3070 return {1, T::CC_CP_R};
3071}
3072template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::sbc_a_R() {
3073 SBC(get8<SRC>()); return {1, T::CC_CP_R + EE};
3074}
3075template<typename T> II CPUCore<T>::sbc_a_byte() {
3076 SBC(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3077}
3078template<typename T> II CPUCore<T>::sbc_a_xhl() {
3079 SBC(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3080}
3081template<typename T> template<Reg16 IXY> II CPUCore<T>::sbc_a_xix() {
3082 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3083 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3084 T::setMemPtr(addr);
3085 SBC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3086 return {2, T::CC_DD + T::CC_CP_XIX};
3087}
3088
3089// SUB r
3090template<typename T> inline void CPUCore<T>::SUB(byte reg) {
3091 unsigned res = getA() - reg;
3092 byte f = ((res & 0x100) ? C_FLAG : 0) |
3093 N_FLAG |
3094 ((getA() ^ res ^ reg) & H_FLAG) |
3095 (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3096 if constexpr (T::IS_R800) {
3097 f |= table.ZS[res & 0xFF];
3098 f |= getF() & (X_FLAG | Y_FLAG);
3099 } else {
3100 f |= table.ZSXY[res & 0xFF];
3101 }
3102 setF(f);
3103 setA(res);
3104}
3105template<typename T> II CPUCore<T>::sub_a() {
3106 if constexpr (T::IS_R800) {
3107 word t = 0 * 256 | ZS0 | N_FLAG;
3108 setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3109 } else {
3110 setAF(0 * 256 | ZSXY0 | N_FLAG);
3111 }
3112 return {1, T::CC_CP_R};
3113}
3114template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::sub_R() {
3115 SUB(get8<SRC>()); return {1, T::CC_CP_R + EE};
3116}
3117template<typename T> II CPUCore<T>::sub_byte() {
3118 SUB(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3119}
3120template<typename T> II CPUCore<T>::sub_xhl() {
3121 SUB(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3122}
3123template<typename T> template<Reg16 IXY> II CPUCore<T>::sub_xix() {
3124 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3125 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3126 T::setMemPtr(addr);
3127 SUB(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3128 return {2, T::CC_DD + T::CC_CP_XIX};
3129}
3130
3131// XOR r
3132template<typename T> inline void CPUCore<T>::XOR(byte reg) {
3133 setA(getA() ^ reg);
3134 byte f = 0;
3135 if constexpr (T::IS_R800) {
3136 f |= table.ZSP[getA()];
3137 f |= getF() & (X_FLAG | Y_FLAG);
3138 } else {
3139 f |= table.ZSPXY[getA()];
3140 }
3141 setF(f);
3142}
3143template<typename T> II CPUCore<T>::xor_a() {
3144 if constexpr (T::IS_R800) {
3145 word t = 0 * 256 + ZSP0;
3146 setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3147 } else {
3148 setAF(0 * 256 + ZSPXY0);
3149 }
3150 return {1, T::CC_CP_R};
3151}
3152template<typename T> template<Reg8 SRC, int EE> II CPUCore<T>::xor_R() {
3153 XOR(get8<SRC>()); return {1, T::CC_CP_R + EE};
3154}
3155template<typename T> II CPUCore<T>::xor_byte() {
3156 XOR(RDMEM_OPCODE<1>(T::CC_CP_N_1)); return {2, T::CC_CP_N};
3157}
3158template<typename T> II CPUCore<T>::xor_xhl() {
3159 XOR(RDMEM(getHL(), T::CC_CP_XHL_1)); return {1, T::CC_CP_XHL};
3160}
3161template<typename T> template<Reg16 IXY> II CPUCore<T>::xor_xix() {
3162 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_CP_XIX_1);
3163 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3164 T::setMemPtr(addr);
3165 XOR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3166 return {2, T::CC_DD + T::CC_CP_XIX};
3167}
3168
3169
3170// DEC r
3171template<typename T> inline byte CPUCore<T>::DEC(byte reg) {
3172 byte res = reg - 1;
3173 byte f = ((reg & ~res & 0x80) >> 5) | // V_FLAG
3174 (((res & 0x0F) + 1) & H_FLAG) |
3175 N_FLAG;
3176 if constexpr (T::IS_R800) {
3177 f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3178 f |= table.ZS[res];
3179 } else {
3180 f |= getF() & C_FLAG;
3181 f |= table.ZSXY[res];
3182 }
3183 setF(f);
3184 return res;
3185}
3186template<typename T> template<Reg8 REG, int EE> II CPUCore<T>::dec_R() {
3187 set8<REG>(DEC(get8<REG>())); return {1, T::CC_INC_R + EE};
3188}
3189template<typename T> template<int EE> inline void CPUCore<T>::DEC_X(unsigned x) {
3190 byte val = DEC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3191 WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3192}
3193template<typename T> II CPUCore<T>::dec_xhl() {
3194 DEC_X<0>(getHL());
3195 return {1, T::CC_INC_XHL};
3196}
3197template<typename T> template<Reg16 IXY> II CPUCore<T>::dec_xix() {
3198 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_INC_XIX_1);
3199 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3200 T::setMemPtr(addr);
3201 DEC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3202 return {2, T::CC_INC_XHL + T::CC_DD + T::EE_INC_XIX};
3203}
3204
3205// INC r
3206template<typename T> inline byte CPUCore<T>::INC(byte reg) {
3207 reg++;
3208 byte f = ((reg & -reg & 0x80) >> 5) | // V_FLAG
3209 (((reg & 0x0F) - 1) & H_FLAG) |
3210 0; // N_FLAG
3211 if constexpr (T::IS_R800) {
3212 f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3213 f |= table.ZS[reg];
3214 } else {
3215 f |= getF() & C_FLAG;
3216 f |= table.ZSXY[reg];
3217 }
3218 setF(f);
3219 return reg;
3220}
3221template<typename T> template<Reg8 REG, int EE> II CPUCore<T>::inc_R() {
3222 set8<REG>(INC(get8<REG>())); return {1, T::CC_INC_R + EE};
3223}
3224template<typename T> template<int EE> inline void CPUCore<T>::INC_X(unsigned x) {
3225 byte val = INC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3226 WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3227}
3228template<typename T> II CPUCore<T>::inc_xhl() {
3229 INC_X<0>(getHL());
3230 return {1, T::CC_INC_XHL};
3231}
3232template<typename T> template<Reg16 IXY> II CPUCore<T>::inc_xix() {
3233 int8_t ofst = RDMEM_OPCODE<1>(T::CC_DD + T::CC_INC_XIX_1);
3234 unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3235 T::setMemPtr(addr);
3236 INC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3237 return {2, T::CC_INC_XHL + T::CC_DD + T::EE_INC_XIX};
3238}
3239
3240
3241// ADC HL,ss
3242template<typename T> template<Reg16 REG> inline II CPUCore<T>::adc_hl_SS() {
3243 unsigned reg = get16<REG>();
3244 T::setMemPtr(getHL() + 1);
3245 unsigned res = getHL() + reg + ((getF() & C_FLAG) ? 1 : 0);
3246 byte f = (res >> 16) | // C_FLAG
3247 0; // N_FLAG
3248 if constexpr (T::IS_R800) {
3249 f |= getF() & (X_FLAG | Y_FLAG);
3250 }
3251 if (res & 0xFFFF) {
3252 f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3253 f |= 0; // Z_FLAG
3254 f |= ((getHL() ^ res) & (reg ^ res) & 0x8000) >> 13; // V_FLAG
3255 if constexpr (T::IS_R800) {
3256 f |= (res >> 8) & S_FLAG;
3257 } else {
3258 f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3259 }
3260 } else {
3261 f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3262 f |= Z_FLAG;
3263 f |= (getHL() & reg & 0x8000) >> 13; // V_FLAG
3264 f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3265 }
3266 setF(f);
3267 setHL(res);
3268 return {1, T::CC_ADC_HL_SS};
3269}
3270template<typename T> II CPUCore<T>::adc_hl_hl() {
3271 T::setMemPtr(getHL() + 1);
3272 unsigned res = 2 * getHL() + ((getF() & C_FLAG) ? 1 : 0);
3273 byte f = (res >> 16) | // C_FLAG
3274 0; // N_FLAG
3275 if constexpr (T::IS_R800) {
3276 f |= getF() & (X_FLAG | Y_FLAG);
3277 }
3278 if (res & 0xFFFF) {
3279 f |= 0; // Z_FLAG
3280 f |= ((getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3281 if constexpr (T::IS_R800) {
3282 f |= (res >> 8) & (H_FLAG | S_FLAG);
3283 } else {
3284 f |= (res >> 8) & (H_FLAG | S_FLAG | X_FLAG | Y_FLAG);
3285 }
3286 } else {
3287 f |= Z_FLAG;
3288 f |= (getHL() & 0x8000) >> 13; // V_FLAG
3289 f |= 0; // H_FLAG S_FLAG (X_FLAG Y_FLAG)
3290 }
3291 setF(f);
3292 setHL(res);
3293 return {1, T::CC_ADC_HL_SS};
3294}
3295
3296// ADD HL/IX/IY,ss
3297template<typename T> template<Reg16 REG1, Reg16 REG2, int EE> II CPUCore<T>::add_SS_TT() {
3298 unsigned reg1 = get16<REG1>();
3299 unsigned reg2 = get16<REG2>();
3300 T::setMemPtr(reg1 + 1);
3301 unsigned res = reg1 + reg2;
3302 byte f = (((reg1 ^ res ^ reg2) >> 8) & H_FLAG) |
3303 (res >> 16) | // C_FLAG
3304 0; // N_FLAG
3305 if constexpr (T::IS_R800) {
3306 f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3307 } else {
3308 f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3309 f |= (res >> 8) & (X_FLAG | Y_FLAG);
3310 }
3311 setF(f);
3312 set16<REG1>(res & 0xFFFF);
3313 return {1, T::CC_ADD_HL_SS + EE};
3314}
3315template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::add_SS_SS() {
3316 unsigned reg = get16<REG>();
3317 T::setMemPtr(reg + 1);
3318 unsigned res = 2 * reg;
3319 byte f = (res >> 16) | // C_FLAG
3320 0; // N_FLAG
3321 if constexpr (T::IS_R800) {
3322 f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3323 f |= (res >> 8) & H_FLAG;
3324 } else {
3325 f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3326 f |= (res >> 8) & (H_FLAG | X_FLAG | Y_FLAG);
3327 }
3328 setF(f);
3329 set16<REG>(res & 0xFFFF);
3330 return {1, T::CC_ADD_HL_SS + EE};
3331}
3332
3333// SBC HL,ss
3334template<typename T> template<Reg16 REG> inline II CPUCore<T>::sbc_hl_SS() {
3335 unsigned reg = get16<REG>();
3336 T::setMemPtr(getHL() + 1);
3337 unsigned res = getHL() - reg - ((getF() & C_FLAG) ? 1 : 0);
3338 byte f = ((res & 0x10000) ? C_FLAG : 0) |
3339 N_FLAG;
3340 if constexpr (T::IS_R800) {
3341 f |= getF() & (X_FLAG | Y_FLAG);
3342 }
3343 if (res & 0xFFFF) {
3344 f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3345 f |= 0; // Z_FLAG
3346 f |= ((reg ^ getHL()) & (getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3347 if constexpr (T::IS_R800) {
3348 f |= (res >> 8) & S_FLAG;
3349 } else {
3350 f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3351 }
3352 } else {
3353 f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3354 f |= Z_FLAG;
3355 f |= ((reg ^ getHL()) & getHL() & 0x8000) >> 13; // V_FLAG
3356 f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3357 }
3358 setF(f);
3359 setHL(res);
3360 return {1, T::CC_ADC_HL_SS};
3361}
3362template<typename T> II CPUCore<T>::sbc_hl_hl() {
3363 T::setMemPtr(getHL() + 1);
3364 byte f = T::IS_R800 ? (getF() & (X_FLAG | Y_FLAG)) : 0;
3365 if (getF() & C_FLAG) {
3366 f |= C_FLAG | H_FLAG | S_FLAG | N_FLAG;
3367 if constexpr (!T::IS_R800) {
3368 f |= X_FLAG | Y_FLAG;
3369 }
3370 setHL(0xFFFF);
3371 } else {
3372 f |= Z_FLAG | N_FLAG;
3373 setHL(0);
3374 }
3375 setF(f);
3376 return {1, T::CC_ADC_HL_SS};
3377}
3378
3379// DEC ss
3380template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::dec_SS() {
3381 set16<REG>(get16<REG>() - 1); return {1, T::CC_INC_SS + EE};
3382}
3383
3384// INC ss
3385template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::inc_SS() {
3386 set16<REG>(get16<REG>() + 1); return {1, T::CC_INC_SS + EE};
3387}
3388
3389
3390// BIT n,r
3391template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::bit_N_R() {
3392 byte reg = get8<REG>();
3393 byte f = 0; // N_FLAG
3394 if constexpr (T::IS_R800) {
3395 // this is very different from Z80 (not only XY flags)
3396 f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3397 f |= H_FLAG;
3398 f |= (reg & (1 << N)) ? 0 : Z_FLAG;
3399 } else {
3400 f |= table.ZSPH[reg & (1 << N)];
3401 f |= getF() & C_FLAG;
3402 f |= reg & (X_FLAG | Y_FLAG);
3403 }
3404 setF(f);
3405 return {1, T::CC_BIT_R};
3406}
3407template<typename T> template<unsigned N> inline II CPUCore<T>::bit_N_xhl() {
3408 byte m = RDMEM(getHL(), T::CC_BIT_XHL_1) & (1 << N);
3409 byte f = 0; // N_FLAG
3410 if constexpr (T::IS_R800) {
3411 f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3412 f |= H_FLAG;
3413 f |= m ? 0 : Z_FLAG;
3414 } else {
3415 f |= table.ZSPH[m];
3416 f |= getF() & C_FLAG;
3417 f |= (T::getMemPtr() >> 8) & (X_FLAG | Y_FLAG);
3418 }
3419 setF(f);
3420 return {1, T::CC_BIT_XHL};
3421}
3422template<typename T> template<unsigned N> inline II CPUCore<T>::bit_N_xix(unsigned addr) {
3423 T::setMemPtr(addr);
3424 byte m = RDMEM(addr, T::CC_DD + T::CC_BIT_XIX_1) & (1 << N);
3425 byte f = 0; // N_FLAG
3426 if constexpr (T::IS_R800) {
3427 f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3428 f |= H_FLAG;
3429 f |= m ? 0 : Z_FLAG;
3430 } else {
3431 f |= table.ZSPH[m];
3432 f |= getF() & C_FLAG;
3433 f |= (addr >> 8) & (X_FLAG | Y_FLAG);
3434 }
3435 setF(f);
3436 return {3, T::CC_DD + T::CC_BIT_XIX};
3437}
3438
3439// RES n,r
3440static constexpr byte RES(unsigned b, byte reg) {
3441 return reg & ~(1 << b);
3442}
3443template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::res_N_R() {
3444 set8<REG>(RES(N, get8<REG>())); return {1, T::CC_SET_R};
3445}
3446template<typename T> template<int EE> inline byte CPUCore<T>::RES_X(unsigned bit, unsigned addr) {
3447 byte res = RES(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3448 WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3449 return res;
3450}
3451template<typename T> template<unsigned N> II CPUCore<T>::res_N_xhl() {
3452 RES_X<0>(N, getHL()); return {1, T::CC_SET_XHL};
3453}
3454template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::res_N_xix_R(unsigned a) {
3455 T::setMemPtr(a);
3456 set8<REG>(RES_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3457 return {3, T::CC_DD + T::CC_SET_XIX};
3458}
3459
3460// SET n,r
3461static constexpr byte SET(unsigned b, byte reg) {
3462 return reg | (1 << b);
3463}
3464template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::set_N_R() {
3465 set8<REG>(SET(N, get8<REG>())); return {1, T::CC_SET_R};
3466}
3467template<typename T> template<int EE> inline byte CPUCore<T>::SET_X(unsigned bit, unsigned addr) {
3468 byte res = SET(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3469 WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3470 return res;
3471}
3472template<typename T> template<unsigned N> II CPUCore<T>::set_N_xhl() {
3473 SET_X<0>(N, getHL()); return {1, T::CC_SET_XHL};
3474}
3475template<typename T> template<unsigned N, Reg8 REG> II CPUCore<T>::set_N_xix_R(unsigned a) {
3476 T::setMemPtr(a);
3477 set8<REG>(SET_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3478 return {3, T::CC_DD + T::CC_SET_XIX};
3479}
3480
3481// RL r
3482template<typename T> inline byte CPUCore<T>::RL(byte reg) {
3483 byte c = reg >> 7;
3484 reg = (reg << 1) | ((getF() & C_FLAG) ? 0x01 : 0);
3485 byte f = c ? C_FLAG : 0;
3486 if constexpr (T::IS_R800) {
3487 f |= table.ZSP[reg];
3488 f |= getF() & (X_FLAG | Y_FLAG);
3489 } else {
3490 f |= table.ZSPXY[reg];
3491 }
3492 setF(f);
3493 return reg;
3494}
3495template<typename T> template<int EE> inline byte CPUCore<T>::RL_X(unsigned x) {
3496 byte res = RL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3497 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3498 return res;
3499}
3500template<typename T> template<Reg8 REG> II CPUCore<T>::rl_R() {
3501 set8<REG>(RL(get8<REG>())); return {1, T::CC_SET_R};
3502}
3503template<typename T> II CPUCore<T>::rl_xhl() {
3504 RL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3505}
3506template<typename T> template<Reg8 REG> II CPUCore<T>::rl_xix_R(unsigned a) {
3507 T::setMemPtr(a);
3508 set8<REG>(RL_X<T::CC_DD + T::EE_SET_XIX>(a));
3509 return {3, T::CC_DD + T::CC_SET_XIX};
3510}
3511
3512// RLC r
3513template<typename T> inline byte CPUCore<T>::RLC(byte reg) {
3514 byte c = reg >> 7;
3515 reg = (reg << 1) | c;
3516 byte f = c ? C_FLAG : 0;
3517 if constexpr (T::IS_R800) {
3518 f |= table.ZSP[reg];
3519 f |= getF() & (X_FLAG | Y_FLAG);
3520 } else {
3521 f |= table.ZSPXY[reg];
3522 }
3523 setF(f);
3524 return reg;
3525}
3526template<typename T> template<int EE> inline byte CPUCore<T>::RLC_X(unsigned x) {
3527 byte res = RLC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3528 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3529 return res;
3530}
3531template<typename T> template<Reg8 REG> II CPUCore<T>::rlc_R() {
3532 set8<REG>(RLC(get8<REG>())); return {1, T::CC_SET_R};
3533}
3534template<typename T> II CPUCore<T>::rlc_xhl() {
3535 RLC_X<0>(getHL()); return {1, T::CC_SET_XHL};
3536}
3537template<typename T> template<Reg8 REG> II CPUCore<T>::rlc_xix_R(unsigned a) {
3538 T::setMemPtr(a);
3539 set8<REG>(RLC_X<T::CC_DD + T::EE_SET_XIX>(a));
3540 return {3, T::CC_DD + T::CC_SET_XIX};
3541}
3542
3543// RR r
3544template<typename T> inline byte CPUCore<T>::RR(byte reg) {
3545 byte c = reg & 1;
3546 reg = (reg >> 1) | ((getF() & C_FLAG) << 7);
3547 byte f = c ? C_FLAG : 0;
3548 if constexpr (T::IS_R800) {
3549 f |= table.ZSP[reg];
3550 f |= getF() & (X_FLAG | Y_FLAG);
3551 } else {
3552 f |= table.ZSPXY[reg];
3553 }
3554 setF(f);
3555 return reg;
3556}
3557template<typename T> template<int EE> inline byte CPUCore<T>::RR_X(unsigned x) {
3558 byte res = RR(RDMEM(x, T::CC_SET_XHL_1 + EE));
3559 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3560 return res;
3561}
3562template<typename T> template<Reg8 REG> II CPUCore<T>::rr_R() {
3563 set8<REG>(RR(get8<REG>())); return {1, T::CC_SET_R};
3564}
3565template<typename T> II CPUCore<T>::rr_xhl() {
3566 RR_X<0>(getHL()); return {1, T::CC_SET_XHL};
3567}
3568template<typename T> template<Reg8 REG> II CPUCore<T>::rr_xix_R(unsigned a) {
3569 T::setMemPtr(a);
3570 set8<REG>(RR_X<T::CC_DD + T::EE_SET_XIX>(a));
3571 return {3, T::CC_DD + T::CC_SET_XIX};
3572}
3573
3574// RRC r
3575template<typename T> inline byte CPUCore<T>::RRC(byte reg) {
3576 byte c = reg & 1;
3577 reg = (reg >> 1) | (c << 7);
3578 byte f = c ? C_FLAG : 0;
3579 if constexpr (T::IS_R800) {
3580 f |= table.ZSP[reg];
3581 f |= getF() & (X_FLAG | Y_FLAG);
3582 } else {
3583 f |= table.ZSPXY[reg];
3584 }
3585 setF(f);
3586 return reg;
3587}
3588template<typename T> template<int EE> inline byte CPUCore<T>::RRC_X(unsigned x) {
3589 byte res = RRC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3590 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3591 return res;
3592}
3593template<typename T> template<Reg8 REG> II CPUCore<T>::rrc_R() {
3594 set8<REG>(RRC(get8<REG>())); return {1, T::CC_SET_R};
3595}
3596template<typename T> II CPUCore<T>::rrc_xhl() {
3597 RRC_X<0>(getHL()); return {1, T::CC_SET_XHL};
3598}
3599template<typename T> template<Reg8 REG> II CPUCore<T>::rrc_xix_R(unsigned a) {
3600 T::setMemPtr(a);
3601 set8<REG>(RRC_X<T::CC_DD + T::EE_SET_XIX>(a));
3602 return {3, T::CC_DD + T::CC_SET_XIX};
3603}
3604
3605// SLA r
3606template<typename T> inline byte CPUCore<T>::SLA(byte reg) {
3607 byte c = reg >> 7;
3608 reg <<= 1;
3609 byte f = c ? C_FLAG : 0;
3610 if constexpr (T::IS_R800) {
3611 f |= table.ZSP[reg];
3612 f |= getF() & (X_FLAG | Y_FLAG);
3613 } else {
3614 f |= table.ZSPXY[reg];
3615 }
3616 setF(f);
3617 return reg;
3618}
3619template<typename T> template<int EE> inline byte CPUCore<T>::SLA_X(unsigned x) {
3620 byte res = SLA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3621 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3622 return res;
3623}
3624template<typename T> template<Reg8 REG> II CPUCore<T>::sla_R() {
3625 set8<REG>(SLA(get8<REG>())); return {1, T::CC_SET_R};
3626}
3627template<typename T> II CPUCore<T>::sla_xhl() {
3628 SLA_X<0>(getHL()); return {1, T::CC_SET_XHL};
3629}
3630template<typename T> template<Reg8 REG> II CPUCore<T>::sla_xix_R(unsigned a) {
3631 T::setMemPtr(a);
3632 set8<REG>(SLA_X<T::CC_DD + T::EE_SET_XIX>(a));
3633 return {3, T::CC_DD + T::CC_SET_XIX};
3634}
3635
3636// SLL r
3637template<typename T> inline byte CPUCore<T>::SLL(byte reg) {
3638 assert(!T::IS_R800); // this instruction is Z80-only
3639 byte c = reg >> 7;
3640 reg = (reg << 1) | 1;
3641 byte f = c ? C_FLAG : 0;
3642 f |= table.ZSPXY[reg];
3643 setF(f);
3644 return reg;
3645}
3646template<typename T> template<int EE> inline byte CPUCore<T>::SLL_X(unsigned x) {
3647 byte res = SLL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3648 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3649 return res;
3650}
3651template<typename T> template<Reg8 REG> II CPUCore<T>::sll_R() {
3652 set8<REG>(SLL(get8<REG>())); return {1, T::CC_SET_R};
3653}
3654template<typename T> II CPUCore<T>::sll_xhl() {
3655 SLL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3656}
3657template<typename T> template<Reg8 REG> II CPUCore<T>::sll_xix_R(unsigned a) {
3658 T::setMemPtr(a);
3659 set8<REG>(SLL_X<T::CC_DD + T::EE_SET_XIX>(a));
3660 return {3, T::CC_DD + T::CC_SET_XIX};
3661}
3662template<typename T> II CPUCore<T>::sll2() {
3663 assert(T::IS_R800); // this instruction is R800-only
3664 byte f = (getF() & (X_FLAG | Y_FLAG)) |
3665 (getA() >> 7) | // C_FLAG
3666 0; // all other flags zero
3667 setF(f);
3668 return {3, T::CC_DD + T::CC_SET_XIX}; // TODO
3669}
3670
3671// SRA r
3672template<typename T> inline byte CPUCore<T>::SRA(byte reg) {
3673 byte c = reg & 1;
3674 reg = (reg >> 1) | (reg & 0x80);
3675 byte f = c ? C_FLAG : 0;
3676 if constexpr (T::IS_R800) {
3677 f |= table.ZSP[reg];
3678 f |= getF() & (X_FLAG | Y_FLAG);
3679 } else {
3680 f |= table.ZSPXY[reg];
3681 }
3682 setF(f);
3683 return reg;
3684}
3685template<typename T> template<int EE> inline byte CPUCore<T>::SRA_X(unsigned x) {
3686 byte res = SRA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3687 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3688 return res;
3689}
3690template<typename T> template<Reg8 REG> II CPUCore<T>::sra_R() {
3691 set8<REG>(SRA(get8<REG>())); return {1, T::CC_SET_R};
3692}
3693template<typename T> II CPUCore<T>::sra_xhl() {
3694 SRA_X<0>(getHL()); return {1, T::CC_SET_XHL};
3695}
3696template<typename T> template<Reg8 REG> II CPUCore<T>::sra_xix_R(unsigned a) {
3697 T::setMemPtr(a);
3698 set8<REG>(SRA_X<T::CC_DD + T::EE_SET_XIX>(a));
3699 return {3, T::CC_DD + T::CC_SET_XIX};
3700}
3701
3702// SRL R
3703template<typename T> inline byte CPUCore<T>::SRL(byte reg) {
3704 byte c = reg & 1;
3705 reg >>= 1;
3706 byte f = c ? C_FLAG : 0;
3707 if constexpr (T::IS_R800) {
3708 f |= table.ZSP[reg];
3709 f |= getF() & (X_FLAG | Y_FLAG);
3710 } else {
3711 f |= table.ZSPXY[reg];
3712 }
3713 setF(f);
3714 return reg;
3715}
3716template<typename T> template<int EE> inline byte CPUCore<T>::SRL_X(unsigned x) {
3717 byte res = SRL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3718 WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3719 return res;
3720}
3721template<typename T> template<Reg8 REG> II CPUCore<T>::srl_R() {
3722 set8<REG>(SRL(get8<REG>())); return {1, T::CC_SET_R};
3723}
3724template<typename T> II CPUCore<T>::srl_xhl() {
3725 SRL_X<0>(getHL()); return {1, T::CC_SET_XHL};
3726}
3727template<typename T> template<Reg8 REG> II CPUCore<T>::srl_xix_R(unsigned a) {
3728 T::setMemPtr(a);
3729 set8<REG>(SRL_X<T::CC_DD + T::EE_SET_XIX>(a));
3730 return {3, T::CC_DD + T::CC_SET_XIX};
3731}
3732
3733// RLA RLCA RRA RRCA
3734template<typename T> II CPUCore<T>::rla() {
3735 byte c = getF() & C_FLAG;
3736 byte f = (getA() & 0x80) ? C_FLAG : 0;
3737 if constexpr (T::IS_R800) {
3738 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3739 } else {
3740 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3741 }
3742 setA((getA() << 1) | (c ? 1 : 0));
3743 if constexpr (!T::IS_R800) {
3744 f |= getA() & (X_FLAG | Y_FLAG);
3745 }
3746 setF(f);
3747 return {1, T::CC_RLA};
3748}
3749template<typename T> II CPUCore<T>::rlca() {
3750 setA((getA() << 1) | (getA() >> 7));
3751 byte f = 0;
3752 if constexpr (T::IS_R800) {
3753 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3754 f |= getA() & C_FLAG;
3755 } else {
3756 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3757 f |= getA() & (Y_FLAG | X_FLAG | C_FLAG);
3758 }
3759 setF(f);
3760 return {1, T::CC_RLA};
3761}
3762template<typename T> II CPUCore<T>::rra() {
3763 byte c = (getF() & C_FLAG) << 7;
3764 byte f = (getA() & 0x01) ? C_FLAG : 0;
3765 if constexpr (T::IS_R800) {
3766 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3767 } else {
3768 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3769 }
3770 setA((getA() >> 1) | c);
3771 if constexpr (!T::IS_R800) {
3772 f |= getA() & (X_FLAG | Y_FLAG);
3773 }
3774 setF(f);
3775 return {1, T::CC_RLA};
3776}
3777template<typename T> II CPUCore<T>::rrca() {
3778 byte f = getA() & C_FLAG;
3779 if constexpr (T::IS_R800) {
3780 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3781 } else {
3782 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3783 }
3784 setA((getA() >> 1) | (getA() << 7));
3785 if constexpr (!T::IS_R800) {
3786 f |= getA() & (X_FLAG | Y_FLAG);
3787 }
3788 setF(f);
3789 return {1, T::CC_RLA};
3790}
3791
3792
3793// RLD
3794template<typename T> II CPUCore<T>::rld() {
3795 byte val = RDMEM(getHL(), T::CC_RLD_1);
3796 T::setMemPtr(getHL() + 1);
3797 WRMEM(getHL(), (val << 4) | (getA() & 0x0F), T::CC_RLD_2);
3798 setA((getA() & 0xF0) | (val >> 4));
3799 byte f = 0;
3800 if constexpr (T::IS_R800) {
3801 f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3802 f |= table.ZSP[getA()];
3803 } else {
3804 f |= getF() & C_FLAG;
3805 f |= table.ZSPXY[getA()];
3806 }
3807 setF(f);
3808 return {1, T::CC_RLD};
3809}
3810
3811// RRD
3812template<typename T> II CPUCore<T>::rrd() {
3813 byte val = RDMEM(getHL(), T::CC_RLD_1);
3814 T::setMemPtr(getHL() + 1);
3815 WRMEM(getHL(), (val >> 4) | (getA() << 4), T::CC_RLD_2);
3816 setA((getA() & 0xF0) | (val & 0x0F));
3817 byte f = 0;
3818 if constexpr (T::IS_R800) {
3819 f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3820 f |= table.ZSP[getA()];
3821 } else {
3822 f |= getF() & C_FLAG;
3823 f |= table.ZSPXY[getA()];
3824 }
3825 setF(f);
3826 return {1, T::CC_RLD};
3827}
3828
3829
3830// PUSH ss
3831template<typename T> template<int EE> inline void CPUCore<T>::PUSH(unsigned reg) {
3832 setSP(getSP() - 2);
3833 WR_WORD_rev<true, true>(getSP(), reg, T::CC_PUSH_1 + EE);
3834}
3835template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::push_SS() {
3836 PUSH<EE>(get16<REG>()); return {1, T::CC_PUSH + EE};
3837}
3838
3839// POP ss
3840template<typename T> template<int EE> inline unsigned CPUCore<T>::POP() {
3841 unsigned addr = getSP();
3842 setSP(addr + 2);
3843 if constexpr (T::IS_R800) {
3844 // handles both POP and RET instructions (RET with condition = true)
3845 if constexpr (EE == 0) { // not reti/retn, not pop ix/iy
3846 setCurrentPopRet();
3847 // No need for setSlowInstructions()
3848 // -> this only matters directly after a CALL
3849 // instruction and in that case we're still
3850 // executing slow instructions.
3851 }
3852 }
3853 return RD_WORD(addr, T::CC_POP_1 + EE);
3854}
3855template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::pop_SS() {
3856 set16<REG>(POP<EE>()); return {1, T::CC_POP + EE};
3857}
3858
3859
3860// CALL nn / CALL cc,nn
3861template<typename T> template<typename COND> II CPUCore<T>::call(COND cond) {
3862 unsigned addr = RD_WORD_PC<1>(T::CC_CALL_1);
3863 T::setMemPtr(addr);
3864 if (cond(getF())) {
3865 PUSH<T::EE_CALL>(getPC() + 3);
3866 setPC(addr);
3867 if constexpr (T::IS_R800) {
3868 setCurrentCall();
3869 setSlowInstructions();
3870 }
3871 return {0/*3*/, T::CC_CALL_A};
3872 } else {
3873 return {3, T::CC_CALL_B};
3874 }
3875}
3876
3877
3878// RST n
3879template<typename T> template<unsigned ADDR> II CPUCore<T>::rst() {
3880 PUSH<0>(getPC() + 1);
3881 T::setMemPtr(ADDR);
3882 setPC(ADDR);
3883 if constexpr (T::IS_R800) {
3884 setCurrentCall();
3885 setSlowInstructions();
3886 }
3887 return {0/*1*/, T::CC_RST};
3888}
3889
3890
3891// RET
3892template<typename T> template<int EE, typename COND> inline II CPUCore<T>::RET(COND cond) {
3893 if (cond(getF())) {
3894 unsigned addr = POP<EE>();
3895 T::setMemPtr(addr);
3896 setPC(addr);
3897 return {0/*1*/, T::CC_RET_A + EE};
3898 } else {
3899 return {1, T::CC_RET_B + EE};
3900 }
3901}
3902template<typename T> template<typename COND> II CPUCore<T>::ret(COND cond) {
3903 return RET<T::EE_RET_C>(cond);
3904}
3905template<typename T> II CPUCore<T>::ret() {
3906 return RET<0>(CondTrue());
3907}
3908template<typename T> II CPUCore<T>::retn() { // also reti
3909 setIFF1(getIFF2());
3910 setSlowInstructions();
3911 return RET<T::EE_RETN>(CondTrue());
3912}
3913
3914
3915// JP ss
3916template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::jp_SS() {
3917 setPC(get16<REG>()); T::R800ForcePageBreak(); return {0/*1*/, T::CC_JP_HL + EE};
3918}
3919
3920// JP nn / JP cc,nn
3921template<typename T> template<typename COND> II CPUCore<T>::jp(COND cond) {
3922 unsigned addr = RD_WORD_PC<1>(T::CC_JP_1);
3923 T::setMemPtr(addr);
3924 if (cond(getF())) {
3925 setPC(addr);
3926 T::R800ForcePageBreak();
3927 return {0/*3*/, T::CC_JP_A};
3928 } else {
3929 return {3, T::CC_JP_B};
3930 }
3931}
3932
3933// JR e
3934template<typename T> template<typename COND> II CPUCore<T>::jr(COND cond) {
3935 int8_t ofst = RDMEM_OPCODE<1>(T::CC_JR_1);
3936 if (cond(getF())) {
3937 if (((getPC() + 2) & 0xFF) == 0) {
3938 // On R800, when this instruction is located in the
3939 // last two byte of a page (a page is a 256-byte
3940 // (aligned) memory block) and even if we jump back,
3941 // thus fetching the next opcode byte does not cause a
3942 // page-break, there still is one cycle overhead. It's
3943 // as-if there is a page-break.
3944 //
3945 // This could be explained by some (very limited)
3946 // pipeline behaviour in R800: it seems that the
3947 // decision to cause a page-break on the next
3948 // instruction is already made before the jump
3949 // destination address for the current instruction is
3950 // calculated (though a destination address in another
3951 // page is also a reason for a page-break).
3952 //
3953 // It's likely all instructions behave like this, but I
3954 // think we can get away with only explicitly emulating
3955 // this behaviour in the djnz and the jr (conditional
3956 // or not) instructions: all other instructions that
3957 // cause the PC to change in a non-incremental way do
3958 // already force a pagebreak for another reason, so
3959 // this effect is masked. Examples of such instructions
3960 // are: JP, RET, CALL, RST, all repeated block
3961 // instructions, accepting an IRQ, (are there more
3962 // instructions or events that change PC?)
3963 //
3964 // See doc/r800-djnz.txt for more details.
3965 T::R800ForcePageBreak();
3966 }
3967 setPC((getPC() + 2 + ofst) & 0xFFFF);
3968 T::setMemPtr(getPC());
3969 return {0/*2*/, T::CC_JR_A};
3970 } else {
3971 return {2, T::CC_JR_B};
3972 }
3973}
3974
3975// DJNZ e
3976template<typename T> II CPUCore<T>::djnz() {
3977 byte b = getB() - 1;
3978 setB(b);
3979 int8_t ofst = RDMEM_OPCODE<1>(T::CC_JR_1 + T::EE_DJNZ);
3980 if (b) {
3981 if (((getPC() + 2) & 0xFF) == 0) {
3982 // See comment in jr()
3983 T::R800ForcePageBreak();
3984 }
3985 setPC((getPC() + 2 + ofst) & 0xFFFF);
3986 T::setMemPtr(getPC());
3987 return {0/*2*/, T::CC_JR_A + T::EE_DJNZ};
3988 } else {
3989 return {2, T::CC_JR_B + T::EE_DJNZ};
3990 }
3991}
3992
3993// EX (SP),ss
3994template<typename T> template<Reg16 REG, int EE> II CPUCore<T>::ex_xsp_SS() {
3995 unsigned res = RD_WORD_impl<true, false>(getSP(), T::CC_EX_SP_HL_1 + EE);
3996 T::setMemPtr(res);
3997 WR_WORD_rev<false, true>(getSP(), get16<REG>(), T::CC_EX_SP_HL_2 + EE);
3998 set16<REG>(res);
3999 return {1, T::CC_EX_SP_HL + EE};
4000}
4001
4002// IN r,(c)
4003template<typename T> template<Reg8 REG> II CPUCore<T>::in_R_c() {
4004 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_IN_R_C_1);
4005 T::setMemPtr(getBC() + 1);
4006 byte res = READ_PORT(getBC(), T::CC_IN_R_C_1);
4007 byte f = 0;
4008 if constexpr (T::IS_R800) {
4009 f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4010 f |= table.ZSP[res];
4011 } else {
4012 f |= getF() & C_FLAG;
4013 f |= table.ZSPXY[res];
4014 }
4015 setF(f);
4016 set8<REG>(res);
4017 return {1, T::CC_IN_R_C};
4018}
4019
4020// IN a,(n)
4021template<typename T> II CPUCore<T>::in_a_byte() {
4022 unsigned y = RDMEM_OPCODE<1>(T::CC_IN_A_N_1) + 256 * getA();
4023 T::setMemPtr(y + 1);
4024 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_IN_A_N_2);
4025 setA(READ_PORT(y, T::CC_IN_A_N_2));
4026 return {2, T::CC_IN_A_N};
4027}
4028
4029// OUT (c),r
4030template<typename T> template<Reg8 REG> II CPUCore<T>::out_c_R() {
4031 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4032 T::setMemPtr(getBC() + 1);
4033 WRITE_PORT(getBC(), get8<REG>(), T::CC_OUT_C_R_1);
4034 return {1, T::CC_OUT_C_R};
4035}
4036template<typename T> II CPUCore<T>::out_c_0() {
4037 // TODO not on R800
4038 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_OUT_C_R_1);
4039 T::setMemPtr(getBC() + 1);
4040 byte out_c_x = isCMOS ? 255 : 0;
4041 WRITE_PORT(getBC(), out_c_x, T::CC_OUT_C_R_1);
4042 return {1, T::CC_OUT_C_R};
4043}
4044
4045// OUT (n),a
4046template<typename T> II CPUCore<T>::out_byte_a() {
4047 byte port = RDMEM_OPCODE<1>(T::CC_OUT_N_A_1);
4048 unsigned y = (getA() << 8) | port;
4049 T::setMemPtr((getA() << 8) | ((port + 1) & 255));
4050 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_OUT_N_A_2);
4051 WRITE_PORT(y, getA(), T::CC_OUT_N_A_2);
4052 return {2, T::CC_OUT_N_A};
4053}
4054
4055
4056// block CP
4057template<typename T> inline II CPUCore<T>::BLOCK_CP(int increase, bool repeat) {
4058 T::setMemPtr(T::getMemPtr() + increase);
4059 byte val = RDMEM(getHL(), T::CC_CPI_1);
4060 byte res = getA() - val;
4061 setHL(getHL() + increase);
4062 setBC(getBC() - 1);
4063 byte f = ((getA() ^ val ^ res) & H_FLAG) |
4064 table.ZS[res] |
4065 N_FLAG |
4066 (getBC() ? V_FLAG : 0);
4067 if constexpr (T::IS_R800) {
4068 f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4069 } else {
4070 f |= getF() & C_FLAG;
4071 unsigned k = res - ((f & H_FLAG) >> 4);
4072 f |= (k << 4) & Y_FLAG; // bit 1 -> flag 5
4073 f |= k & X_FLAG; // bit 3 -> flag 3
4074 }
4075 setF(f);
4076 if (repeat && getBC() && res) {
4077 //setPC(getPC() - 2);
4078 T::setMemPtr(getPC() + 1);
4079 return {-1/*1*/, T::CC_CPIR};
4080 } else {
4081 return {1, T::CC_CPI};
4082 }
4083}
4084template<typename T> II CPUCore<T>::cpd() { return BLOCK_CP(-1, false); }
4085template<typename T> II CPUCore<T>::cpi() { return BLOCK_CP( 1, false); }
4086template<typename T> II CPUCore<T>::cpdr() { return BLOCK_CP(-1, true ); }
4087template<typename T> II CPUCore<T>::cpir() { return BLOCK_CP( 1, true ); }
4088
4089
4090// block LD
4091template<typename T> inline II CPUCore<T>::BLOCK_LD(int increase, bool repeat) {
4092 byte val = RDMEM(getHL(), T::CC_LDI_1);
4093 WRMEM(getDE(), val, T::CC_LDI_2);
4094 setHL(getHL() + increase);
4095 setDE(getDE() + increase);
4096 setBC(getBC() - 1);
4097 byte f = getBC() ? V_FLAG : 0;
4098 if constexpr (T::IS_R800) {
4099 f |= getF() & (S_FLAG | Z_FLAG | C_FLAG | X_FLAG | Y_FLAG);
4100 } else {
4101 f |= getF() & (S_FLAG | Z_FLAG | C_FLAG);
4102 f |= ((getA() + val) << 4) & Y_FLAG; // bit 1 -> flag 5
4103 f |= (getA() + val) & X_FLAG; // bit 3 -> flag 3
4104 }
4105 setF(f);
4106 if (repeat && getBC()) {
4107 //setPC(getPC() - 2);
4108 T::setMemPtr(getPC() + 1);
4109 return {-1/*1*/, T::CC_LDIR};
4110 } else {
4111 return {1, T::CC_LDI};
4112 }
4113}
4114template<typename T> II CPUCore<T>::ldd() { return BLOCK_LD(-1, false); }
4115template<typename T> II CPUCore<T>::ldi() { return BLOCK_LD( 1, false); }
4116template<typename T> II CPUCore<T>::lddr() { return BLOCK_LD(-1, true ); }
4117template<typename T> II CPUCore<T>::ldir() { return BLOCK_LD( 1, true ); }
4118
4119
4120// block IN
4121template<typename T> inline II CPUCore<T>::BLOCK_IN(int increase, bool repeat) {
4122 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_INI_1);
4123 T::setMemPtr(getBC() + increase);
4124 setBC(getBC() - 0x100); // decr before use
4125 byte val = READ_PORT(getBC(), T::CC_INI_1);
4126 WRMEM(getHL(), val, T::CC_INI_2);
4127 setHL(getHL() + increase);
4128 unsigned k = val + ((getC() + increase) & 0xFF);
4129 byte b = getB();
4130 if constexpr (T::IS_R800) {
4131 setF((getF() & ~Z_FLAG) | (b ? 0 : Z_FLAG) | N_FLAG);
4132 } else {
4133 setF(((val & S_FLAG) >> 6) | // N_FLAG
4134 ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4135 table.ZSXY[b] |
4136 (table.ZSPXY[(k & 0x07) ^ b] & P_FLAG));
4137 }
4138 if (repeat && b) {
4139 //setPC(getPC() - 2);
4140 return {-1/*1*/, T::CC_INIR};
4141 } else {
4142 return {1, T::CC_INI};
4143 }
4144}
4145template<typename T> II CPUCore<T>::ind() { return BLOCK_IN(-1, false); }
4146template<typename T> II CPUCore<T>::ini() { return BLOCK_IN( 1, false); }
4147template<typename T> II CPUCore<T>::indr() { return BLOCK_IN(-1, true ); }
4148template<typename T> II CPUCore<T>::inir() { return BLOCK_IN( 1, true ); }
4149
4150
4151// block OUT
4152template<typename T> inline II CPUCore<T>::BLOCK_OUT(int increase, bool repeat) {
4153 byte val = RDMEM(getHL(), T::CC_OUTI_1);
4154 setHL(getHL() + increase);
4155 if constexpr (T::IS_R800) T::waitForEvenCycle(T::CC_OUTI_2);
4156 WRITE_PORT(getBC(), val, T::CC_OUTI_2);
4157 setBC(getBC() - 0x100); // decr after use
4158 T::setMemPtr(getBC() + increase);
4159 unsigned k = val + getL();
4160 byte b = getB();
4161 if constexpr (T::IS_R800) {
4162 setF((getF() & ~Z_FLAG) | (b ? 0 : Z_FLAG) | N_FLAG);
4163 } else {
4164 setF(((val & S_FLAG) >> 6) | // N_FLAG
4165 ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4166 table.ZSXY[b] |
4167 (table.ZSPXY[(k & 0x07) ^ b] & P_FLAG));
4168 }
4169 if (repeat && b) {
4170 //setPC(getPC() - 2);
4171 return {-1/*1*/, T::CC_OTIR};
4172 } else {
4173 return {1, T::CC_OUTI};
4174 }
4175}
4176template<typename T> II CPUCore<T>::outd() { return BLOCK_OUT(-1, false); }
4177template<typename T> II CPUCore<T>::outi() { return BLOCK_OUT( 1, false); }
4178template<typename T> II CPUCore<T>::otdr() { return BLOCK_OUT(-1, true ); }
4179template<typename T> II CPUCore<T>::otir() { return BLOCK_OUT( 1, true ); }
4180
4181
4182// various
4183template<typename T> II CPUCore<T>::nop() { return {1, T::CC_NOP}; }
4184template<typename T> II CPUCore<T>::ccf() {
4185 byte f = 0;
4186 if constexpr (T::IS_R800) {
4187 // H flag is different from Z80 (and as always XY flags as well)
4188 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | X_FLAG | Y_FLAG | H_FLAG);
4189 } else {
4190 f |= (getF() & C_FLAG) << 4; // H_FLAG
4191 // only set X(Y) flag (don't reset if already set)
4192 if (isCMOS) {
4193 // Y flag is not changed on a CMOS Z80
4194 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | Y_FLAG);
4195 f |= (getF() | getA()) & X_FLAG;
4196 } else {
4197 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4198 f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4199 }
4200 }
4201 f ^= C_FLAG;
4202 setF(f);
4203 return {1, T::CC_CCF};
4204}
4205template<typename T> II CPUCore<T>::cpl() {
4206 setA(getA() ^ 0xFF);
4207 byte f = H_FLAG | N_FLAG;
4208 if constexpr (T::IS_R800) {
4209 f |= getF();
4210 } else {
4211 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4212 f |= getA() & (X_FLAG | Y_FLAG);
4213 }
4214 setF(f);
4215 return {1, T::CC_CPL};
4216}
4217template<typename T> II CPUCore<T>::daa() {
4218 byte a = getA();
4219 byte f = getF();
4220 byte adjust = 0;
4221 if ((f & H_FLAG) || ((getA() & 0xf) > 9)) adjust += 6;
4222 if ((f & C_FLAG) || (getA() > 0x99)) adjust += 0x60;
4223 if (f & N_FLAG) a -= adjust; else a += adjust;
4224 if constexpr (T::IS_R800) {
4225 f &= C_FLAG | N_FLAG | X_FLAG | Y_FLAG;
4226 f |= table.ZSP[a];
4227 } else {
4228 f &= C_FLAG | N_FLAG;
4229 f |= table.ZSPXY[a];
4230 }
4231 f |= (getA() > 0x99) | ((getA() ^ a) & H_FLAG);
4232 setA(a);
4233 setF(f);
4234 return {1, T::CC_DAA};
4235}
4236template<typename T> II CPUCore<T>::neg() {
4237 // alternative: LUT word negTable[256]
4238 unsigned a = getA();
4239 unsigned res = -signed(a);
4240 byte f = ((res & 0x100) ? C_FLAG : 0) |
4241 N_FLAG |
4242 ((res ^ a) & H_FLAG) |
4243 ((a & res & 0x80) >> 5); // V_FLAG
4244 if constexpr (T::IS_R800) {
4245 f |= table.ZS[res & 0xFF];
4246 f |= getF() & (X_FLAG | Y_FLAG);
4247 } else {
4248 f |= table.ZSXY[res & 0xFF];
4249 }
4250 setF(f);
4251 setA(res);
4252 return {1, T::CC_NEG};
4253}
4254template<typename T> II CPUCore<T>::scf() {
4255 byte f = C_FLAG;
4256 if constexpr (T::IS_R800) {
4257 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
4258 } else {
4259 // only set X(Y) flag (don't reset if already set)
4260 if (isCMOS) {
4261 // Y flag is not changed on a CMOS Z80
4262 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | Y_FLAG);
4263 f |= (getF() | getA()) & X_FLAG;
4264 } else {
4265 f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
4266 f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4267 }
4268 }
4269 setF(f);
4270 return {1, T::CC_SCF};
4271}
4272
4273template<typename T> II CPUCore<T>::ex_af_af() {
4274 unsigned t = getAF2(); setAF2(getAF()); setAF(t);
4275 return {1, T::CC_EX};
4276}
4277template<typename T> II CPUCore<T>::ex_de_hl() {
4278 unsigned t = getDE(); setDE(getHL()); setHL(t);
4279 return {1, T::CC_EX};
4280}
4281template<typename T> II CPUCore<T>::exx() {
4282 unsigned t1 = getBC2(); setBC2(getBC()); setBC(t1);
4283 unsigned t2 = getDE2(); setDE2(getDE()); setDE(t2);
4284 unsigned t3 = getHL2(); setHL2(getHL()); setHL(t3);
4285 return {1, T::CC_EX};
4286}
4287
4288template<typename T> II CPUCore<T>::di() {
4289 setIFF1(false);
4290 setIFF2(false);
4291 return {1, T::CC_DI};
4292}
4293template<typename T> II CPUCore<T>::ei() {
4294 setIFF1(true);
4295 setIFF2(true);
4296 setCurrentEI(); // no ints directly after this instr
4297 setSlowInstructions();
4298 return {1, T::CC_EI};
4299}
4300template<typename T> II CPUCore<T>::halt() {
4301 setHALT(true);
4302 setSlowInstructions();
4303
4304 if (!(getIFF1() || getIFF2())) {
4305 diHaltCallback.execute();
4306 }
4307 return {1, T::CC_HALT};
4308}
4309template<typename T> template<unsigned N> II CPUCore<T>::im_N() {
4310 setIM(N); return {1, T::CC_IM};
4311}
4312
4313// LD A,I/R
4314template<typename T> template<Reg8 REG> II CPUCore<T>::ld_a_IR() {
4315 setA(get8<REG>());
4316 byte f = getIFF2() ? V_FLAG : 0;
4317 if constexpr (T::IS_R800) {
4318 f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4319 f |= table.ZS[getA()];
4320 } else {
4321 f |= getF() & C_FLAG;
4322 f |= table.ZSXY[getA()];
4323 // see comment in the IRQ acceptance part of executeSlow().
4324 setCurrentLDAI(); // only Z80 (not R800) has this quirk
4325 setSlowInstructions();
4326 }
4327 setF(f);
4328 return {1, T::CC_LD_A_I};
4329}
4330
4331// LD I/R,A
4332template<typename T> II CPUCore<T>::ld_r_a() {
4333 // This code sequence:
4334 // XOR A / LD R,A / LD A,R
4335 // gives A=2 for Z80, but A=1 for R800. The difference can possibly be
4336 // explained by a difference in the relative time between writing the
4337 // new value to the R register and increasing the R register per M1
4338 // cycle. Here we implemented the R800 behaviour by storing 'A-1' into
4339 // R, that's good enough for now.
4340 byte val = getA();
4341 if constexpr (T::IS_R800) val -= 1;
4342 setR(val);
4343 return {1, T::CC_LD_A_I};
4344}
4345template<typename T> II CPUCore<T>::ld_i_a() {
4346 setI(getA());
4347 return {1, T::CC_LD_A_I};
4348}
4349
4350// MULUB A,r
4351template<typename T> template<Reg8 REG> II CPUCore<T>::mulub_a_R() {
4352 assert(T::IS_R800); // this instruction is R800-only
4353 // Verified on real R800:
4354 // YHXN flags are unchanged
4355 // SV flags are reset
4356 // Z flag is set when result is zero
4357 // C flag is set when result doesn't fit in 8-bit
4358 setHL(unsigned(getA()) * get8<REG>());
4359 setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4360 0 | // S_FLAG V_FLAG
4361 (getHL() ? 0 : Z_FLAG) |
4362 ((getHL() & 0xFF00) ? C_FLAG : 0));
4363 return {1, T::CC_MULUB};
4364}
4365
4366// MULUW HL,ss
4367template<typename T> template<Reg16 REG> II CPUCore<T>::muluw_hl_SS() {
4368 assert(T::IS_R800); // this instruction is R800-only
4369 // Verified on real R800:
4370 // YHXN flags are unchanged
4371 // SV flags are reset
4372 // Z flag is set when result is zero
4373 // C flag is set when result doesn't fit in 16-bit
4374 unsigned res = unsigned(getHL()) * get16<REG>();
4375 setDE(res >> 16);
4376 setHL(res & 0xffff);
4377 setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4378 0 | // S_FLAG V_FLAG
4379 (res ? 0 : Z_FLAG) |
4380 ((res & 0xFFFF0000) ? C_FLAG : 0));
4381 return {1, T::CC_MULUW};
4382}
4383
4384
4385// versions:
4386// 1 -> initial version
4387// 2 -> moved memptr from here to Z80TYPE (and not to R800TYPE)
4388// 3 -> timing of the emulation changed (no changes in serialization)
4389// 4 -> timing of the emulation changed again (see doc/internal/r800-call.txt)
4390// 5 -> added serialization of nmiEdge
4391template<typename T> template<typename Archive>
4392void CPUCore<T>::serialize(Archive& ar, unsigned version)
4393{
4394 T::serialize(ar, version);
4395 ar.serialize("regs", static_cast<CPURegs&>(*this));
4396 if (ar.versionBelow(version, 2)) {
4397 unsigned mPtr = 0; // dummy value (avoid warning)
4398 ar.serialize("memptr", mPtr);
4399 T::setMemPtr(mPtr);
4400 }
4401
4402 if (ar.versionBelow(version, 5)) {
4403 // NMI is unused on MSX and even on systems where it is used nmiEdge
4404 // is true only between the moment the NMI request comes in and the
4405 // moment the Z80 jumps to the NMI handler, so defaulting to false
4406 // is pretty safe.
4407 nmiEdge = false;
4408 } else {
4409 // CPU is deserialized after devices, so nmiEdge is restored to the
4410 // saved version even if IRQHelpers set it on deserialization.
4411 ar.serialize("nmiEdge", nmiEdge);
4412 }
4413
4414 // Don't serialize:
4415 // - IRQStatus, NMIStatus:
4416 // the IRQHelper deserialization makes sure these get the right value
4417 // - slowInstructions, exitLoop:
4418 // serialization happens outside the CPU emulation loop
4419
4420 if constexpr (T::IS_R800) {
4421 if (ar.versionBelow(version, 4)) {
4422 motherboard.getMSXCliComm().printWarning(
4423 "Loading an old savestate: the timing of the R800 "
4424 "emulation has changed. This may cause synchronization "
4425 "problems in replay.");
4426 }
4427 }
4428}
4429
4430// Force template instantiation
4431template class CPUCore<Z80TYPE>;
4432template class CPUCore<R800TYPE>;
4433
4436
4437} // namespace openmsx
#define NEXT
#define NEXT_EI
#define CASE(X)
#define NEXT_STOP
BaseSetting * setting
Definition: Interpreter.cc:27
TclObject t
void lowerIRQ()
Lowers the maskable interrupt count.
Definition: CPUCore.cc:436
void setNextSyncPoint(EmuTime::param time)
Definition: CPUCore.cc:491
void disasmCommand(Interpreter &interp, std::span< const TclObject > tokens, TclObject &result) const
Definition: CPUCore.cc:507
void setFreq(unsigned freq)
Change the clock freq.
Definition: CPUCore.cc:534
void execute(bool fastForward)
Definition: CPUCore.cc:2534
void warp(EmuTime::param time)
Definition: CPUCore.cc:318
CPUCore(MSXMotherBoard &motherboard, const std::string &name, const BooleanSetting &traceSetting, TclCallback &diHaltCallback, EmuTime::param time)
Definition: CPUCore.cc:278
void lowerNMI()
Lowers the non-maskable interrupt count.
Definition: CPUCore.cc:452
void exitCPULoopSync()
Request to exit the main CPU emulation loop.
Definition: CPUCore.cc:397
EmuTime::param getCurrentTime() const
Definition: CPUCore.cc:324
void exitCPULoopAsync()
Similar to exitCPULoopSync(), but this method may be called from any thread.
Definition: CPUCore.cc:392
void raiseNMI()
Raises the non-maskable interrupt count.
Definition: CPUCore.cc:442
void serialize(Archive &ar, unsigned version)
Definition: CPUCore.cc:4392
void doReset(EmuTime::param time)
Reset the CPU.
Definition: CPUCore.cc:329
void wait(EmuTime::param time)
Definition: CPUCore.cc:474
EmuTime waitCycles(EmuTime::param time, unsigned cycles)
Definition: CPUCore.cc:481
bool isM1Cycle(unsigned address) const
Definition: CPUCore.cc:458
void raiseIRQ()
Raises the maskable interrupt count.
Definition: CPUCore.cc:427
void addListElement(const T &t)
Definition: TclObject.hh:127
#define NEVER_INLINE
Definition: inline.hh:17
#define ALWAYS_INLINE
Definition: inline.hh:16
ALWAYS_INLINE uint16_t read_UA_L16(const void *p)
Definition: endian.hh:227
ALWAYS_INLINE void write_UA_L16(void *p, uint16_t x)
Definition: endian.hh:187
constexpr unsigned LOW
Definition: CacheLine.hh:9
constexpr unsigned HIGH
Definition: CacheLine.hh:10
constexpr unsigned BITS
Definition: CacheLine.hh:6
bool isMainThread()
Returns true when called from the main thread.
Definition: Thread.cc:15
This file implemented 3 utility functions:
Definition: Autofire.cc:9
constexpr byte N_FLAG
Definition: CPUCore.cc:211
constexpr byte ZSXY0
Definition: CPUCore.cc:224
constexpr byte Y_FLAG
Definition: CPUCore.cc:206
constexpr byte Z_FLAG
Definition: CPUCore.cc:205
constexpr Table table
Definition: CPUCore.cc:259
constexpr unsigned N
Definition: ResampleHQ.cc:226
unsigned dasm(const MSXCPUInterface &interf, word pc, byte buf[4], std::string &dest, EmuTime::param time)
Disassemble.
Definition: Dasm.cc:18
@ REG_I
Definition: CPUCore.cc:200
@ REG_R
Definition: CPUCore.cc:200
@ DUMMY
Definition: CPUCore.cc:200
constexpr byte V_FLAG
Definition: CPUCore.cc:209
constexpr byte ZSXY255
Definition: CPUCore.cc:228
constexpr byte P_FLAG
Definition: CPUCore.cc:210
constexpr byte C_FLAG
Definition: CPUCore.cc:212
constexpr byte S_FLAG
Definition: CPUCore.cc:204
uint16_t word
16 bit unsigned integer
Definition: openmsx.hh:29
constexpr KeyMatrixPosition x
Keyboard bindings.
Definition: Keyboard.cc:127
void serialize(Archive &ar, T &t, unsigned version)
constexpr byte H_FLAG
Definition: CPUCore.cc:207
constexpr byte ZSPXY0
Definition: CPUCore.cc:226
constexpr byte ZSP0
Definition: CPUCore.cc:225
constexpr byte ZS0
Definition: CPUCore.cc:223
constexpr byte X_FLAG
Definition: CPUCore.cc:208
constexpr byte ZS255
Definition: CPUCore.cc:227
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
Definition: serialize.hh:1009
TemporaryString tmpStrCat(Ts &&... ts)
Definition: strCat.hh:617
Definition: view_test.cc:239
bool operator()(byte f) const
Definition: CPUCore.cc:268
bool operator()(byte f) const
Definition: CPUCore.cc:272
bool operator()(byte f) const
Definition: CPUCore.cc:269
bool operator()(byte f) const
Definition: CPUCore.cc:271
bool operator()(byte f) const
Definition: CPUCore.cc:274
bool operator()(byte f) const
Definition: CPUCore.cc:275
bool operator()(byte f) const
Definition: CPUCore.cc:273
bool operator()(byte) const
Definition: CPUCore.cc:276
bool operator()(byte f) const
Definition: CPUCore.cc:270
byte ZSP[256]
Definition: CPUCore.cc:218
byte ZSXY[256]
Definition: CPUCore.cc:217
byte ZSPH[256]
Definition: CPUCore.cc:220
byte ZSPXY[256]
Definition: CPUCore.cc:219
byte ZS[256]
Definition: CPUCore.cc:216
#define UNREACHABLE
Definition: unreachable.hh:38
constexpr void repeat(T n, Op op)
Repeat the given operation 'op' 'n' times.
Definition: xrange.hh:148
constexpr auto xrange(T e)
Definition: xrange.hh:133