openMSX
opll.cc
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1 /*
2  * Copyright (C) 2019 Nuke.YKT
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12  * GNU General Public License for more details.
13  *
14  *
15  * Yamaha YM2413 emulator
16  * Thanks:
17  * siliconpr0n.org(digshadow, John McMaster):
18  * VRC VII decap and die shot.
19  *
20  * version: 1.0.1
21  */
22 
23 #include <string.h>
24 #include "opll.hh"
25 
26 enum {
30  eg_num_release = 3
31 };
32 
33 enum {
35  rm_num_hh = 1,
38  rm_num_sd = 4,
39  rm_num_tc = 5
40 };
41 
42 /* logsin table */
43 static const uint16_t logsinrom[256] = {
44  0x859, 0x6c3, 0x607, 0x58b, 0x52e, 0x4e4, 0x4a6, 0x471,
45  0x443, 0x41a, 0x3f5, 0x3d3, 0x3b5, 0x398, 0x37e, 0x365,
46  0x34e, 0x339, 0x324, 0x311, 0x2ff, 0x2ed, 0x2dc, 0x2cd,
47  0x2bd, 0x2af, 0x2a0, 0x293, 0x286, 0x279, 0x26d, 0x261,
48  0x256, 0x24b, 0x240, 0x236, 0x22c, 0x222, 0x218, 0x20f,
49  0x206, 0x1fd, 0x1f5, 0x1ec, 0x1e4, 0x1dc, 0x1d4, 0x1cd,
50  0x1c5, 0x1be, 0x1b7, 0x1b0, 0x1a9, 0x1a2, 0x19b, 0x195,
51  0x18f, 0x188, 0x182, 0x17c, 0x177, 0x171, 0x16b, 0x166,
52  0x160, 0x15b, 0x155, 0x150, 0x14b, 0x146, 0x141, 0x13c,
53  0x137, 0x133, 0x12e, 0x129, 0x125, 0x121, 0x11c, 0x118,
54  0x114, 0x10f, 0x10b, 0x107, 0x103, 0x0ff, 0x0fb, 0x0f8,
55  0x0f4, 0x0f0, 0x0ec, 0x0e9, 0x0e5, 0x0e2, 0x0de, 0x0db,
56  0x0d7, 0x0d4, 0x0d1, 0x0cd, 0x0ca, 0x0c7, 0x0c4, 0x0c1,
57  0x0be, 0x0bb, 0x0b8, 0x0b5, 0x0b2, 0x0af, 0x0ac, 0x0a9,
58  0x0a7, 0x0a4, 0x0a1, 0x09f, 0x09c, 0x099, 0x097, 0x094,
59  0x092, 0x08f, 0x08d, 0x08a, 0x088, 0x086, 0x083, 0x081,
60  0x07f, 0x07d, 0x07a, 0x078, 0x076, 0x074, 0x072, 0x070,
61  0x06e, 0x06c, 0x06a, 0x068, 0x066, 0x064, 0x062, 0x060,
62  0x05e, 0x05c, 0x05b, 0x059, 0x057, 0x055, 0x053, 0x052,
63  0x050, 0x04e, 0x04d, 0x04b, 0x04a, 0x048, 0x046, 0x045,
64  0x043, 0x042, 0x040, 0x03f, 0x03e, 0x03c, 0x03b, 0x039,
65  0x038, 0x037, 0x035, 0x034, 0x033, 0x031, 0x030, 0x02f,
66  0x02e, 0x02d, 0x02b, 0x02a, 0x029, 0x028, 0x027, 0x026,
67  0x025, 0x024, 0x023, 0x022, 0x021, 0x020, 0x01f, 0x01e,
68  0x01d, 0x01c, 0x01b, 0x01a, 0x019, 0x018, 0x017, 0x017,
69  0x016, 0x015, 0x014, 0x014, 0x013, 0x012, 0x011, 0x011,
70  0x010, 0x00f, 0x00f, 0x00e, 0x00d, 0x00d, 0x00c, 0x00c,
71  0x00b, 0x00a, 0x00a, 0x009, 0x009, 0x008, 0x008, 0x007,
72  0x007, 0x007, 0x006, 0x006, 0x005, 0x005, 0x005, 0x004,
73  0x004, 0x004, 0x003, 0x003, 0x003, 0x002, 0x002, 0x002,
74  0x002, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001,
75  0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000
76 };
77 
78 /* exp table */
79 static const uint16_t exprom[256] = {
80  0x7fa, 0x7f5, 0x7ef, 0x7ea, 0x7e4, 0x7df, 0x7da, 0x7d4,
81  0x7cf, 0x7c9, 0x7c4, 0x7bf, 0x7b9, 0x7b4, 0x7ae, 0x7a9,
82  0x7a4, 0x79f, 0x799, 0x794, 0x78f, 0x78a, 0x784, 0x77f,
83  0x77a, 0x775, 0x770, 0x76a, 0x765, 0x760, 0x75b, 0x756,
84  0x751, 0x74c, 0x747, 0x742, 0x73d, 0x738, 0x733, 0x72e,
85  0x729, 0x724, 0x71f, 0x71a, 0x715, 0x710, 0x70b, 0x706,
86  0x702, 0x6fd, 0x6f8, 0x6f3, 0x6ee, 0x6e9, 0x6e5, 0x6e0,
87  0x6db, 0x6d6, 0x6d2, 0x6cd, 0x6c8, 0x6c4, 0x6bf, 0x6ba,
88  0x6b5, 0x6b1, 0x6ac, 0x6a8, 0x6a3, 0x69e, 0x69a, 0x695,
89  0x691, 0x68c, 0x688, 0x683, 0x67f, 0x67a, 0x676, 0x671,
90  0x66d, 0x668, 0x664, 0x65f, 0x65b, 0x657, 0x652, 0x64e,
91  0x649, 0x645, 0x641, 0x63c, 0x638, 0x634, 0x630, 0x62b,
92  0x627, 0x623, 0x61e, 0x61a, 0x616, 0x612, 0x60e, 0x609,
93  0x605, 0x601, 0x5fd, 0x5f9, 0x5f5, 0x5f0, 0x5ec, 0x5e8,
94  0x5e4, 0x5e0, 0x5dc, 0x5d8, 0x5d4, 0x5d0, 0x5cc, 0x5c8,
95  0x5c4, 0x5c0, 0x5bc, 0x5b8, 0x5b4, 0x5b0, 0x5ac, 0x5a8,
96  0x5a4, 0x5a0, 0x59c, 0x599, 0x595, 0x591, 0x58d, 0x589,
97  0x585, 0x581, 0x57e, 0x57a, 0x576, 0x572, 0x56f, 0x56b,
98  0x567, 0x563, 0x560, 0x55c, 0x558, 0x554, 0x551, 0x54d,
99  0x549, 0x546, 0x542, 0x53e, 0x53b, 0x537, 0x534, 0x530,
100  0x52c, 0x529, 0x525, 0x522, 0x51e, 0x51b, 0x517, 0x514,
101  0x510, 0x50c, 0x509, 0x506, 0x502, 0x4ff, 0x4fb, 0x4f8,
102  0x4f4, 0x4f1, 0x4ed, 0x4ea, 0x4e7, 0x4e3, 0x4e0, 0x4dc,
103  0x4d9, 0x4d6, 0x4d2, 0x4cf, 0x4cc, 0x4c8, 0x4c5, 0x4c2,
104  0x4be, 0x4bb, 0x4b8, 0x4b5, 0x4b1, 0x4ae, 0x4ab, 0x4a8,
105  0x4a4, 0x4a1, 0x49e, 0x49b, 0x498, 0x494, 0x491, 0x48e,
106  0x48b, 0x488, 0x485, 0x482, 0x47e, 0x47b, 0x478, 0x475,
107  0x472, 0x46f, 0x46c, 0x469, 0x466, 0x463, 0x460, 0x45d,
108  0x45a, 0x457, 0x454, 0x451, 0x44e, 0x44b, 0x448, 0x445,
109  0x442, 0x43f, 0x43c, 0x439, 0x436, 0x433, 0x430, 0x42d,
110  0x42a, 0x428, 0x425, 0x422, 0x41f, 0x41c, 0x419, 0x416,
111  0x414, 0x411, 0x40e, 0x40b, 0x408, 0x406, 0x403, 0x400
112 };
113 
114 static const opll_patch_t patch_ds1001[opll_patch_max] = {
115  { 0x05, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x03, 0x01 },{ 0x00, 0x00 },{ 0x0e, 0x08 },{ 0x08, 0x01 },{ 0x04, 0x02 },{ 0x02, 0x07 } },
116  { 0x14, 0x00, 0x01, 0x05,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x03, 0x01 },{ 0x00, 0x00 },{ 0x0d, 0x0f },{ 0x08, 0x06 },{ 0x02, 0x01 },{ 0x03, 0x02 } },
117  { 0x08, 0x00, 0x01, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0f, 0x0b },{ 0x0a, 0x02 },{ 0x02, 0x01 },{ 0x00, 0x02 } },
118  { 0x0c, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x06 },{ 0x08, 0x04 },{ 0x06, 0x02 },{ 0x01, 0x07 } },
119  { 0x1e, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x02, 0x01 },{ 0x00, 0x00 },{ 0x0e, 0x07 },{ 0x01, 0x06 },{ 0x00, 0x02 },{ 0x01, 0x08 } },
120  { 0x06, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x02, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x0e },{ 0x03, 0x02 },{ 0x0f, 0x0f },{ 0x04, 0x04 } },
121  { 0x1d, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x08, 0x08 },{ 0x02, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x07 } },
122  { 0x22, 0x01, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x03, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x07 },{ 0x02, 0x02 },{ 0x00, 0x01 },{ 0x01, 0x07 } },
123  { 0x25, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x05, 0x01 },{ 0x00, 0x00 },{ 0x04, 0x07 },{ 0x00, 0x03 },{ 0x07, 0x00 },{ 0x02, 0x01 } },
124  { 0x0f, 0x00, 0x01, 0x07,{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x00 },{ 0x05, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x0a },{ 0x08, 0x05 },{ 0x05, 0x00 },{ 0x01, 0x02 } },
125  { 0x24, 0x00, 0x00, 0x07,{ 0x00, 0x01 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x07, 0x01 },{ 0x00, 0x00 },{ 0x0f, 0x0f },{ 0x08, 0x08 },{ 0x02, 0x01 },{ 0x02, 0x02 } },
126  { 0x11, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x03 },{ 0x00, 0x00 },{ 0x06, 0x07 },{ 0x05, 0x04 },{ 0x01, 0x01 },{ 0x08, 0x06 } },
127  { 0x13, 0x00, 0x00, 0x05,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x02 },{ 0x03, 0x00 },{ 0x0c, 0x09 },{ 0x09, 0x05 },{ 0x00, 0x00 },{ 0x03, 0x02 } },
128  { 0x0c, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x03 },{ 0x00, 0x00 },{ 0x09, 0x0c },{ 0x04, 0x00 },{ 0x03, 0x0f },{ 0x03, 0x06 } },
129  { 0x0d, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x01 },{ 0x01, 0x02 },{ 0x00, 0x00 },{ 0x0c, 0x0d },{ 0x01, 0x05 },{ 0x05, 0x00 },{ 0x06, 0x06 } },
130 
131  { 0x18, 0x00, 0x01, 0x07,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0d, 0x00 },{ 0x0f, 0x00 },{ 0x06, 0x00 },{ 0x0a, 0x00 } },
132  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0c, 0x00 },{ 0x08, 0x00 },{ 0x0a, 0x00 },{ 0x07, 0x00 } },
133  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x05, 0x00 },{ 0x00, 0x00 },{ 0x0f, 0x00 },{ 0x08, 0x00 },{ 0x05, 0x00 },{ 0x09, 0x00 } },
134  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0f },{ 0x00, 0x08 },{ 0x00, 0x06 },{ 0x00, 0x0d } },
135  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0d },{ 0x00, 0x08 },{ 0x00, 0x06 },{ 0x00, 0x08 } },
136  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0a },{ 0x00, 0x0a },{ 0x00, 0x05 },{ 0x00, 0x05 } }
137 };
138 
139 static const opll_patch_t patch_ym2413[opll_patch_max] = {
140  { 0x1e, 0x01, 0x00, 0x07,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0d, 0x07 },{ 0x00, 0x08 },{ 0x00, 0x01 },{ 0x00, 0x07 } },
141  { 0x1a, 0x00, 0x01, 0x05,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x03, 0x01 },{ 0x00, 0x00 },{ 0x0d, 0x0f },{ 0x08, 0x07 },{ 0x02, 0x01 },{ 0x03, 0x03 } },
142  { 0x19, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x03, 0x01 },{ 0x02, 0x00 },{ 0x0f, 0x0c },{ 0x02, 0x04 },{ 0x01, 0x02 },{ 0x01, 0x03 } },
143  { 0x0e, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x06 },{ 0x08, 0x04 },{ 0x07, 0x02 },{ 0x00, 0x07 } },
144  { 0x1e, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x02, 0x01 },{ 0x00, 0x00 },{ 0x0e, 0x07 },{ 0x00, 0x06 },{ 0x00, 0x02 },{ 0x00, 0x08 } },
145  { 0x16, 0x00, 0x00, 0x05,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x02 },{ 0x00, 0x00 },{ 0x0e, 0x07 },{ 0x00, 0x01 },{ 0x00, 0x01 },{ 0x00, 0x08 } },
146  { 0x1d, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x08, 0x08 },{ 0x02, 0x01 },{ 0x01, 0x00 },{ 0x00, 0x07 } },
147  { 0x2d, 0x01, 0x00, 0x04,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x03, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x07 },{ 0x02, 0x02 },{ 0x00, 0x00 },{ 0x00, 0x07 } },
148  { 0x1b, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x06, 0x06 },{ 0x04, 0x05 },{ 0x01, 0x01 },{ 0x00, 0x07 } },
149  { 0x0b, 0x01, 0x01, 0x00,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x08, 0x0f },{ 0x05, 0x07 },{ 0x07, 0x00 },{ 0x01, 0x07 } },
150  { 0x03, 0x01, 0x00, 0x01,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x03, 0x01 },{ 0x02, 0x00 },{ 0x0f, 0x0e },{ 0x0a, 0x04 },{ 0x01, 0x00 },{ 0x00, 0x04 } },
151  { 0x24, 0x00, 0x00, 0x07,{ 0x00, 0x01 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x07, 0x01 },{ 0x00, 0x00 },{ 0x0f, 0x0f },{ 0x08, 0x08 },{ 0x02, 0x01 },{ 0x02, 0x02 } },
152  { 0x0c, 0x00, 0x00, 0x05,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0c, 0x0f },{ 0x02, 0x05 },{ 0x02, 0x04 },{ 0x00, 0x02 } },
153  { 0x15, 0x00, 0x00, 0x03,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x0c, 0x09 },{ 0x09, 0x05 },{ 0x00, 0x00 },{ 0x03, 0x02 } },
154  { 0x09, 0x00, 0x00, 0x03,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x02, 0x00 },{ 0x0f, 0x0e },{ 0x01, 0x04 },{ 0x04, 0x01 },{ 0x00, 0x03 } },
155 
156  { 0x18, 0x00, 0x01, 0x07,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0d, 0x00 },{ 0x0f, 0x00 },{ 0x06, 0x00 },{ 0x0a, 0x00 } },
157  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0c, 0x00 },{ 0x08, 0x00 },{ 0x0a, 0x00 },{ 0x07, 0x00 } },
158  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x05, 0x00 },{ 0x00, 0x00 },{ 0x0f, 0x00 },{ 0x08, 0x00 },{ 0x05, 0x00 },{ 0x09, 0x00 } },
159  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0f },{ 0x00, 0x08 },{ 0x00, 0x06 },{ 0x00, 0x0d } },
160  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0d },{ 0x00, 0x08 },{ 0x00, 0x04 },{ 0x00, 0x08 } },
161  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0a },{ 0x00, 0x0a },{ 0x00, 0x05 },{ 0x00, 0x05 } }
162 };
163 
164 static const opll_patch_t patch_ymf281[opll_patch_max] = {
165  { 0x1a, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x02, 0x01 },{ 0x00, 0x00 },{ 0x0f, 0x06 },{ 0x0f, 0x07 },{ 0x00, 0x01 },{ 0x00, 0x06 } },
166  { 0x05, 0x00, 0x00, 0x01,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x0f, 0x08 },{ 0x06, 0x03 },{ 0x08, 0x00 },{ 0x00, 0x03 } },
167  { 0x16, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x03, 0x01 },{ 0x02, 0x00 },{ 0x0f, 0x0d },{ 0x02, 0x03 },{ 0x01, 0x00 },{ 0x01, 0x03 } },
168  { 0x0b, 0x00, 0x01, 0x07,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x06 },{ 0x08, 0x04 },{ 0x07, 0x01 },{ 0x00, 0x07 } },
169  { 0x1e, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x02, 0x01 },{ 0x00, 0x00 },{ 0x0e, 0x07 },{ 0x01, 0x06 },{ 0x00, 0x02 },{ 0x00, 0x08 } },
170  { 0x02, 0x00, 0x01, 0x06,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x02, 0x00 },{ 0x09, 0x06 },{ 0x0a, 0x01 },{ 0x02, 0x02 },{ 0x00, 0x07 } },
171  { 0x1b, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x08, 0x08 },{ 0x04, 0x03 },{ 0x01, 0x00 },{ 0x00, 0x07 } },
172  { 0x0a, 0x00, 0x00, 0x02,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x07, 0x02 },{ 0x03, 0x00 },{ 0x06, 0x06 },{ 0x06, 0x04 },{ 0x04, 0x02 },{ 0x00, 0x07 } },
173  { 0x07, 0x00, 0x00, 0x03,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0c, 0x07 },{ 0x05, 0x07 },{ 0x05, 0x00 },{ 0x01, 0x07 } },
174  { 0x1e, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x00 },{ 0x06, 0x01 },{ 0x01, 0x00 },{ 0x0f, 0x0f },{ 0x02, 0x03 },{ 0x0f, 0x0f },{ 0x00, 0x03 } },
175  { 0x18, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x0f, 0x0e },{ 0x05, 0x03 },{ 0x02, 0x01 },{ 0x00, 0x03 } },
176  { 0x24, 0x00, 0x00, 0x07,{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x07, 0x01 },{ 0x00, 0x00 },{ 0x0f, 0x0f },{ 0x08, 0x08 },{ 0x02, 0x00 },{ 0x02, 0x03 } },
177  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x05, 0x04 },{ 0x00, 0x00 },{ 0x0f, 0x0f },{ 0x0f, 0x03 },{ 0x07, 0x0f },{ 0x00, 0x05 } },
178  { 0x03, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x01 },{ 0x0f, 0x01 },{ 0x00, 0x00 },{ 0x0f, 0x0e },{ 0x0c, 0x03 },{ 0x03, 0x0f },{ 0x0f, 0x0c } },
179  { 0x00, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x01 },{ 0x00, 0x00 },{ 0x0b, 0x08 },{ 0x0f, 0x04 },{ 0x00, 0x0f },{ 0x00, 0x05 } },
180 
181  { 0x18, 0x00, 0x01, 0x07,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0d, 0x00 },{ 0x0f, 0x00 },{ 0x06, 0x00 },{ 0x0a, 0x00 } },
182  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0c, 0x00 },{ 0x08, 0x00 },{ 0x0a, 0x00 },{ 0x07, 0x00 } },
183  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x05, 0x00 },{ 0x00, 0x00 },{ 0x0f, 0x00 },{ 0x08, 0x00 },{ 0x05, 0x00 },{ 0x09, 0x00 } },
184  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0f },{ 0x00, 0x08 },{ 0x00, 0x06 },{ 0x00, 0x0d } },
185  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0d },{ 0x00, 0x08 },{ 0x00, 0x04 },{ 0x00, 0x08 } },
186  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0a },{ 0x00, 0x0a },{ 0x00, 0x05 },{ 0x00, 0x05 } }
187 };
188 
189 static const opll_patch_t patch_ym2423[opll_patch_max] = {
190  { 0x1b, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x09, 0x05 },{ 0x04, 0x04 },{ 0x01, 0x00 },{ 0x00, 0x05 } },
191  { 0x12, 0x00, 0x00, 0x04,{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x03, 0x01 },{ 0x01, 0x00 },{ 0x0f, 0x0f },{ 0x03, 0x02 },{ 0x0a, 0x0e },{ 0x00, 0x09 } },
192  { 0x11, 0x00, 0x00, 0x05,{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x02 },{ 0x0f, 0x0f },{ 0x02, 0x02 },{ 0x05, 0x07 },{ 0x00, 0x05 } },
193  { 0x28, 0x00, 0x00, 0x07,{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x03, 0x02 },{ 0x00, 0x00 },{ 0x0f, 0x0f },{ 0x03, 0x02 },{ 0x09, 0x0b },{ 0x00, 0x04 } },
194  { 0x17, 0x00, 0x00, 0x05,{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x02, 0x01 },{ 0x02, 0x00 },{ 0x05, 0x06 },{ 0x01, 0x0f },{ 0x07, 0x00 },{ 0x00, 0x09 } },
195  { 0x18, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x03, 0x00 },{ 0x00, 0x00 },{ 0x0f, 0x0f },{ 0x07, 0x04 },{ 0x05, 0x08 },{ 0x00, 0x05 } },
196  { 0x1c, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x05, 0x07 },{ 0x01, 0x01 },{ 0x02, 0x02 },{ 0x00, 0x06 } },
197  { 0x1b, 0x00, 0x00, 0x07,{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x04 },{ 0x00, 0x00 },{ 0x07, 0x03 },{ 0x03, 0x0f },{ 0x00, 0x00 },{ 0x00, 0x06 } },
198  { 0x0d, 0x00, 0x00, 0x03,{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x04, 0x06 },{ 0x02, 0x0f },{ 0x02, 0x00 },{ 0x00, 0x06 } },
199  { 0x10, 0x00, 0x00, 0x05,{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x02 },{ 0x0f, 0x0f },{ 0x03, 0x03 },{ 0x02, 0x00 },{ 0x00, 0x04 } },
200  { 0x1b, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0c, 0x09 },{ 0x05, 0x06 },{ 0x0f, 0x0f },{ 0x00, 0x06 } },
201  { 0x1b, 0x00, 0x00, 0x00,{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x09, 0x01 },{ 0x03, 0x00 },{ 0x0f, 0x0f },{ 0x05, 0x03 },{ 0x07, 0x0f },{ 0x00, 0x02 } },
202  { 0x11, 0x00, 0x00, 0x03,{ 0x00, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x02 },{ 0x02, 0x00 },{ 0x09, 0x0b },{ 0x04, 0x01 },{ 0x0e, 0x0f },{ 0x00, 0x07 } },
203  { 0x17, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x0d, 0x0e },{ 0x03, 0x01 },{ 0x0b, 0x0e },{ 0x00, 0x0b } },
204  { 0x0d, 0x00, 0x00, 0x05,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x06 },{ 0x00, 0x00 },{ 0x0f, 0x0f },{ 0x02, 0x04 },{ 0x02, 0x09 },{ 0x00, 0x09 } },
205 
206  { 0x18, 0x00, 0x01, 0x07,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0d, 0x00 },{ 0x0f, 0x00 },{ 0x06, 0x00 },{ 0x0a, 0x00 } },
207  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0c, 0x00 },{ 0x08, 0x00 },{ 0x0a, 0x00 },{ 0x07, 0x00 } },
208  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x05, 0x00 },{ 0x00, 0x00 },{ 0x0f, 0x00 },{ 0x08, 0x00 },{ 0x05, 0x00 },{ 0x09, 0x00 } },
209  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0f },{ 0x00, 0x08 },{ 0x00, 0x06 },{ 0x00, 0x0d } },
210  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0d },{ 0x00, 0x08 },{ 0x00, 0x04 },{ 0x00, 0x08 } },
211  { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0a },{ 0x00, 0x0a },{ 0x00, 0x05 },{ 0x00, 0x05 } }
212 };
213 
214 static const uint32_t ch_offset[18] = {
215  1, 2, 0, 1, 2, 3, 4, 5, 3, 4, 5, 6, 7, 8, 6, 7, 8, 0
216 };
217 
218 static const uint32_t pg_multi[16] = {
219  1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 20, 24, 24, 30, 30
220 };
221 
222 static const uint32_t eg_stephi[4][4] = {
223  { 0, 0, 0, 0 },
224  { 1, 0, 0, 0 },
225  { 1, 0, 1, 0 },
226  { 1, 1, 1, 0 }
227 };
228 
229 static const uint32_t eg_ksltable[16] = {
230  0, 32, 40, 45, 48, 51, 53, 55, 56, 58, 59, 60, 61, 62, 63, 64
231 };
232 
233 static void OPLL_DoIO(opll_t *chip) {
234  /* Write signal check */
235  chip->write_a_en = (chip->write_a & 0x03) == 0x01;
236  chip->write_d_en = (chip->write_d & 0x03) == 0x01;
237  chip->write_a <<= 1;
238  chip->write_d <<= 1;
239 }
240 
241 static void OPLL_DoModeWrite(opll_t *chip) {
242  uint8_t slot;
243  if ((chip->write_mode_address & 0x10) && chip->write_d_en) {
244  slot = chip->write_mode_address & 0x01;
245  switch (chip->write_mode_address & 0x0f) {
246  case 0x00:
247  case 0x01:
248  chip->patch.multi[slot] = chip->write_data & 0x0f;
249  chip->patch.ksr[slot] = (chip->write_data >> 4) & 0x01;
250  chip->patch.et[slot] = (chip->write_data >> 5) & 0x01;
251  chip->patch.vib[slot] = (chip->write_data >> 6) & 0x01;
252  chip->patch.am[slot] = (chip->write_data >> 7) & 0x01;
253  break;
254 
255  case 0x02:
256  chip->patch.ksl[0] = (chip->write_data >> 6) & 0x03;
257  chip->patch.tl = chip->write_data & 0x3f;
258  break;
259 
260  case 0x03:
261  chip->patch.ksl[1] = (chip->write_data >> 6) & 0x03;
262  chip->patch.dc = (chip->write_data >> 4) & 0x01;
263  chip->patch.dm = (chip->write_data >> 3) & 0x01;
264  chip->patch.fb = chip->write_data & 0x07;
265  break;
266 
267  case 0x04:
268  case 0x05:
269  chip->patch.dr[slot] = chip->write_data & 0x0f;
270  chip->patch.ar[slot] = (chip->write_data >> 4) & 0x0f;
271  break;
272 
273  case 0x06:
274  case 0x07:
275  chip->patch.rr[slot] = chip->write_data & 0x0f;
276  chip->patch.sl[slot] = (chip->write_data >> 4) & 0x0f;
277  break;
278 
279  case 0x0e:
280  chip->rhythm = chip->write_data & 0x3f;
281  if (chip->chip_type == opll_type_ds1001) {
282  chip->rhythm |= 0x20;
283  }
284  chip->rm_enable = (chip->rm_enable & 0x7f) | ((chip->rhythm << 2) & 0x80);
285  break;
286 
287  case 0x0f:
288  chip->testmode = chip->write_data & 0x0f;
289  break;
290  }
291  }
292 }
293 
294 void OPLL_Reset(opll_t *chip, uint32_t chip_type) {
295  uint32_t i;
296  memset(chip, 0, sizeof(opll_t));
297  chip->chip_type = chip_type;
298  if (chip_type == opll_type_ds1001) {
299  /* Rhythm mode is always on */
300  chip->rhythm = 0x20;
301  chip->rm_enable = int8_t(0x80);
302  }
303  switch (chip_type) {
304  case opll_type_ds1001:
305  chip->patchrom = patch_ds1001;
306  break;
307  case opll_type_ymf281:
308  case opll_type_ymf281b:
309  chip->patchrom = patch_ymf281;
310  break;
311  case opll_type_ym2423:
312  chip->patchrom = patch_ym2423;
313  break;
314  case opll_type_ym2413:
315  case opll_type_ym2413b:
316  case opll_type_ym2420:
317  default:
318  chip->patchrom = patch_ym2413;
319  break;
320  }
321  for (i = 0; i < 18; i++) {
322  chip->eg_state[i] = eg_num_release;
323  chip->eg_level[i] = 0x7f;
324  chip->eg_out = 0x7f;
325  }
326  chip->rm_select = rm_num_tc + 1;
327 }
328 
329 static void OPLL_DoRegWrite(opll_t *chip) {
330  uint32_t channel;
331 
332  /* Address */
333  if (chip->write_a_en) {
334  if ((chip->write_data & 0xc0) == 0x00) {
335  /* FM Write */
336  chip->write_fm_address = 1;
337  chip->address = chip->write_data;
338  } else {
339  chip->write_fm_address = 0;
340  }
341  }
342  /* Data */
343  if (chip->write_fm_address && chip->write_d_en) {
344  chip->data = chip->write_data;
345  }
346 
347  /* Update registers */
348  if (chip->write_fm_data && !chip->write_a_en) {
349  if ((chip->address & 0x0f) == chip->cycles && chip->cycles < 16) {
350  channel = chip->cycles % 9;
351  switch (chip->address & 0xf0) {
352  case 0x10:
353  if (chip->chip_type == opll_type_ym2420)
354  {
355  chip->fnum[channel] = (chip->fnum[channel] & 0x0f) | ((chip->data & 0x1f) << 4);
356  chip->block[channel] = (chip->data >> 5) & 0x07;
357  }
358  else
359  chip->fnum[channel] = (chip->fnum[channel] & 0x100) | chip->data;
360  break;
361  case 0x20:
362  if (chip->chip_type == opll_type_ym2420)
363  chip->fnum[channel] = (chip->fnum[channel] & 0x1f0) | (chip->data & 0x0f);
364  else
365  {
366  chip->fnum[channel] = (chip->fnum[channel] & 0xff) | ((chip->data & 0x01) << 8);
367  chip->block[channel] = (chip->data >> 1) & 0x07;
368  }
369  chip->kon[channel] = (chip->data >> 4) & 0x01;
370  chip->son[channel] = (chip->data >> 5) & 0x01;
371  break;
372  case 0x30:
373  chip->vol[channel] = chip->data & 0x0f;
374  chip->inst[channel] = (chip->data >> 4) & 0x0f;
375  break;
376  }
377  }
378  }
379 
380 
381  if (chip->write_a_en) {
382  chip->write_fm_data = 0;
383  }
384  if (chip->write_fm_address && chip->write_d_en) {
385  chip->write_fm_data = 1;
386  }
387  if (chip->write_a_en) {
388  if (((chip->write_data & 0xf0) == 0x00)) {
389  chip->write_mode_address = 0x10 | (chip->write_data & 0x0f);
390  } else {
391  chip->write_mode_address = 0x00;
392  }
393  }
394 
395 }
396 static void OPLL_PreparePatch1(opll_t *chip) {
397  uint8_t instr;
398  uint32_t mcsel = ((chip->cycles + 1) / 3) & 0x01;
399  uint32_t instr_index;
400  uint32_t ch = ch_offset[chip->cycles];
401  const opll_patch_t *patch;
402  instr = chip->inst[ch];
403  if (instr > 0) {
404  instr_index = opll_patch_1 + instr - 1;
405  }
406  if (chip->rm_select <= rm_num_tc) {
407  instr_index = opll_patch_drum_0 + chip->rm_select;
408  }
409  if (chip->rm_select <= rm_num_tc || instr > 0) {
410  patch = &chip->patchrom[instr_index];
411  } else {
412  patch = &chip->patch;
413  }
414  if (chip->rm_select == rm_num_hh || chip->rm_select == rm_num_tom) {
415  chip->c_tl = chip->inst[ch] << 2;
416  } else if (mcsel == 1) {
417  chip->c_tl = chip->vol[ch] << 2;
418  } else {
419  chip->c_tl = patch->tl;
420  }
421 
422  chip->c_adrr[0] = patch->ar[mcsel];
423  chip->c_adrr[1] = patch->dr[mcsel];
424  chip->c_adrr[2] = patch->rr[mcsel];
425  chip->c_et = patch->et[mcsel];
426  chip->c_ksr = patch->ksr[mcsel];
427  chip->c_ksl = patch->ksl[mcsel];
428  chip->c_ksr_freq = (chip->block[ch] << 1) | (chip->fnum[ch] >> 8);
429  chip->c_ksl_freq = (chip->fnum[ch]>>5);
430  chip->c_ksl_block = (chip->block[ch]);
431 }
432 
433 static void OPLL_PreparePatch2(opll_t *chip) {
434  uint8_t instr;
435  uint32_t mcsel = ((chip->cycles + 1) / 3) & 0x01;
436  uint32_t instr_index;
437  const opll_patch_t *patch;
438  instr = chip->inst[ch_offset[chip->cycles]];
439  if (instr > 0) {
440  instr_index = opll_patch_1 + instr - 1;
441  }
442  if (chip->rm_select <= rm_num_tc) {
443  instr_index = opll_patch_drum_0 + chip->rm_select;
444  }
445  if (chip->rm_select <= rm_num_tc || instr > 0) {
446  patch = &chip->patchrom[instr_index];
447  } else {
448  patch = &chip->patch;
449  }
450 
451  chip->c_fnum = chip->fnum[ch_offset[chip->cycles]];
452  chip->c_block = chip->block[ch_offset[chip->cycles]];
453 
454  chip->c_multi = patch->multi[mcsel];
455  chip->c_sl = patch->sl[mcsel];
456  chip->c_fb = patch->fb;
457  chip->c_vib = patch->vib[mcsel];
458  chip->c_am = patch->am[mcsel];
459  chip->c_dc <<= 1;
460  chip->c_dm <<= 1;
461  chip->c_dc |= patch->dc;
462  chip->c_dm |= patch->dm;
463 }
464 
465 static void OPLL_PhaseGenerate(opll_t *chip) {
466  uint32_t ismod;
467  uint32_t phase;
468  uint8_t rm_bit;
469  uint16_t pg_out;
470 
471  chip->pg_phase[(chip->cycles + 17) % 18] = chip->pg_phase_next + chip->pg_inc;
472 
473  if ((chip->rm_enable & 0x40) && (chip->cycles == 13 || chip->cycles == 14)) {
474  ismod = 0;
475  } else {
476  ismod = ((chip->cycles + 3) / 3) & 1;
477  }
478  phase = chip->pg_phase[chip->cycles];
479  /* KeyOn event check */
480  if ((chip->testmode & 0x04)
481  || (ismod && (chip->eg_dokon & 0x8000)) || (!ismod && (chip->eg_dokon & 0x01))) {
482  chip->pg_phase_next = 0;
483  } else {
484  chip->pg_phase_next = phase;
485  }
486  /* Rhythm mode */
487  if (chip->cycles == 13) {
488  chip->rm_hh_bit2 = (phase >> (2 + 9)) & 1;
489  chip->rm_hh_bit3 = (phase >> (3 + 9)) & 1;
490  chip->rm_hh_bit7 = (phase >> (7 + 9)) & 1;
491  chip->rm_hh_bit8 = (phase >> (8 + 9)) & 1;
492  } else if (chip->cycles == 17 && (chip->rm_enable & 0x80)) {
493  chip->rm_tc_bit3 = (phase >> (3 + 9)) & 1;
494  chip->rm_tc_bit5 = (phase >> (5 + 9)) & 1;
495  }
496  if ((chip->rm_enable & 0x80)) {
497  switch (chip->cycles) {
498  case 13:
499  /* HH */
500  rm_bit = (chip->rm_hh_bit2 ^ chip->rm_hh_bit7)
501  | (chip->rm_hh_bit3 ^ chip->rm_tc_bit5)
502  | (chip->rm_tc_bit3 ^ chip->rm_tc_bit5);
503  pg_out = rm_bit << 9;
504  if (rm_bit ^ (chip->rm_noise & 1)) {
505  pg_out |= 0xd0;
506  } else {
507  pg_out |= 0x34;
508  }
509  break;
510  case 16:
511  /* SD */
512  pg_out = (chip->rm_hh_bit8 << 9)
513  | ((chip->rm_hh_bit8 ^ (chip->rm_noise & 1)) << 8);
514  break;
515  case 17:
516  /* TC */
517  rm_bit = (chip->rm_hh_bit2 ^ chip->rm_hh_bit7)
518  | (chip->rm_hh_bit3 ^ chip->rm_tc_bit5)
519  | (chip->rm_tc_bit3 ^ chip->rm_tc_bit5);
520  pg_out = (rm_bit << 9) | 0x100;
521  break;
522  default:
523  pg_out = phase >> 9;
524  }
525  } else {
526  pg_out = phase >> 9;
527  }
528  chip->pg_out = pg_out;
529 }
530 
531 static void OPLL_PhaseCalcIncrement(opll_t *chip) {
532  uint32_t freq;
533  uint16_t block;
534  freq = chip->c_fnum << 1;
535  block = chip->c_block;
536  /* Apply vibrato */
537  if (chip->c_vib) {
538  switch (chip->lfo_vib_counter) {
539  case 0:
540  case 4:
541  break;
542  case 1:
543  case 3:
544  freq += freq >> 8;
545  break;
546  case 2:
547  freq += freq >> 7;
548  break;
549  case 5:
550  case 7:
551  freq -= freq >> 8;
552  break;
553  case 6:
554  freq -= freq >> 7;
555  break;
556  }
557  }
558  /* Apply block */
559  freq = (freq << block) >> 1;
560 
561  chip->pg_inc = (freq * pg_multi[chip->c_multi]) >> 1;
562 }
563 
564 static void OPLL_EnvelopeKSLTL(opll_t *chip)
565 {
566  int32_t ksl;
567 
568  ksl = eg_ksltable[chip->c_ksl_freq]-((8-chip->c_ksl_block)<<3);
569  if (ksl < 0) {
570  ksl = 0;
571  }
572 
573  ksl <<= 1;
574 
575  if (chip->c_ksl) {
576  ksl = ksl >> (3-chip->c_ksl);
577  } else {
578  ksl = 0;
579  }
580 
581  chip->eg_ksltl = ksl + (chip->c_tl<<1);
582 }
583 
584 static void OPLL_EnvelopeOutput(opll_t *chip)
585 {
586  int32_t level = chip->eg_level[(chip->cycles+17)%18];
587 
588  level += chip->eg_ksltl;
589 
590  if (chip->c_am) {
591  level += chip->lfo_am_out;
592  }
593 
594  if (level >= 128) {
595  level = 127;
596  }
597 
598  if (chip->testmode & 0x01) {
599  level = 0;
600  }
601 
602  chip->eg_out = level;
603 }
604 
605 static void OPLL_EnvelopeGenerate(opll_t *chip) {
606  uint8_t timer_inc;
607  uint8_t timer_bit;
608  uint8_t timer_low;
609  uint8_t rate;
610  uint8_t state_rate;
611  uint8_t ksr;
612  uint8_t sum;
613  uint8_t rate_hi;
614  uint8_t rate_lo;
615  int32_t level;
616  int32_t next_level;
617  uint8_t zero;
618  uint8_t state;
619  uint8_t next_state;
620  int32_t step;
621  int32_t sl;
622  uint32_t mcsel = ((chip->cycles + 1) / 3) & 0x01;
623 
624 
625  /* EG timer */
626  if ((chip->eg_counter_state & 3) != 3) {
627  timer_inc = 0;
628  } else if (chip->cycles == 0) {
629  timer_inc = 1;
630  } else {
631  timer_inc = chip->eg_timer_carry;
632  }
633  timer_low = chip->eg_timer & 3;
634  timer_bit = chip->eg_timer & 1;
635  timer_bit += timer_inc;
636  chip->eg_timer_carry = timer_bit >> 1;
637  chip->eg_timer = ((timer_bit & 1) << 17) | (chip->eg_timer >> 1);
638  if (chip->testmode & 0x08) {
639  chip->eg_timer &= 0x2ffff;
640  chip->eg_timer |= (chip->write_data << (16 - 2)) & 0x10000;
641  }
642  if (!chip->eg_timer_shift_stop && ((chip->eg_timer >> 16) & 1)) {
643  chip->eg_timer_shift = chip->cycles;
644  }
645  if (chip->cycles == 0 && (chip->eg_counter_state_prev & 1) == 1) {
646  chip->eg_timer_low_lock = timer_low;
647  chip->eg_timer_shift_lock = chip->eg_timer_shift;
648  if (chip->eg_timer_shift_lock > 13)
649  chip->eg_timer_shift_lock = 0;
650 
651  chip->eg_timer_shift = 0;
652  }
653  chip->eg_timer_shift_stop |= (chip->eg_timer >> 16) & 1;
654  if (chip->cycles == 0) {
655  chip->eg_timer_shift_stop = 0;
656  }
658  if (chip->cycles == 17) {
659  chip->eg_counter_state++;
660  }
661 
662  level = chip->eg_level[(chip->cycles+16)%18];
663  next_level = level;
664  zero = level == 0;
665  chip->eg_silent = level == 0x7f;
666 
667  if (chip->eg_state[(chip->cycles+16)%18] != eg_num_attack && (chip->eg_off&2) && !(chip->eg_dokon&2)) {
668  next_level = 0x7f;
669  }
670 
671  if (chip->eg_maxrate && (chip->eg_dokon&2)) {
672  next_level = 0x00;
673  }
674 
675 
676  state = chip->eg_state[(chip->cycles+16)%18];
677  next_state = eg_num_attack;
678 
679  step = 0;
680  sl = chip->eg_sl;
681 
682  switch (state) {
683  case eg_num_attack:
684  if (!chip->eg_maxrate && (chip->eg_kon & 2) && !zero) {
685  int32_t shift = chip->eg_rate_hi - 11 + chip->eg_inc_hi;
686  if (chip->eg_inc_lo) {
687  shift = 1;
688  }
689  if (shift > 0) {
690  if (shift > 4)
691  shift = 4;
692  step = ~level >> (5 - shift);
693  }
694  }
695  if (zero) {
696  next_state = eg_num_decay;
697  } else {
698  next_state = eg_num_attack;
699  }
700  break;
701  case eg_num_decay:
702  if (!(chip->eg_off & 2) && !(chip->eg_dokon & 2) && (level >> 3) != sl)
703  {
704  uint8_t i0 = chip->eg_rate_hi == 15 || (chip->eg_rate_hi == 14 && chip->eg_inc_hi);
705  uint8_t i1 = (chip->eg_rate_hi == 14 && !chip->eg_inc_hi) || (chip->eg_rate_hi == 13 && chip->eg_inc_hi) ||
706  (chip->eg_rate_hi == 13 && !chip->eg_inc_hi && (chip->eg_counter_state_prev & 1))
707  || (chip->eg_rate_hi == 12 && chip->eg_inc_hi && (chip->eg_counter_state_prev & 1))
708  || (chip->eg_rate_hi == 12 && !chip->eg_inc_hi && ((chip->eg_counter_state_prev & 3) == 3))
709  || (chip->eg_inc_lo && ((chip->eg_counter_state_prev & 3) == 3));
710  step = (i0<<1) | i1;
711  }
712  if ((level >> 3) == sl) {
713  next_state = eg_num_sustain;
714  } else {
715  next_state = eg_num_decay;
716  }
717  break;
718  case eg_num_sustain:
719  case eg_num_release:
720  if (!(chip->eg_off & 2) && !(chip->eg_dokon & 2))
721  {
722  uint8_t i0 = chip->eg_rate_hi == 15 || (chip->eg_rate_hi == 14 && chip->eg_inc_hi);
723  uint8_t i1 = (chip->eg_rate_hi == 14 && !chip->eg_inc_hi) || (chip->eg_rate_hi == 13 && chip->eg_inc_hi) ||
724  (chip->eg_rate_hi == 13 && !chip->eg_inc_hi && (chip->eg_counter_state_prev & 1))
725  || (chip->eg_rate_hi == 12 && chip->eg_inc_hi && (chip->eg_counter_state_prev & 1))
726  || (chip->eg_rate_hi == 12 && !chip->eg_inc_hi && ((chip->eg_counter_state_prev & 3) == 3))
727  || (chip->eg_inc_lo && ((chip->eg_counter_state_prev & 3) == 3));
728  step = (i0<<1) | i1;
729  }
730  next_state = state;
731  break;
732  }
733 
734  if (!(chip->eg_kon & 2)) {
735  next_state = eg_num_release;
736  }
737  if (chip->eg_dokon & 2) {
738  next_state = eg_num_attack;
739  }
740 
741  chip->eg_level[(chip->cycles+16)%18] = next_level+step;
742  chip->eg_state[(chip->cycles+16)%18] = next_state;
743 
744  rate_hi = chip->eg_rate >> 2;
745  rate_lo = chip->eg_rate & 3;
746  chip->eg_inc_hi = eg_stephi[rate_lo][chip->eg_timer_low_lock];
747  sum = (chip->eg_timer_shift_lock + rate_hi) & 0x0f;
748  chip->eg_inc_lo = 0;
749  if (rate_hi < 12 && !chip->eg_zerorate) {
750  switch (sum) {
751  case 12:
752  chip->eg_inc_lo = 1;
753  break;
754  case 13:
755  chip->eg_inc_lo = (rate_lo >> 1) & 1;
756  break;
757  case 14:
758  chip->eg_inc_lo = rate_lo & 1;
759  break;
760  }
761  }
762  chip->eg_maxrate = rate_hi == 0x0f;
763 
764  chip->eg_rate_hi = rate_hi;
765 
766  chip->eg_kon <<= 1;
767  chip->eg_kon |= chip->kon[ch_offset[chip->cycles]];
768  chip->eg_off <<= 1;
769  chip->eg_off |= (chip->eg_level[chip->cycles] >> 2) == 0x1f;
770  switch (chip->rm_select) {
771  case rm_num_bd0:
772  case rm_num_bd1:
773  chip->eg_kon |= (chip->rhythm >> 4) & 1;
774  break;
775  case rm_num_sd:
776  chip->eg_kon |= (chip->rhythm >> 3) & 1;
777  break;
778  case rm_num_tom:
779  chip->eg_kon |= (chip->rhythm >> 2) & 1;
780  break;
781  case rm_num_tc:
782  chip->eg_kon |= (chip->rhythm >> 1) & 1;
783  break;
784  case rm_num_hh:
785  chip->eg_kon |= chip->rhythm & 1;
786  break;
787  }
788 
789  /* Calculate rate */
790  rate = 0;
791  chip->eg_dokon <<= 1;
792  state_rate = chip->eg_state[chip->cycles];
793  if (state_rate == eg_num_release && (chip->eg_kon&1) && (chip->eg_off&1)) {
794  state_rate = eg_num_attack;
795  chip->eg_dokon |= 1;
796  }
797  switch (state_rate) {
798  case eg_num_attack:
799  rate = chip->c_adrr[0];
800  break;
801  case eg_num_decay:
802  rate = chip->c_adrr[1];
803  break;
804  case eg_num_sustain:
805  if (!chip->c_et) {
806  rate = chip->c_adrr[2];
807  }
808  break;
809  case eg_num_release:
810  if (chip->son[ch_offset[chip->cycles]]) {
811  rate = 5;
812  } else {
813  rate = chip->c_adrr[2];
814  }
815  break;
816  }
817  if (!(chip->eg_kon&1) && !mcsel && chip->rm_select != rm_num_tom && chip->rm_select != rm_num_hh) {
818  rate = 0;
819  }
820  if ((chip->eg_kon&1) && chip->eg_state[chip->cycles] == eg_num_release && !(chip->eg_off&1)) {
821  rate = 12;
822  }
823  if (!(chip->eg_kon&1) && !chip->son[ch_offset[chip->cycles]] && mcsel == 1 && !chip->c_et) {
824  rate = 7;
825  }
826  chip->eg_zerorate = rate == 0;
827  ksr = chip->c_ksr_freq;
828  if (!chip->c_ksr)
829  ksr >>= 2;
830  chip->eg_rate = (rate << 2) + ksr;
831  if (chip->eg_rate & 0x40) {
832  chip->eg_rate = 0x3c | (ksr & 3);
833  }
834  chip->eg_sl = chip->c_sl;
835 }
836 
837 static void OPLL_Channel(opll_t *chip) {
838  int16_t sign;
839  int16_t ch_out = chip->ch_out;
840  uint8_t ismod = (chip->cycles / 3) & 1;
841  uint8_t mute_m = ismod || ((chip->rm_enable&0x40) && (chip->cycles+15)%18 >= 12);
842  uint8_t mute_r = 1;
843  if (chip->chip_type == opll_type_ds1001) {
844  chip->output_m = ch_out;
845  if (chip->output_m >= 0) {
846  chip->output_m++;
847  }
848  if (mute_m) {
849  chip->output_m = 0;
850  }
851  chip->output_r = 0;
852  return;
853  } else {
854  /* TODO: This might be incorrect */
855  if ((chip->rm_enable & 0x40)) {
856  switch (chip->cycles) {
857  case 16: /* HH */
858  case 17: /* TOM */
859  case 0: /* BD */
860  case 1: /* SD */
861  case 2: /* TC */
862  case 3: /* HH */
863  case 4: /* TOM */
864  case 5: /* BD */
865  case 9: /* TOM */
866  case 10: /* TOM */
867  mute_r = 0;
868  break;
869  }
870  }
871  if (chip->chip_type == opll_type_ym2413b || chip->chip_type == opll_type_ymf281b) {
872  if (mute_m)
873  chip->output_m = 0;
874  else
875  chip->output_m = ch_out;
876  if (mute_r)
877  chip->output_r = 0;
878  else
879  chip->output_r = ch_out;
880  } else {
881  sign = ch_out >> 8;
882  if (ch_out >= 0) {
883  ch_out++;
884  sign++;
885  }
886  if (mute_m)
887  chip->output_m = sign;
888  else
889  chip->output_m = ch_out;
890  if (mute_r)
891  chip->output_r = sign;
892  else
893  chip->output_r = ch_out;
894  }
895  }
896 }
897 
898 static void OPLL_Operator(opll_t *chip) {
899  uint8_t ismod1, ismod2, ismod3;
900  uint32_t op_mod;
901  uint16_t exp_shift;
902  int16_t output;
903  uint32_t level;
904  uint32_t phase;
905  int16_t routput;
906  if ((chip->rm_enable & 0x80) && (chip->cycles == 15 || chip->cycles == 16)) {
907  ismod1 = 0;
908  } else {
909  ismod1 = ((chip->cycles + 1) / 3) & 1;
910  }
911  if ((chip->rm_enable & 0x40) && (chip->cycles == 13 || chip->cycles == 14)) {
912  ismod2 = 0;
913  } else {
914  ismod2 = ((chip->cycles + 3) / 3) & 1;
915  }
916  if ((chip->rm_enable & 0x40) && (chip->cycles == 16 || chip->cycles == 17)) {
917  ismod3 = 0;
918  } else {
919  ismod3 = (chip->cycles / 3) & 1;
920  }
921 
922  op_mod = 0;
923 
924  if (ismod3) {
925  op_mod |= chip->op_mod << 1;
926  }
927 
928  if (ismod2 && chip->c_fb) {
929  op_mod |= chip->op_fbsum >> (7 - chip->c_fb);
930  }
931 
932  exp_shift = chip->op_exp_s;
933  if (chip->eg_silent || ((chip->op_neg&2) && (ismod1 ? (chip->c_dm&4) : (chip->c_dc&4)))) {
934  exp_shift |= 12;
935  }
936 
937  output = chip->op_exp_m>>exp_shift;
938  if (!chip->eg_silent && (chip->op_neg&2)) {
939  output = ~output;
940  }
941 
942  level = chip->op_logsin+(chip->eg_out<<4);
943  if (level >= 4096) {
944  level = 4095;
945  }
946 
947  chip->op_exp_m = exprom[level & 0xff];
948  chip->op_exp_s = level >> 8;
949 
950  phase = (op_mod + chip->pg_out) & 0x3ff;
951  if (phase & 0x100) {
952  phase ^= 0xff;
953  }
954  chip->op_logsin = logsinrom[phase & 0xff];
955  chip->op_neg <<= 1;
956  chip->op_neg |= phase >> 9;
957  chip->op_fbsum = (chip->op_fb1[(chip->cycles + 3) % 9] + chip->op_fb2[(chip->cycles + 3) % 9]) >> 1;
958 
959  if (ismod1) {
960  chip->op_fb2[chip->cycles%9] = chip->op_fb1[chip->cycles%9];
961  chip->op_fb1[chip->cycles%9] = output;
962  }
963  chip->op_mod = output&0x1ff;
964 
965  if (chip->chip_type == opll_type_ds1001) {
966  routput = 0;
967  } else {
968  switch (chip->cycles) {
969  case 2:
970  routput = chip->ch_out_hh;
971  break;
972  case 3:
973  routput = chip->ch_out_tm;
974  break;
975  case 4:
976  routput = chip->ch_out_bd;
977  break;
978  case 8:
979  routput = chip->ch_out_sd;
980  break;
981  case 9:
982  routput = chip->ch_out_tc;
983  break;
984  default:
985  routput = 0; /* TODO: Not quite true */
986  break;
987  }
988  switch (chip->cycles) {
989  case 15:
990  chip->ch_out_hh = output>>3;
991  break;
992  case 16:
993  chip->ch_out_tm = output>>3;
994  break;
995  case 17:
996  chip->ch_out_bd = output>>3;
997  break;
998  case 0:
999  chip->ch_out_sd = output>>3;
1000  break;
1001  case 1:
1002  chip->ch_out_tc = output>>3;
1003  break;
1004  default:
1005  break;
1006  }
1007  }
1008 
1009  chip->ch_out = ismod1 ? routput : (output>>3);
1010 }
1011 
1012 static void OPLL_DoRhythm(opll_t *chip) {
1013  uint8_t nbit;
1014 
1015  /* Noise */
1016  nbit = (chip->rm_noise ^ (chip->rm_noise >> 14)) & 0x01;
1017  nbit |= (chip->rm_noise == 0x00) | ((chip->testmode >> 1) & 0x01);
1018  chip->rm_noise = (nbit << 22) | (chip->rm_noise >> 1);
1019 }
1020 
1021 static void OPLL_DoLFO(opll_t *chip) {
1022  uint8_t vib_step;
1023  uint8_t am_inc = 0;
1024  uint8_t am_bit;
1025 
1026  /* Update counter */
1027  if (chip->cycles == 17) {
1028  vib_step = ((chip->lfo_counter & 0x3ff) + 1) >> 10;
1029  chip->lfo_am_step = ((chip->lfo_counter & 0x3f) + 1) >> 6;
1030  vib_step |= (chip->testmode >> 3) & 0x01;
1031  chip->lfo_vib_counter += vib_step;
1032  chip->lfo_vib_counter &= 0x07;
1033  chip->lfo_counter++;
1034  }
1035 
1036  /* LFO AM */
1037  if ((chip->lfo_am_step || (chip->testmode & 0x08)) && chip->cycles < 9) {
1038  am_inc = chip->lfo_am_dir | (chip->cycles == 0);
1039  }
1040 
1041  if (chip->cycles >= 9) {
1042  chip->lfo_am_car = 0;
1043  }
1044 
1045  if (chip->cycles == 0) {
1046  if (chip->lfo_am_dir && (chip->lfo_am_counter & 0x7f) == 0) {
1047  chip->lfo_am_dir = 0;
1048  } else if (!chip->lfo_am_dir && (chip->lfo_am_counter & 0x69) == 0x69) {
1049  chip->lfo_am_dir = 1;
1050  }
1051  }
1052 
1053  am_bit = chip->lfo_am_counter & 0x01;
1054  am_bit += am_inc + chip->lfo_am_car;
1055  chip->lfo_am_car = am_bit >> 1;
1056  am_bit &= 0x01;
1057  chip->lfo_am_counter = (am_bit << 8) | (chip->lfo_am_counter >> 1);
1058 
1059 
1060  /* Reset LFO */
1061  if (chip->testmode & 0x02) {
1062  chip->lfo_vib_counter = 0;
1063  chip->lfo_counter = 0;
1064  chip->lfo_am_dir = 0;
1065  chip->lfo_am_counter &= 0xff;
1066  }
1067 }
1068 
1069 
1070 void OPLL_Clock(opll_t *chip, int32_t *buffer) {
1071  buffer[0] = chip->output_m;
1072  buffer[1] = chip->output_r;
1073  if (chip->cycles == 0) {
1074  chip->lfo_am_out = (chip->lfo_am_counter >> 3) & 0x0f;
1075  }
1076  chip->rm_enable >>= 1;
1077  OPLL_DoModeWrite(chip);
1078  chip->rm_select++;
1079  if (chip->rm_select > rm_num_tc) {
1080  chip->rm_select = rm_num_tc + 1;
1081  }
1082  if (chip->cycles == 11 && (chip->rm_enable & 0x80) == 0x80) {
1083  chip->rm_select = rm_num_bd0;
1084  }
1085  OPLL_PreparePatch1(chip);
1086 
1087  OPLL_Channel(chip);
1088 
1089  OPLL_PhaseGenerate(chip);
1090 
1091  OPLL_Operator(chip);
1092 
1093  OPLL_PhaseCalcIncrement(chip);
1094 
1095  OPLL_EnvelopeOutput(chip);
1096  OPLL_EnvelopeKSLTL(chip);
1097  OPLL_EnvelopeGenerate(chip);
1098 
1099  OPLL_DoLFO(chip);
1100  OPLL_DoRhythm(chip);
1101  OPLL_PreparePatch2(chip);
1102  OPLL_DoRegWrite(chip);
1103  OPLL_DoIO(chip);
1104  chip->cycles = (chip->cycles + 1) % 18;
1105 
1106 }
1107 
1108 
1109 void OPLL_Write(opll_t *chip, uint32_t port, uint8_t data) {
1110  chip->write_data = data;
1111  if (port & 1) {
1112  /* Data */
1113  chip->write_d |= 1;
1114  } else {
1115  /* Address */
1116  chip->write_a |= 1;
1117  }
1118 }
opll_t::eg_out
uint8_t eg_out
Definition: opll.hh:118
opll_t::rm_hh_bit8
uint8_t rm_hh_bit8
Definition: opll.hh:187
opll_t::rm_hh_bit2
uint8_t rm_hh_bit2
Definition: opll.hh:184
opll.hh
opll_t::op_mod
int16_t op_mod
Definition: opll.hh:131
rm_num_bd1
@ rm_num_bd1
Definition: opll.cc:37
opll_patch_t::ar
uint8_t ar[2]
Definition: opll.hh:74
opll_t::patchrom
const opll_patch_t * patchrom
Definition: opll.hh:84
opll_patch_t::dr
uint8_t dr[2]
Definition: opll.hh:75
opll_t::write_d
uint8_t write_d
Definition: opll.hh:88
eg_num_release
@ eg_num_release
Definition: opll.cc:30
opll_t::eg_dokon
uint32_t eg_dokon
Definition: opll.hh:108
opll_type_ym2413b
@ opll_type_ym2413b
Definition: opll.hh:31
opll_t::rm_hh_bit3
uint8_t rm_hh_bit3
Definition: opll.hh:185
opll_t::lfo_am_car
uint8_t lfo_am_car
Definition: opll.hh:149
opll_patch_t::sl
uint8_t sl[2]
Definition: opll.hh:76
opll_t::write_d_en
uint8_t write_d_en
Definition: opll.hh:90
rm_num_tc
@ rm_num_tc
Definition: opll.cc:39
opll_t::rm_noise
uint32_t rm_noise
Definition: opll.hh:182
opll_t::c_et
uint8_t c_et
Definition: opll.hh:169
OPLL_Clock
void OPLL_Clock(opll_t *chip, int32_t *buffer)
Definition: opll.cc:1070
opll_t::rm_tc_bit5
uint8_t rm_tc_bit5
Definition: opll.hh:189
opll_t::pg_out
uint16_t pg_out
Definition: opll.hh:123
opll_t::son
uint8_t son[9]
Definition: opll.hh:155
opll_patch_t::ksl
uint8_t ksl[2]
Definition: opll.hh:73
opll_patch_drum_0
@ opll_patch_drum_0
Definition: opll.hh:54
opll_t::eg_ksltl
uint16_t eg_ksltl
Definition: opll.hh:117
opll_t::write_a
uint8_t write_a
Definition: opll.hh:87
opll_t::c_ksl_block
uint8_t c_ksl_block
Definition: opll.hh:173
opll_t::testmode
uint8_t testmode
Definition: opll.hh:159
opll_t::eg_timer_shift_stop
uint8_t eg_timer_shift_stop
Definition: opll.hh:104
opll_t::c_adrr
uint8_t c_adrr[3]
Definition: opll.hh:176
opll_t::lfo_am_dir
uint8_t lfo_am_dir
Definition: opll.hh:148
opll_t::eg_timer_shift
uint8_t eg_timer_shift
Definition: opll.hh:102
opll_t::c_fb
uint8_t c_fb
Definition: opll.hh:166
opll_t::eg_inc_hi
uint8_t eg_inc_hi
Definition: opll.hh:114
opll_t::write_fm_data
uint8_t write_fm_data
Definition: opll.hh:92
step
constexpr auto step
Definition: eeprom.cc:9
opll_type_ymf281
@ opll_type_ymf281
Definition: opll.hh:32
opll_t::c_ksl
uint8_t c_ksl
Definition: opll.hh:175
opll_t::address
uint8_t address
Definition: opll.hh:94
opll_t::eg_silent
uint8_t eg_silent
Definition: opll.hh:119
opll_patch_t::dc
uint8_t dc
Definition: opll.hh:65
opll_t::lfo_vib_counter
uint8_t lfo_vib_counter
Definition: opll.hh:145
opll_t::eg_timer_low_lock
uint8_t eg_timer_low_lock
Definition: opll.hh:100
opll_t::data
uint8_t data
Definition: opll.hh:95
opll_t::eg_counter_state
uint8_t eg_counter_state
Definition: opll.hh:97
opll_t::eg_kon
uint8_t eg_kon
Definition: opll.hh:107
opll_t::rm_hh_bit7
uint8_t rm_hh_bit7
Definition: opll.hh:186
opll_t::c_multi
uint8_t c_multi
Definition: opll.hh:174
opll_t::fnum
uint16_t fnum[9]
Definition: opll.hh:152
opll_t::ch_out
int16_t ch_out
Definition: opll.hh:137
opll_t::kon
uint8_t kon[9]
Definition: opll.hh:154
opll_patch_t::am
uint8_t am[2]
Definition: opll.hh:68
opll_t::pg_inc
uint32_t pg_inc
Definition: opll.hh:124
opll_t::c_ksr
uint8_t c_ksr
Definition: opll.hh:170
opll_t::cycles
uint32_t cycles
Definition: opll.hh:82
opll_patch_t
Definition: opll.hh:63
opll_type_ymf281b
@ opll_type_ymf281b
Definition: opll.hh:33
opll_t::eg_rate_hi
uint8_t eg_rate_hi
Definition: opll.hh:115
opll_t::c_ksl_freq
uint8_t c_ksl_freq
Definition: opll.hh:172
opll_type_ds1001
@ opll_type_ds1001
Definition: opll.hh:30
opll_t::op_fb1
int16_t op_fb1[9]
Definition: opll.hh:128
opll_t::c_dm
uint8_t c_dm
Definition: opll.hh:165
rm_num_sd
@ rm_num_sd
Definition: opll.cc:38
opll_type_ym2420
@ opll_type_ym2420
Definition: opll.hh:34
opll_t::ch_out_hh
int16_t ch_out_hh
Definition: opll.hh:138
OPLL_Reset
void OPLL_Reset(opll_t *chip, uint32_t chip_type)
Definition: opll.cc:294
opll_t::ch_out_bd
int16_t ch_out_bd
Definition: opll.hh:140
opll_t::rm_select
uint32_t rm_select
Definition: opll.hh:183
eg_num_decay
@ eg_num_decay
Definition: opll.cc:28
opll_t::eg_state
uint8_t eg_state[18]
Definition: opll.hh:105
opll_t::ch_out_tc
int16_t ch_out_tc
Definition: opll.hh:142
opll_patch_1
@ opll_patch_1
Definition: opll.hh:39
opll_t::ch_out_sd
int16_t ch_out_sd
Definition: opll.hh:141
OPLL_Write
void OPLL_Write(opll_t *chip, uint32_t port, uint8_t data)
Definition: opll.cc:1109
opll_t::op_exp_s
uint16_t op_exp_s
Definition: opll.hh:135
opll_t::eg_sl
uint16_t eg_sl
Definition: opll.hh:116
opll_patch_t::ksr
uint8_t ksr[2]
Definition: opll.hh:71
opll_t::c_dc
uint8_t c_dc
Definition: opll.hh:164
opll_t::write_mode_address
uint8_t write_mode_address
Definition: opll.hh:93
opll_t::op_neg
uint8_t op_neg
Definition: opll.hh:132
opll_t::c_tl
uint8_t c_tl
Definition: opll.hh:163
opll_t::pg_phase_next
uint32_t pg_phase_next
Definition: opll.hh:126
opll_patch_t::et
uint8_t et[2]
Definition: opll.hh:70
opll_patch_t::rr
uint8_t rr[2]
Definition: opll.hh:77
opll_t::eg_level
uint8_t eg_level[18]
Definition: opll.hh:106
opll_t::op_exp_m
uint16_t op_exp_m
Definition: opll.hh:134
opll_t::chip_type
uint32_t chip_type
Definition: opll.hh:81
opll_t::c_am
uint8_t c_am
Definition: opll.hh:167
opll_patch_max
@ opll_patch_max
Definition: opll.hh:60
rm_num_tom
@ rm_num_tom
Definition: opll.cc:36
opll_t::lfo_counter
uint16_t lfo_counter
Definition: opll.hh:144
opll_t::lfo_am_counter
uint16_t lfo_am_counter
Definition: opll.hh:146
eg_num_sustain
@ eg_num_sustain
Definition: opll.cc:29
opll_t::write_fm_address
uint8_t write_fm_address
Definition: opll.hh:91
opll_type_ym2423
@ opll_type_ym2423
Definition: opll.hh:35
opll_t
Definition: opll.hh:80
opll_t::c_fnum
uint16_t c_fnum
Definition: opll.hh:178
opll_t::inst
uint8_t inst[9]
Definition: opll.hh:157
opll_t::write_data
uint8_t write_data
Definition: opll.hh:86
opll_patch_t::tl
uint8_t tl
Definition: opll.hh:64
opll_t::op_fbsum
int16_t op_fbsum
Definition: opll.hh:130
opll_t::eg_counter_state_prev
uint8_t eg_counter_state_prev
Definition: opll.hh:98
opll_t::c_sl
uint8_t c_sl
Definition: opll.hh:177
opll_type_ym2413
@ opll_type_ym2413
Definition: opll.hh:29
opll_t::eg_off
uint8_t eg_off
Definition: opll.hh:109
opll_t::c_vib
uint8_t c_vib
Definition: opll.hh:168
opll_t::vol
uint8_t vol[9]
Definition: opll.hh:156
opll_t::eg_timer_shift_lock
uint8_t eg_timer_shift_lock
Definition: opll.hh:103
opll_t::pg_phase
uint32_t pg_phase[18]
Definition: opll.hh:125
opll_t::c_block
uint16_t c_block
Definition: opll.hh:179
opll_t::output_r
int16_t output_r
Definition: opll.hh:192
opll_t::output_m
int16_t output_m
Definition: opll.hh:191
opll_patch_t::dm
uint8_t dm
Definition: opll.hh:66
opll_t::ch_out_tm
int16_t ch_out_tm
Definition: opll.hh:139
opll_t::eg_maxrate
uint8_t eg_maxrate
Definition: opll.hh:111
eg_num_attack
@ eg_num_attack
Definition: opll.cc:27
opll_t::rm_tc_bit3
uint8_t rm_tc_bit3
Definition: opll.hh:188
opll_t::rm_enable
int8_t rm_enable
Definition: opll.hh:181
opll_t::block
uint8_t block[9]
Definition: opll.hh:153
opll_patch_t::fb
uint8_t fb
Definition: opll.hh:67
opll_t::eg_timer_carry
uint8_t eg_timer_carry
Definition: opll.hh:101
opll_t::write_a_en
uint8_t write_a_en
Definition: opll.hh:89
opll_t::op_logsin
uint16_t op_logsin
Definition: opll.hh:133
opll_t::eg_inc_lo
uint8_t eg_inc_lo
Definition: opll.hh:113
opll_t::op_fb2
int16_t op_fb2[9]
Definition: opll.hh:129
opll_t::eg_zerorate
uint8_t eg_zerorate
Definition: opll.hh:112
rm_num_hh
@ rm_num_hh
Definition: opll.cc:35
opll_patch_t::multi
uint8_t multi[2]
Definition: opll.hh:72
opll_t::c_ksr_freq
uint8_t c_ksr_freq
Definition: opll.hh:171
sum
auto sum(InputRange &&range)
Definition: stl.hh:293
opll_t::eg_timer
uint32_t eg_timer
Definition: opll.hh:99
opll_patch_t::vib
uint8_t vib[2]
Definition: opll.hh:69
opll_t::eg_rate
uint8_t eg_rate
Definition: opll.hh:110
opll_t::rhythm
uint8_t rhythm
Definition: opll.hh:158
opll_t::patch
opll_patch_t patch
Definition: opll.hh:160
opll_t::lfo_am_step
uint8_t lfo_am_step
Definition: opll.hh:147
opll_t::lfo_am_out
uint8_t lfo_am_out
Definition: opll.hh:150
rm_num_bd0
@ rm_num_bd0
Definition: opll.cc:34